31600 lines
1.1 MiB
31600 lines
1.1 MiB
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weather_shield.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0000e088 08000190 08000190 00010190 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 000005c0 0800e218 0800e218 0001e218 2**3
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800e7d8 0800e7d8 0002044c 2**0
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CONTENTS
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4 .ARM 00000008 0800e7d8 0800e7d8 0001e7d8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 0800e7e0 0800e7e0 0002044c 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800e7e0 0800e7e0 0001e7e0 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 0800e7e4 0800e7e4 0001e7e4 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 0000044c 20000000 0800e7e8 00020000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000640 2000044c 0800ec34 0002044c 2**2
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ALLOC
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10 ._user_heap_stack 00000604 20000a8c 0800ec34 00020a8c 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0002044c 2**0
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CONTENTS, READONLY
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12 .debug_info 0002438d 00000000 00000000 0002047c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 000047c8 00000000 00000000 00044809 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00001878 00000000 00000000 00048fd8 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_ranges 00001680 00000000 00000000 0004a850 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 0002f8dd 00000000 00000000 0004bed0 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 0001d621 00000000 00000000 0007b7ad 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 001091cd 00000000 00000000 00098dce 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000053 00000000 00000000 001a1f9b 2**0
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CONTENTS, READONLY
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20 .debug_frame 000078e0 00000000 00000000 001a1ff0 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000190 <__do_global_dtors_aux>:
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8000190: b510 push {r4, lr}
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8000192: 4c05 ldr r4, [pc, #20] ; (80001a8 <__do_global_dtors_aux+0x18>)
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8000194: 7823 ldrb r3, [r4, #0]
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8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16>
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8000198: 4b04 ldr r3, [pc, #16] ; (80001ac <__do_global_dtors_aux+0x1c>)
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800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12>
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800019c: 4804 ldr r0, [pc, #16] ; (80001b0 <__do_global_dtors_aux+0x20>)
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800019e: f3af 8000 nop.w
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80001a2: 2301 movs r3, #1
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80001a4: 7023 strb r3, [r4, #0]
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80001a6: bd10 pop {r4, pc}
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80001a8: 2000044c .word 0x2000044c
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80001ac: 00000000 .word 0x00000000
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80001b0: 0800e200 .word 0x0800e200
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080001b4 <frame_dummy>:
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80001b4: b508 push {r3, lr}
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80001b6: 4b03 ldr r3, [pc, #12] ; (80001c4 <frame_dummy+0x10>)
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80001b8: b11b cbz r3, 80001c2 <frame_dummy+0xe>
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80001ba: 4903 ldr r1, [pc, #12] ; (80001c8 <frame_dummy+0x14>)
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80001bc: 4803 ldr r0, [pc, #12] ; (80001cc <frame_dummy+0x18>)
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80001be: f3af 8000 nop.w
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80001c2: bd08 pop {r3, pc}
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80001c4: 00000000 .word 0x00000000
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80001c8: 20000450 .word 0x20000450
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80001cc: 0800e200 .word 0x0800e200
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080001d0 <strlen>:
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80001d0: 4603 mov r3, r0
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80001d2: f813 2b01 ldrb.w r2, [r3], #1
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80001d6: 2a00 cmp r2, #0
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80001d8: d1fb bne.n 80001d2 <strlen+0x2>
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80001da: 1a18 subs r0, r3, r0
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80001dc: 3801 subs r0, #1
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80001de: 4770 bx lr
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080001e0 <memchr>:
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80001e0: f001 01ff and.w r1, r1, #255 ; 0xff
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80001e4: 2a10 cmp r2, #16
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80001e6: db2b blt.n 8000240 <memchr+0x60>
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80001e8: f010 0f07 tst.w r0, #7
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80001ec: d008 beq.n 8000200 <memchr+0x20>
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80001ee: f810 3b01 ldrb.w r3, [r0], #1
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80001f2: 3a01 subs r2, #1
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80001f4: 428b cmp r3, r1
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80001f6: d02d beq.n 8000254 <memchr+0x74>
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80001f8: f010 0f07 tst.w r0, #7
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80001fc: b342 cbz r2, 8000250 <memchr+0x70>
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80001fe: d1f6 bne.n 80001ee <memchr+0xe>
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8000200: b4f0 push {r4, r5, r6, r7}
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8000202: ea41 2101 orr.w r1, r1, r1, lsl #8
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8000206: ea41 4101 orr.w r1, r1, r1, lsl #16
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800020a: f022 0407 bic.w r4, r2, #7
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800020e: f07f 0700 mvns.w r7, #0
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8000212: 2300 movs r3, #0
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8000214: e8f0 5602 ldrd r5, r6, [r0], #8
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8000218: 3c08 subs r4, #8
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800021a: ea85 0501 eor.w r5, r5, r1
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800021e: ea86 0601 eor.w r6, r6, r1
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8000222: fa85 f547 uadd8 r5, r5, r7
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8000226: faa3 f587 sel r5, r3, r7
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800022a: fa86 f647 uadd8 r6, r6, r7
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800022e: faa5 f687 sel r6, r5, r7
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8000232: b98e cbnz r6, 8000258 <memchr+0x78>
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8000234: d1ee bne.n 8000214 <memchr+0x34>
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8000236: bcf0 pop {r4, r5, r6, r7}
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8000238: f001 01ff and.w r1, r1, #255 ; 0xff
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800023c: f002 0207 and.w r2, r2, #7
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8000240: b132 cbz r2, 8000250 <memchr+0x70>
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8000242: f810 3b01 ldrb.w r3, [r0], #1
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8000246: 3a01 subs r2, #1
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8000248: ea83 0301 eor.w r3, r3, r1
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800024c: b113 cbz r3, 8000254 <memchr+0x74>
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800024e: d1f8 bne.n 8000242 <memchr+0x62>
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8000250: 2000 movs r0, #0
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8000252: 4770 bx lr
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8000254: 3801 subs r0, #1
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8000256: 4770 bx lr
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8000258: 2d00 cmp r5, #0
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800025a: bf06 itte eq
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800025c: 4635 moveq r5, r6
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800025e: 3803 subeq r0, #3
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8000260: 3807 subne r0, #7
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8000262: f015 0f01 tst.w r5, #1
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8000266: d107 bne.n 8000278 <memchr+0x98>
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8000268: 3001 adds r0, #1
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800026a: f415 7f80 tst.w r5, #256 ; 0x100
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800026e: bf02 ittt eq
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8000270: 3001 addeq r0, #1
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8000272: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
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8000276: 3001 addeq r0, #1
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8000278: bcf0 pop {r4, r5, r6, r7}
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800027a: 3801 subs r0, #1
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800027c: 4770 bx lr
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800027e: bf00 nop
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08000280 <__aeabi_drsub>:
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8000280: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000
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8000284: e002 b.n 800028c <__adddf3>
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8000286: bf00 nop
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08000288 <__aeabi_dsub>:
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8000288: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000
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0800028c <__adddf3>:
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800028c: b530 push {r4, r5, lr}
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800028e: ea4f 0441 mov.w r4, r1, lsl #1
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8000292: ea4f 0543 mov.w r5, r3, lsl #1
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8000296: ea94 0f05 teq r4, r5
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800029a: bf08 it eq
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800029c: ea90 0f02 teqeq r0, r2
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80002a0: bf1f itttt ne
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80002a2: ea54 0c00 orrsne.w ip, r4, r0
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80002a6: ea55 0c02 orrsne.w ip, r5, r2
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80002aa: ea7f 5c64 mvnsne.w ip, r4, asr #21
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80002ae: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80002b2: f000 80e2 beq.w 800047a <__adddf3+0x1ee>
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80002b6: ea4f 5454 mov.w r4, r4, lsr #21
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80002ba: ebd4 5555 rsbs r5, r4, r5, lsr #21
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80002be: bfb8 it lt
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80002c0: 426d neglt r5, r5
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80002c2: dd0c ble.n 80002de <__adddf3+0x52>
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80002c4: 442c add r4, r5
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80002c6: ea80 0202 eor.w r2, r0, r2
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80002ca: ea81 0303 eor.w r3, r1, r3
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80002ce: ea82 0000 eor.w r0, r2, r0
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80002d2: ea83 0101 eor.w r1, r3, r1
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80002d6: ea80 0202 eor.w r2, r0, r2
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80002da: ea81 0303 eor.w r3, r1, r3
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80002de: 2d36 cmp r5, #54 ; 0x36
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80002e0: bf88 it hi
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80002e2: bd30 pophi {r4, r5, pc}
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80002e4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
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80002e8: ea4f 3101 mov.w r1, r1, lsl #12
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80002ec: f44f 1c80 mov.w ip, #1048576 ; 0x100000
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80002f0: ea4c 3111 orr.w r1, ip, r1, lsr #12
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80002f4: d002 beq.n 80002fc <__adddf3+0x70>
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80002f6: 4240 negs r0, r0
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80002f8: eb61 0141 sbc.w r1, r1, r1, lsl #1
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80002fc: f013 4f00 tst.w r3, #2147483648 ; 0x80000000
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8000300: ea4f 3303 mov.w r3, r3, lsl #12
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8000304: ea4c 3313 orr.w r3, ip, r3, lsr #12
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8000308: d002 beq.n 8000310 <__adddf3+0x84>
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800030a: 4252 negs r2, r2
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800030c: eb63 0343 sbc.w r3, r3, r3, lsl #1
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8000310: ea94 0f05 teq r4, r5
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8000314: f000 80a7 beq.w 8000466 <__adddf3+0x1da>
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8000318: f1a4 0401 sub.w r4, r4, #1
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800031c: f1d5 0e20 rsbs lr, r5, #32
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8000320: db0d blt.n 800033e <__adddf3+0xb2>
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8000322: fa02 fc0e lsl.w ip, r2, lr
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8000326: fa22 f205 lsr.w r2, r2, r5
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800032a: 1880 adds r0, r0, r2
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800032c: f141 0100 adc.w r1, r1, #0
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8000330: fa03 f20e lsl.w r2, r3, lr
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8000334: 1880 adds r0, r0, r2
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8000336: fa43 f305 asr.w r3, r3, r5
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800033a: 4159 adcs r1, r3
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800033c: e00e b.n 800035c <__adddf3+0xd0>
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800033e: f1a5 0520 sub.w r5, r5, #32
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8000342: f10e 0e20 add.w lr, lr, #32
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8000346: 2a01 cmp r2, #1
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8000348: fa03 fc0e lsl.w ip, r3, lr
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800034c: bf28 it cs
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800034e: f04c 0c02 orrcs.w ip, ip, #2
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8000352: fa43 f305 asr.w r3, r3, r5
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8000356: 18c0 adds r0, r0, r3
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8000358: eb51 71e3 adcs.w r1, r1, r3, asr #31
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800035c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
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8000360: d507 bpl.n 8000372 <__adddf3+0xe6>
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8000362: f04f 0e00 mov.w lr, #0
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8000366: f1dc 0c00 rsbs ip, ip, #0
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800036a: eb7e 0000 sbcs.w r0, lr, r0
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800036e: eb6e 0101 sbc.w r1, lr, r1
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8000372: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000
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8000376: d31b bcc.n 80003b0 <__adddf3+0x124>
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8000378: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000
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800037c: d30c bcc.n 8000398 <__adddf3+0x10c>
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800037e: 0849 lsrs r1, r1, #1
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8000380: ea5f 0030 movs.w r0, r0, rrx
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8000384: ea4f 0c3c mov.w ip, ip, rrx
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8000388: f104 0401 add.w r4, r4, #1
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800038c: ea4f 5244 mov.w r2, r4, lsl #21
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8000390: f512 0f80 cmn.w r2, #4194304 ; 0x400000
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8000394: f080 809a bcs.w 80004cc <__adddf3+0x240>
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8000398: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000
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800039c: bf08 it eq
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800039e: ea5f 0c50 movseq.w ip, r0, lsr #1
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80003a2: f150 0000 adcs.w r0, r0, #0
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80003a6: eb41 5104 adc.w r1, r1, r4, lsl #20
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80003aa: ea41 0105 orr.w r1, r1, r5
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80003ae: bd30 pop {r4, r5, pc}
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80003b0: ea5f 0c4c movs.w ip, ip, lsl #1
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80003b4: 4140 adcs r0, r0
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80003b6: eb41 0101 adc.w r1, r1, r1
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80003ba: 3c01 subs r4, #1
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80003bc: bf28 it cs
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80003be: f5b1 1f80 cmpcs.w r1, #1048576 ; 0x100000
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80003c2: d2e9 bcs.n 8000398 <__adddf3+0x10c>
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80003c4: f091 0f00 teq r1, #0
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80003c8: bf04 itt eq
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80003ca: 4601 moveq r1, r0
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80003cc: 2000 moveq r0, #0
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80003ce: fab1 f381 clz r3, r1
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80003d2: bf08 it eq
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80003d4: 3320 addeq r3, #32
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80003d6: f1a3 030b sub.w r3, r3, #11
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80003da: f1b3 0220 subs.w r2, r3, #32
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80003de: da0c bge.n 80003fa <__adddf3+0x16e>
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80003e0: 320c adds r2, #12
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80003e2: dd08 ble.n 80003f6 <__adddf3+0x16a>
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80003e4: f102 0c14 add.w ip, r2, #20
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80003e8: f1c2 020c rsb r2, r2, #12
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80003ec: fa01 f00c lsl.w r0, r1, ip
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80003f0: fa21 f102 lsr.w r1, r1, r2
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80003f4: e00c b.n 8000410 <__adddf3+0x184>
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80003f6: f102 0214 add.w r2, r2, #20
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80003fa: bfd8 it le
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80003fc: f1c2 0c20 rsble ip, r2, #32
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8000400: fa01 f102 lsl.w r1, r1, r2
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8000404: fa20 fc0c lsr.w ip, r0, ip
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8000408: bfdc itt le
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800040a: ea41 010c orrle.w r1, r1, ip
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800040e: 4090 lslle r0, r2
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8000410: 1ae4 subs r4, r4, r3
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8000412: bfa2 ittt ge
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8000414: eb01 5104 addge.w r1, r1, r4, lsl #20
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8000418: 4329 orrge r1, r5
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800041a: bd30 popge {r4, r5, pc}
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800041c: ea6f 0404 mvn.w r4, r4
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8000420: 3c1f subs r4, #31
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8000422: da1c bge.n 800045e <__adddf3+0x1d2>
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8000424: 340c adds r4, #12
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8000426: dc0e bgt.n 8000446 <__adddf3+0x1ba>
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8000428: f104 0414 add.w r4, r4, #20
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800042c: f1c4 0220 rsb r2, r4, #32
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8000430: fa20 f004 lsr.w r0, r0, r4
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8000434: fa01 f302 lsl.w r3, r1, r2
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8000438: ea40 0003 orr.w r0, r0, r3
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800043c: fa21 f304 lsr.w r3, r1, r4
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8000440: ea45 0103 orr.w r1, r5, r3
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8000444: bd30 pop {r4, r5, pc}
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8000446: f1c4 040c rsb r4, r4, #12
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800044a: f1c4 0220 rsb r2, r4, #32
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800044e: fa20 f002 lsr.w r0, r0, r2
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8000452: fa01 f304 lsl.w r3, r1, r4
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8000456: ea40 0003 orr.w r0, r0, r3
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800045a: 4629 mov r1, r5
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800045c: bd30 pop {r4, r5, pc}
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800045e: fa21 f004 lsr.w r0, r1, r4
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8000462: 4629 mov r1, r5
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8000464: bd30 pop {r4, r5, pc}
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8000466: f094 0f00 teq r4, #0
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800046a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000
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800046e: bf06 itte eq
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8000470: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000
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8000474: 3401 addeq r4, #1
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8000476: 3d01 subne r5, #1
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8000478: e74e b.n 8000318 <__adddf3+0x8c>
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800047a: ea7f 5c64 mvns.w ip, r4, asr #21
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800047e: bf18 it ne
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8000480: ea7f 5c65 mvnsne.w ip, r5, asr #21
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8000484: d029 beq.n 80004da <__adddf3+0x24e>
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8000486: ea94 0f05 teq r4, r5
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800048a: bf08 it eq
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800048c: ea90 0f02 teqeq r0, r2
|
|
8000490: d005 beq.n 800049e <__adddf3+0x212>
|
|
8000492: ea54 0c00 orrs.w ip, r4, r0
|
|
8000496: bf04 itt eq
|
|
8000498: 4619 moveq r1, r3
|
|
800049a: 4610 moveq r0, r2
|
|
800049c: bd30 pop {r4, r5, pc}
|
|
800049e: ea91 0f03 teq r1, r3
|
|
80004a2: bf1e ittt ne
|
|
80004a4: 2100 movne r1, #0
|
|
80004a6: 2000 movne r0, #0
|
|
80004a8: bd30 popne {r4, r5, pc}
|
|
80004aa: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
80004ae: d105 bne.n 80004bc <__adddf3+0x230>
|
|
80004b0: 0040 lsls r0, r0, #1
|
|
80004b2: 4149 adcs r1, r1
|
|
80004b4: bf28 it cs
|
|
80004b6: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000
|
|
80004ba: bd30 pop {r4, r5, pc}
|
|
80004bc: f514 0480 adds.w r4, r4, #4194304 ; 0x400000
|
|
80004c0: bf3c itt cc
|
|
80004c2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000
|
|
80004c6: bd30 popcc {r4, r5, pc}
|
|
80004c8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
|
|
80004cc: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000
|
|
80004d0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
|
|
80004d4: f04f 0000 mov.w r0, #0
|
|
80004d8: bd30 pop {r4, r5, pc}
|
|
80004da: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
80004de: bf1a itte ne
|
|
80004e0: 4619 movne r1, r3
|
|
80004e2: 4610 movne r0, r2
|
|
80004e4: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
80004e8: bf1c itt ne
|
|
80004ea: 460b movne r3, r1
|
|
80004ec: 4602 movne r2, r0
|
|
80004ee: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80004f2: bf06 itte eq
|
|
80004f4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
80004f8: ea91 0f03 teqeq r1, r3
|
|
80004fc: f441 2100 orrne.w r1, r1, #524288 ; 0x80000
|
|
8000500: bd30 pop {r4, r5, pc}
|
|
8000502: bf00 nop
|
|
|
|
08000504 <__aeabi_ui2d>:
|
|
8000504: f090 0f00 teq r0, #0
|
|
8000508: bf04 itt eq
|
|
800050a: 2100 moveq r1, #0
|
|
800050c: 4770 bxeq lr
|
|
800050e: b530 push {r4, r5, lr}
|
|
8000510: f44f 6480 mov.w r4, #1024 ; 0x400
|
|
8000514: f104 0432 add.w r4, r4, #50 ; 0x32
|
|
8000518: f04f 0500 mov.w r5, #0
|
|
800051c: f04f 0100 mov.w r1, #0
|
|
8000520: e750 b.n 80003c4 <__adddf3+0x138>
|
|
8000522: bf00 nop
|
|
|
|
08000524 <__aeabi_i2d>:
|
|
8000524: f090 0f00 teq r0, #0
|
|
8000528: bf04 itt eq
|
|
800052a: 2100 moveq r1, #0
|
|
800052c: 4770 bxeq lr
|
|
800052e: b530 push {r4, r5, lr}
|
|
8000530: f44f 6480 mov.w r4, #1024 ; 0x400
|
|
8000534: f104 0432 add.w r4, r4, #50 ; 0x32
|
|
8000538: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000
|
|
800053c: bf48 it mi
|
|
800053e: 4240 negmi r0, r0
|
|
8000540: f04f 0100 mov.w r1, #0
|
|
8000544: e73e b.n 80003c4 <__adddf3+0x138>
|
|
8000546: bf00 nop
|
|
|
|
08000548 <__aeabi_f2d>:
|
|
8000548: 0042 lsls r2, r0, #1
|
|
800054a: ea4f 01e2 mov.w r1, r2, asr #3
|
|
800054e: ea4f 0131 mov.w r1, r1, rrx
|
|
8000552: ea4f 7002 mov.w r0, r2, lsl #28
|
|
8000556: bf1f itttt ne
|
|
8000558: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000
|
|
800055c: f093 4f7f teqne r3, #4278190080 ; 0xff000000
|
|
8000560: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000
|
|
8000564: 4770 bxne lr
|
|
8000566: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000
|
|
800056a: bf08 it eq
|
|
800056c: 4770 bxeq lr
|
|
800056e: f093 4f7f teq r3, #4278190080 ; 0xff000000
|
|
8000572: bf04 itt eq
|
|
8000574: f441 2100 orreq.w r1, r1, #524288 ; 0x80000
|
|
8000578: 4770 bxeq lr
|
|
800057a: b530 push {r4, r5, lr}
|
|
800057c: f44f 7460 mov.w r4, #896 ; 0x380
|
|
8000580: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000
|
|
8000584: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
|
|
8000588: e71c b.n 80003c4 <__adddf3+0x138>
|
|
800058a: bf00 nop
|
|
|
|
0800058c <__aeabi_ul2d>:
|
|
800058c: ea50 0201 orrs.w r2, r0, r1
|
|
8000590: bf08 it eq
|
|
8000592: 4770 bxeq lr
|
|
8000594: b530 push {r4, r5, lr}
|
|
8000596: f04f 0500 mov.w r5, #0
|
|
800059a: e00a b.n 80005b2 <__aeabi_l2d+0x16>
|
|
|
|
0800059c <__aeabi_l2d>:
|
|
800059c: ea50 0201 orrs.w r2, r0, r1
|
|
80005a0: bf08 it eq
|
|
80005a2: 4770 bxeq lr
|
|
80005a4: b530 push {r4, r5, lr}
|
|
80005a6: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000
|
|
80005aa: d502 bpl.n 80005b2 <__aeabi_l2d+0x16>
|
|
80005ac: 4240 negs r0, r0
|
|
80005ae: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
80005b2: f44f 6480 mov.w r4, #1024 ; 0x400
|
|
80005b6: f104 0432 add.w r4, r4, #50 ; 0x32
|
|
80005ba: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
80005be: f43f aed8 beq.w 8000372 <__adddf3+0xe6>
|
|
80005c2: f04f 0203 mov.w r2, #3
|
|
80005c6: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005ca: bf18 it ne
|
|
80005cc: 3203 addne r2, #3
|
|
80005ce: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005d2: bf18 it ne
|
|
80005d4: 3203 addne r2, #3
|
|
80005d6: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
80005da: f1c2 0320 rsb r3, r2, #32
|
|
80005de: fa00 fc03 lsl.w ip, r0, r3
|
|
80005e2: fa20 f002 lsr.w r0, r0, r2
|
|
80005e6: fa01 fe03 lsl.w lr, r1, r3
|
|
80005ea: ea40 000e orr.w r0, r0, lr
|
|
80005ee: fa21 f102 lsr.w r1, r1, r2
|
|
80005f2: 4414 add r4, r2
|
|
80005f4: e6bd b.n 8000372 <__adddf3+0xe6>
|
|
80005f6: bf00 nop
|
|
|
|
080005f8 <__aeabi_dmul>:
|
|
80005f8: b570 push {r4, r5, r6, lr}
|
|
80005fa: f04f 0cff mov.w ip, #255 ; 0xff
|
|
80005fe: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
|
|
8000602: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
8000606: bf1d ittte ne
|
|
8000608: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
800060c: ea94 0f0c teqne r4, ip
|
|
8000610: ea95 0f0c teqne r5, ip
|
|
8000614: f000 f8de bleq 80007d4 <__aeabi_dmul+0x1dc>
|
|
8000618: 442c add r4, r5
|
|
800061a: ea81 0603 eor.w r6, r1, r3
|
|
800061e: ea21 514c bic.w r1, r1, ip, lsl #21
|
|
8000622: ea23 534c bic.w r3, r3, ip, lsl #21
|
|
8000626: ea50 3501 orrs.w r5, r0, r1, lsl #12
|
|
800062a: bf18 it ne
|
|
800062c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
|
|
8000630: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
|
|
8000634: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
|
8000638: d038 beq.n 80006ac <__aeabi_dmul+0xb4>
|
|
800063a: fba0 ce02 umull ip, lr, r0, r2
|
|
800063e: f04f 0500 mov.w r5, #0
|
|
8000642: fbe1 e502 umlal lr, r5, r1, r2
|
|
8000646: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000
|
|
800064a: fbe0 e503 umlal lr, r5, r0, r3
|
|
800064e: f04f 0600 mov.w r6, #0
|
|
8000652: fbe1 5603 umlal r5, r6, r1, r3
|
|
8000656: f09c 0f00 teq ip, #0
|
|
800065a: bf18 it ne
|
|
800065c: f04e 0e01 orrne.w lr, lr, #1
|
|
8000660: f1a4 04ff sub.w r4, r4, #255 ; 0xff
|
|
8000664: f5b6 7f00 cmp.w r6, #512 ; 0x200
|
|
8000668: f564 7440 sbc.w r4, r4, #768 ; 0x300
|
|
800066c: d204 bcs.n 8000678 <__aeabi_dmul+0x80>
|
|
800066e: ea5f 0e4e movs.w lr, lr, lsl #1
|
|
8000672: 416d adcs r5, r5
|
|
8000674: eb46 0606 adc.w r6, r6, r6
|
|
8000678: ea42 21c6 orr.w r1, r2, r6, lsl #11
|
|
800067c: ea41 5155 orr.w r1, r1, r5, lsr #21
|
|
8000680: ea4f 20c5 mov.w r0, r5, lsl #11
|
|
8000684: ea40 505e orr.w r0, r0, lr, lsr #21
|
|
8000688: ea4f 2ece mov.w lr, lr, lsl #11
|
|
800068c: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
|
|
8000690: bf88 it hi
|
|
8000692: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
|
|
8000696: d81e bhi.n 80006d6 <__aeabi_dmul+0xde>
|
|
8000698: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000
|
|
800069c: bf08 it eq
|
|
800069e: ea5f 0e50 movseq.w lr, r0, lsr #1
|
|
80006a2: f150 0000 adcs.w r0, r0, #0
|
|
80006a6: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
80006aa: bd70 pop {r4, r5, r6, pc}
|
|
80006ac: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000
|
|
80006b0: ea46 0101 orr.w r1, r6, r1
|
|
80006b4: ea40 0002 orr.w r0, r0, r2
|
|
80006b8: ea81 0103 eor.w r1, r1, r3
|
|
80006bc: ebb4 045c subs.w r4, r4, ip, lsr #1
|
|
80006c0: bfc2 ittt gt
|
|
80006c2: ebd4 050c rsbsgt r5, r4, ip
|
|
80006c6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80006ca: bd70 popgt {r4, r5, r6, pc}
|
|
80006cc: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
|
|
80006d0: f04f 0e00 mov.w lr, #0
|
|
80006d4: 3c01 subs r4, #1
|
|
80006d6: f300 80ab bgt.w 8000830 <__aeabi_dmul+0x238>
|
|
80006da: f114 0f36 cmn.w r4, #54 ; 0x36
|
|
80006de: bfde ittt le
|
|
80006e0: 2000 movle r0, #0
|
|
80006e2: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000
|
|
80006e6: bd70 pople {r4, r5, r6, pc}
|
|
80006e8: f1c4 0400 rsb r4, r4, #0
|
|
80006ec: 3c20 subs r4, #32
|
|
80006ee: da35 bge.n 800075c <__aeabi_dmul+0x164>
|
|
80006f0: 340c adds r4, #12
|
|
80006f2: dc1b bgt.n 800072c <__aeabi_dmul+0x134>
|
|
80006f4: f104 0414 add.w r4, r4, #20
|
|
80006f8: f1c4 0520 rsb r5, r4, #32
|
|
80006fc: fa00 f305 lsl.w r3, r0, r5
|
|
8000700: fa20 f004 lsr.w r0, r0, r4
|
|
8000704: fa01 f205 lsl.w r2, r1, r5
|
|
8000708: ea40 0002 orr.w r0, r0, r2
|
|
800070c: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000
|
|
8000710: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000
|
|
8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
8000718: fa21 f604 lsr.w r6, r1, r4
|
|
800071c: eb42 0106 adc.w r1, r2, r6
|
|
8000720: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000724: bf08 it eq
|
|
8000726: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800072a: bd70 pop {r4, r5, r6, pc}
|
|
800072c: f1c4 040c rsb r4, r4, #12
|
|
8000730: f1c4 0520 rsb r5, r4, #32
|
|
8000734: fa00 f304 lsl.w r3, r0, r4
|
|
8000738: fa20 f005 lsr.w r0, r0, r5
|
|
800073c: fa01 f204 lsl.w r2, r1, r4
|
|
8000740: ea40 0002 orr.w r0, r0, r2
|
|
8000744: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
|
|
8000748: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
800074c: f141 0100 adc.w r1, r1, #0
|
|
8000750: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000754: bf08 it eq
|
|
8000756: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800075a: bd70 pop {r4, r5, r6, pc}
|
|
800075c: f1c4 0520 rsb r5, r4, #32
|
|
8000760: fa00 f205 lsl.w r2, r0, r5
|
|
8000764: ea4e 0e02 orr.w lr, lr, r2
|
|
8000768: fa20 f304 lsr.w r3, r0, r4
|
|
800076c: fa01 f205 lsl.w r2, r1, r5
|
|
8000770: ea43 0302 orr.w r3, r3, r2
|
|
8000774: fa21 f004 lsr.w r0, r1, r4
|
|
8000778: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
|
|
800077c: fa21 f204 lsr.w r2, r1, r4
|
|
8000780: ea20 0002 bic.w r0, r0, r2
|
|
8000784: eb00 70d3 add.w r0, r0, r3, lsr #31
|
|
8000788: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
800078c: bf08 it eq
|
|
800078e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
8000792: bd70 pop {r4, r5, r6, pc}
|
|
8000794: f094 0f00 teq r4, #0
|
|
8000798: d10f bne.n 80007ba <__aeabi_dmul+0x1c2>
|
|
800079a: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000
|
|
800079e: 0040 lsls r0, r0, #1
|
|
80007a0: eb41 0101 adc.w r1, r1, r1
|
|
80007a4: f411 1f80 tst.w r1, #1048576 ; 0x100000
|
|
80007a8: bf08 it eq
|
|
80007aa: 3c01 subeq r4, #1
|
|
80007ac: d0f7 beq.n 800079e <__aeabi_dmul+0x1a6>
|
|
80007ae: ea41 0106 orr.w r1, r1, r6
|
|
80007b2: f095 0f00 teq r5, #0
|
|
80007b6: bf18 it ne
|
|
80007b8: 4770 bxne lr
|
|
80007ba: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000
|
|
80007be: 0052 lsls r2, r2, #1
|
|
80007c0: eb43 0303 adc.w r3, r3, r3
|
|
80007c4: f413 1f80 tst.w r3, #1048576 ; 0x100000
|
|
80007c8: bf08 it eq
|
|
80007ca: 3d01 subeq r5, #1
|
|
80007cc: d0f7 beq.n 80007be <__aeabi_dmul+0x1c6>
|
|
80007ce: ea43 0306 orr.w r3, r3, r6
|
|
80007d2: 4770 bx lr
|
|
80007d4: ea94 0f0c teq r4, ip
|
|
80007d8: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80007dc: bf18 it ne
|
|
80007de: ea95 0f0c teqne r5, ip
|
|
80007e2: d00c beq.n 80007fe <__aeabi_dmul+0x206>
|
|
80007e4: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
80007e8: bf18 it ne
|
|
80007ea: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
80007ee: d1d1 bne.n 8000794 <__aeabi_dmul+0x19c>
|
|
80007f0: ea81 0103 eor.w r1, r1, r3
|
|
80007f4: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
|
|
80007f8: f04f 0000 mov.w r0, #0
|
|
80007fc: bd70 pop {r4, r5, r6, pc}
|
|
80007fe: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000802: bf06 itte eq
|
|
8000804: 4610 moveq r0, r2
|
|
8000806: 4619 moveq r1, r3
|
|
8000808: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
800080c: d019 beq.n 8000842 <__aeabi_dmul+0x24a>
|
|
800080e: ea94 0f0c teq r4, ip
|
|
8000812: d102 bne.n 800081a <__aeabi_dmul+0x222>
|
|
8000814: ea50 3601 orrs.w r6, r0, r1, lsl #12
|
|
8000818: d113 bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800081a: ea95 0f0c teq r5, ip
|
|
800081e: d105 bne.n 800082c <__aeabi_dmul+0x234>
|
|
8000820: ea52 3603 orrs.w r6, r2, r3, lsl #12
|
|
8000824: bf1c itt ne
|
|
8000826: 4610 movne r0, r2
|
|
8000828: 4619 movne r1, r3
|
|
800082a: d10a bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800082c: ea81 0103 eor.w r1, r1, r3
|
|
8000830: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000
|
|
8000834: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
|
|
8000838: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
|
|
800083c: f04f 0000 mov.w r0, #0
|
|
8000840: bd70 pop {r4, r5, r6, pc}
|
|
8000842: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000
|
|
8000846: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000
|
|
800084a: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0800084c <__aeabi_ddiv>:
|
|
800084c: b570 push {r4, r5, r6, lr}
|
|
800084e: f04f 0cff mov.w ip, #255 ; 0xff
|
|
8000852: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700
|
|
8000856: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
800085a: bf1d ittte ne
|
|
800085c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
8000860: ea94 0f0c teqne r4, ip
|
|
8000864: ea95 0f0c teqne r5, ip
|
|
8000868: f000 f8a7 bleq 80009ba <__aeabi_ddiv+0x16e>
|
|
800086c: eba4 0405 sub.w r4, r4, r5
|
|
8000870: ea81 0e03 eor.w lr, r1, r3
|
|
8000874: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
8000878: ea4f 3101 mov.w r1, r1, lsl #12
|
|
800087c: f000 8088 beq.w 8000990 <__aeabi_ddiv+0x144>
|
|
8000880: ea4f 3303 mov.w r3, r3, lsl #12
|
|
8000884: f04f 5580 mov.w r5, #268435456 ; 0x10000000
|
|
8000888: ea45 1313 orr.w r3, r5, r3, lsr #4
|
|
800088c: ea43 6312 orr.w r3, r3, r2, lsr #24
|
|
8000890: ea4f 2202 mov.w r2, r2, lsl #8
|
|
8000894: ea45 1511 orr.w r5, r5, r1, lsr #4
|
|
8000898: ea45 6510 orr.w r5, r5, r0, lsr #24
|
|
800089c: ea4f 2600 mov.w r6, r0, lsl #8
|
|
80008a0: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000
|
|
80008a4: 429d cmp r5, r3
|
|
80008a6: bf08 it eq
|
|
80008a8: 4296 cmpeq r6, r2
|
|
80008aa: f144 04fd adc.w r4, r4, #253 ; 0xfd
|
|
80008ae: f504 7440 add.w r4, r4, #768 ; 0x300
|
|
80008b2: d202 bcs.n 80008ba <__aeabi_ddiv+0x6e>
|
|
80008b4: 085b lsrs r3, r3, #1
|
|
80008b6: ea4f 0232 mov.w r2, r2, rrx
|
|
80008ba: 1ab6 subs r6, r6, r2
|
|
80008bc: eb65 0503 sbc.w r5, r5, r3
|
|
80008c0: 085b lsrs r3, r3, #1
|
|
80008c2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008c6: f44f 1080 mov.w r0, #1048576 ; 0x100000
|
|
80008ca: f44f 2c00 mov.w ip, #524288 ; 0x80000
|
|
80008ce: ebb6 0e02 subs.w lr, r6, r2
|
|
80008d2: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008d6: bf22 ittt cs
|
|
80008d8: 1ab6 subcs r6, r6, r2
|
|
80008da: 4675 movcs r5, lr
|
|
80008dc: ea40 000c orrcs.w r0, r0, ip
|
|
80008e0: 085b lsrs r3, r3, #1
|
|
80008e2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008e6: ebb6 0e02 subs.w lr, r6, r2
|
|
80008ea: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008ee: bf22 ittt cs
|
|
80008f0: 1ab6 subcs r6, r6, r2
|
|
80008f2: 4675 movcs r5, lr
|
|
80008f4: ea40 005c orrcs.w r0, r0, ip, lsr #1
|
|
80008f8: 085b lsrs r3, r3, #1
|
|
80008fa: ea4f 0232 mov.w r2, r2, rrx
|
|
80008fe: ebb6 0e02 subs.w lr, r6, r2
|
|
8000902: eb75 0e03 sbcs.w lr, r5, r3
|
|
8000906: bf22 ittt cs
|
|
8000908: 1ab6 subcs r6, r6, r2
|
|
800090a: 4675 movcs r5, lr
|
|
800090c: ea40 009c orrcs.w r0, r0, ip, lsr #2
|
|
8000910: 085b lsrs r3, r3, #1
|
|
8000912: ea4f 0232 mov.w r2, r2, rrx
|
|
8000916: ebb6 0e02 subs.w lr, r6, r2
|
|
800091a: eb75 0e03 sbcs.w lr, r5, r3
|
|
800091e: bf22 ittt cs
|
|
8000920: 1ab6 subcs r6, r6, r2
|
|
8000922: 4675 movcs r5, lr
|
|
8000924: ea40 00dc orrcs.w r0, r0, ip, lsr #3
|
|
8000928: ea55 0e06 orrs.w lr, r5, r6
|
|
800092c: d018 beq.n 8000960 <__aeabi_ddiv+0x114>
|
|
800092e: ea4f 1505 mov.w r5, r5, lsl #4
|
|
8000932: ea45 7516 orr.w r5, r5, r6, lsr #28
|
|
8000936: ea4f 1606 mov.w r6, r6, lsl #4
|
|
800093a: ea4f 03c3 mov.w r3, r3, lsl #3
|
|
800093e: ea43 7352 orr.w r3, r3, r2, lsr #29
|
|
8000942: ea4f 02c2 mov.w r2, r2, lsl #3
|
|
8000946: ea5f 1c1c movs.w ip, ip, lsr #4
|
|
800094a: d1c0 bne.n 80008ce <__aeabi_ddiv+0x82>
|
|
800094c: f411 1f80 tst.w r1, #1048576 ; 0x100000
|
|
8000950: d10b bne.n 800096a <__aeabi_ddiv+0x11e>
|
|
8000952: ea41 0100 orr.w r1, r1, r0
|
|
8000956: f04f 0000 mov.w r0, #0
|
|
800095a: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000
|
|
800095e: e7b6 b.n 80008ce <__aeabi_ddiv+0x82>
|
|
8000960: f411 1f80 tst.w r1, #1048576 ; 0x100000
|
|
8000964: bf04 itt eq
|
|
8000966: 4301 orreq r1, r0
|
|
8000968: 2000 moveq r0, #0
|
|
800096a: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd
|
|
800096e: bf88 it hi
|
|
8000970: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700
|
|
8000974: f63f aeaf bhi.w 80006d6 <__aeabi_dmul+0xde>
|
|
8000978: ebb5 0c03 subs.w ip, r5, r3
|
|
800097c: bf04 itt eq
|
|
800097e: ebb6 0c02 subseq.w ip, r6, r2
|
|
8000982: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
8000986: f150 0000 adcs.w r0, r0, #0
|
|
800098a: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
800098e: bd70 pop {r4, r5, r6, pc}
|
|
8000990: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000
|
|
8000994: ea4e 3111 orr.w r1, lr, r1, lsr #12
|
|
8000998: eb14 045c adds.w r4, r4, ip, lsr #1
|
|
800099c: bfc2 ittt gt
|
|
800099e: ebd4 050c rsbsgt r5, r4, ip
|
|
80009a2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80009a6: bd70 popgt {r4, r5, r6, pc}
|
|
80009a8: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
|
|
80009ac: f04f 0e00 mov.w lr, #0
|
|
80009b0: 3c01 subs r4, #1
|
|
80009b2: e690 b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009b4: ea45 0e06 orr.w lr, r5, r6
|
|
80009b8: e68d b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009ba: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80009be: ea94 0f0c teq r4, ip
|
|
80009c2: bf08 it eq
|
|
80009c4: ea95 0f0c teqeq r5, ip
|
|
80009c8: f43f af3b beq.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009cc: ea94 0f0c teq r4, ip
|
|
80009d0: d10a bne.n 80009e8 <__aeabi_ddiv+0x19c>
|
|
80009d2: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80009d6: f47f af34 bne.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009da: ea95 0f0c teq r5, ip
|
|
80009de: f47f af25 bne.w 800082c <__aeabi_dmul+0x234>
|
|
80009e2: 4610 mov r0, r2
|
|
80009e4: 4619 mov r1, r3
|
|
80009e6: e72c b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009e8: ea95 0f0c teq r5, ip
|
|
80009ec: d106 bne.n 80009fc <__aeabi_ddiv+0x1b0>
|
|
80009ee: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
80009f2: f43f aefd beq.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
80009f6: 4610 mov r0, r2
|
|
80009f8: 4619 mov r1, r3
|
|
80009fa: e722 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009fc: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000a00: bf18 it ne
|
|
8000a02: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
8000a06: f47f aec5 bne.w 8000794 <__aeabi_dmul+0x19c>
|
|
8000a0a: ea50 0441 orrs.w r4, r0, r1, lsl #1
|
|
8000a0e: f47f af0d bne.w 800082c <__aeabi_dmul+0x234>
|
|
8000a12: ea52 0543 orrs.w r5, r2, r3, lsl #1
|
|
8000a16: f47f aeeb bne.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
8000a1a: e712 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
|
|
08000a1c <__gedf2>:
|
|
8000a1c: f04f 3cff mov.w ip, #4294967295 ; 0xffffffff
|
|
8000a20: e006 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a22: bf00 nop
|
|
|
|
08000a24 <__ledf2>:
|
|
8000a24: f04f 0c01 mov.w ip, #1
|
|
8000a28: e002 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a2a: bf00 nop
|
|
|
|
08000a2c <__cmpdf2>:
|
|
8000a2c: f04f 0c01 mov.w ip, #1
|
|
8000a30: f84d cd04 str.w ip, [sp, #-4]!
|
|
8000a34: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a38: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a40: bf18 it ne
|
|
8000a42: ea7f 5c6c mvnsne.w ip, ip, asr #21
|
|
8000a46: d01b beq.n 8000a80 <__cmpdf2+0x54>
|
|
8000a48: b001 add sp, #4
|
|
8000a4a: ea50 0c41 orrs.w ip, r0, r1, lsl #1
|
|
8000a4e: bf0c ite eq
|
|
8000a50: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
|
|
8000a54: ea91 0f03 teqne r1, r3
|
|
8000a58: bf02 ittt eq
|
|
8000a5a: ea90 0f02 teqeq r0, r2
|
|
8000a5e: 2000 moveq r0, #0
|
|
8000a60: 4770 bxeq lr
|
|
8000a62: f110 0f00 cmn.w r0, #0
|
|
8000a66: ea91 0f03 teq r1, r3
|
|
8000a6a: bf58 it pl
|
|
8000a6c: 4299 cmppl r1, r3
|
|
8000a6e: bf08 it eq
|
|
8000a70: 4290 cmpeq r0, r2
|
|
8000a72: bf2c ite cs
|
|
8000a74: 17d8 asrcs r0, r3, #31
|
|
8000a76: ea6f 70e3 mvncc.w r0, r3, asr #31
|
|
8000a7a: f040 0001 orr.w r0, r0, #1
|
|
8000a7e: 4770 bx lr
|
|
8000a80: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a84: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a88: d102 bne.n 8000a90 <__cmpdf2+0x64>
|
|
8000a8a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000a8e: d107 bne.n 8000aa0 <__cmpdf2+0x74>
|
|
8000a90: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a94: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a98: d1d6 bne.n 8000a48 <__cmpdf2+0x1c>
|
|
8000a9a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000a9e: d0d3 beq.n 8000a48 <__cmpdf2+0x1c>
|
|
8000aa0: f85d 0b04 ldr.w r0, [sp], #4
|
|
8000aa4: 4770 bx lr
|
|
8000aa6: bf00 nop
|
|
|
|
08000aa8 <__aeabi_cdrcmple>:
|
|
8000aa8: 4684 mov ip, r0
|
|
8000aaa: 4610 mov r0, r2
|
|
8000aac: 4662 mov r2, ip
|
|
8000aae: 468c mov ip, r1
|
|
8000ab0: 4619 mov r1, r3
|
|
8000ab2: 4663 mov r3, ip
|
|
8000ab4: e000 b.n 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ab6: bf00 nop
|
|
|
|
08000ab8 <__aeabi_cdcmpeq>:
|
|
8000ab8: b501 push {r0, lr}
|
|
8000aba: f7ff ffb7 bl 8000a2c <__cmpdf2>
|
|
8000abe: 2800 cmp r0, #0
|
|
8000ac0: bf48 it mi
|
|
8000ac2: f110 0f00 cmnmi.w r0, #0
|
|
8000ac6: bd01 pop {r0, pc}
|
|
|
|
08000ac8 <__aeabi_dcmpeq>:
|
|
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000acc: f7ff fff4 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ad0: bf0c ite eq
|
|
8000ad2: 2001 moveq r0, #1
|
|
8000ad4: 2000 movne r0, #0
|
|
8000ad6: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ada: bf00 nop
|
|
|
|
08000adc <__aeabi_dcmplt>:
|
|
8000adc: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000ae0: f7ff ffea bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ae4: bf34 ite cc
|
|
8000ae6: 2001 movcc r0, #1
|
|
8000ae8: 2000 movcs r0, #0
|
|
8000aea: f85d fb08 ldr.w pc, [sp], #8
|
|
8000aee: bf00 nop
|
|
|
|
08000af0 <__aeabi_dcmple>:
|
|
8000af0: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000af4: f7ff ffe0 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000af8: bf94 ite ls
|
|
8000afa: 2001 movls r0, #1
|
|
8000afc: 2000 movhi r0, #0
|
|
8000afe: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b02: bf00 nop
|
|
|
|
08000b04 <__aeabi_dcmpge>:
|
|
8000b04: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b08: f7ff ffce bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b0c: bf94 ite ls
|
|
8000b0e: 2001 movls r0, #1
|
|
8000b10: 2000 movhi r0, #0
|
|
8000b12: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b16: bf00 nop
|
|
|
|
08000b18 <__aeabi_dcmpgt>:
|
|
8000b18: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b1c: f7ff ffc4 bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b20: bf34 ite cc
|
|
8000b22: 2001 movcc r0, #1
|
|
8000b24: 2000 movcs r0, #0
|
|
8000b26: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b2a: bf00 nop
|
|
|
|
08000b2c <__aeabi_dcmpun>:
|
|
8000b2c: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000b30: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b34: d102 bne.n 8000b3c <__aeabi_dcmpun+0x10>
|
|
8000b36: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000b3a: d10a bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000b40: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x20>
|
|
8000b46: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000b4a: d102 bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b4c: f04f 0000 mov.w r0, #0
|
|
8000b50: 4770 bx lr
|
|
8000b52: f04f 0001 mov.w r0, #1
|
|
8000b56: 4770 bx lr
|
|
|
|
08000b58 <__aeabi_d2iz>:
|
|
8000b58: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000b5c: f512 1200 adds.w r2, r2, #2097152 ; 0x200000
|
|
8000b60: d215 bcs.n 8000b8e <__aeabi_d2iz+0x36>
|
|
8000b62: d511 bpl.n 8000b88 <__aeabi_d2iz+0x30>
|
|
8000b64: f46f 7378 mvn.w r3, #992 ; 0x3e0
|
|
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000b6c: d912 bls.n 8000b94 <__aeabi_d2iz+0x3c>
|
|
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000b72: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
|
|
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000b7a: f011 4f00 tst.w r1, #2147483648 ; 0x80000000
|
|
8000b7e: fa23 f002 lsr.w r0, r3, r2
|
|
8000b82: bf18 it ne
|
|
8000b84: 4240 negne r0, r0
|
|
8000b86: 4770 bx lr
|
|
8000b88: f04f 0000 mov.w r0, #0
|
|
8000b8c: 4770 bx lr
|
|
8000b8e: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000b92: d105 bne.n 8000ba0 <__aeabi_d2iz+0x48>
|
|
8000b94: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000
|
|
8000b98: bf08 it eq
|
|
8000b9a: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000
|
|
8000b9e: 4770 bx lr
|
|
8000ba0: f04f 0000 mov.w r0, #0
|
|
8000ba4: 4770 bx lr
|
|
8000ba6: bf00 nop
|
|
|
|
08000ba8 <__aeabi_d2f>:
|
|
8000ba8: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000bac: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000
|
|
8000bb0: bf24 itt cs
|
|
8000bb2: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000
|
|
8000bb6: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000
|
|
8000bba: d90d bls.n 8000bd8 <__aeabi_d2f+0x30>
|
|
8000bbc: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000
|
|
8000bc0: ea4f 02c0 mov.w r2, r0, lsl #3
|
|
8000bc4: ea4c 7050 orr.w r0, ip, r0, lsr #29
|
|
8000bc8: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000
|
|
8000bcc: eb40 0083 adc.w r0, r0, r3, lsl #2
|
|
8000bd0: bf08 it eq
|
|
8000bd2: f020 0001 biceq.w r0, r0, #1
|
|
8000bd6: 4770 bx lr
|
|
8000bd8: f011 4f80 tst.w r1, #1073741824 ; 0x40000000
|
|
8000bdc: d121 bne.n 8000c22 <__aeabi_d2f+0x7a>
|
|
8000bde: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000
|
|
8000be2: bfbc itt lt
|
|
8000be4: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000
|
|
8000be8: 4770 bxlt lr
|
|
8000bea: f441 1180 orr.w r1, r1, #1048576 ; 0x100000
|
|
8000bee: ea4f 5252 mov.w r2, r2, lsr #21
|
|
8000bf2: f1c2 0218 rsb r2, r2, #24
|
|
8000bf6: f1c2 0c20 rsb ip, r2, #32
|
|
8000bfa: fa10 f30c lsls.w r3, r0, ip
|
|
8000bfe: fa20 f002 lsr.w r0, r0, r2
|
|
8000c02: bf18 it ne
|
|
8000c04: f040 0001 orrne.w r0, r0, #1
|
|
8000c08: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000c0c: ea4f 23d3 mov.w r3, r3, lsr #11
|
|
8000c10: fa03 fc0c lsl.w ip, r3, ip
|
|
8000c14: ea40 000c orr.w r0, r0, ip
|
|
8000c18: fa23 f302 lsr.w r3, r3, r2
|
|
8000c1c: ea4f 0343 mov.w r3, r3, lsl #1
|
|
8000c20: e7cc b.n 8000bbc <__aeabi_d2f+0x14>
|
|
8000c22: ea7f 5362 mvns.w r3, r2, asr #21
|
|
8000c26: d107 bne.n 8000c38 <__aeabi_d2f+0x90>
|
|
8000c28: ea50 3301 orrs.w r3, r0, r1, lsl #12
|
|
8000c2c: bf1e ittt ne
|
|
8000c2e: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000
|
|
8000c32: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000
|
|
8000c36: 4770 bxne lr
|
|
8000c38: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000
|
|
8000c3c: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000
|
|
8000c40: f440 0000 orr.w r0, r0, #8388608 ; 0x800000
|
|
8000c44: 4770 bx lr
|
|
8000c46: bf00 nop
|
|
|
|
08000c48 <__aeabi_ldivmod>:
|
|
8000c48: b97b cbnz r3, 8000c6a <__aeabi_ldivmod+0x22>
|
|
8000c4a: b972 cbnz r2, 8000c6a <__aeabi_ldivmod+0x22>
|
|
8000c4c: 2900 cmp r1, #0
|
|
8000c4e: bfbe ittt lt
|
|
8000c50: 2000 movlt r0, #0
|
|
8000c52: f04f 4100 movlt.w r1, #2147483648 ; 0x80000000
|
|
8000c56: e006 blt.n 8000c66 <__aeabi_ldivmod+0x1e>
|
|
8000c58: bf08 it eq
|
|
8000c5a: 2800 cmpeq r0, #0
|
|
8000c5c: bf1c itt ne
|
|
8000c5e: f06f 4100 mvnne.w r1, #2147483648 ; 0x80000000
|
|
8000c62: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
|
|
8000c66: f000 b9b9 b.w 8000fdc <__aeabi_idiv0>
|
|
8000c6a: f1ad 0c08 sub.w ip, sp, #8
|
|
8000c6e: e96d ce04 strd ip, lr, [sp, #-16]!
|
|
8000c72: 2900 cmp r1, #0
|
|
8000c74: db09 blt.n 8000c8a <__aeabi_ldivmod+0x42>
|
|
8000c76: 2b00 cmp r3, #0
|
|
8000c78: db1a blt.n 8000cb0 <__aeabi_ldivmod+0x68>
|
|
8000c7a: f000 f84d bl 8000d18 <__udivmoddi4>
|
|
8000c7e: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000c82: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000c86: b004 add sp, #16
|
|
8000c88: 4770 bx lr
|
|
8000c8a: 4240 negs r0, r0
|
|
8000c8c: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000c90: 2b00 cmp r3, #0
|
|
8000c92: db1b blt.n 8000ccc <__aeabi_ldivmod+0x84>
|
|
8000c94: f000 f840 bl 8000d18 <__udivmoddi4>
|
|
8000c98: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000c9c: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000ca0: b004 add sp, #16
|
|
8000ca2: 4240 negs r0, r0
|
|
8000ca4: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000ca8: 4252 negs r2, r2
|
|
8000caa: eb63 0343 sbc.w r3, r3, r3, lsl #1
|
|
8000cae: 4770 bx lr
|
|
8000cb0: 4252 negs r2, r2
|
|
8000cb2: eb63 0343 sbc.w r3, r3, r3, lsl #1
|
|
8000cb6: f000 f82f bl 8000d18 <__udivmoddi4>
|
|
8000cba: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000cbe: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000cc2: b004 add sp, #16
|
|
8000cc4: 4240 negs r0, r0
|
|
8000cc6: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
8000cca: 4770 bx lr
|
|
8000ccc: 4252 negs r2, r2
|
|
8000cce: eb63 0343 sbc.w r3, r3, r3, lsl #1
|
|
8000cd2: f000 f821 bl 8000d18 <__udivmoddi4>
|
|
8000cd6: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000cda: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000cde: b004 add sp, #16
|
|
8000ce0: 4252 negs r2, r2
|
|
8000ce2: eb63 0343 sbc.w r3, r3, r3, lsl #1
|
|
8000ce6: 4770 bx lr
|
|
|
|
08000ce8 <__aeabi_uldivmod>:
|
|
8000ce8: b953 cbnz r3, 8000d00 <__aeabi_uldivmod+0x18>
|
|
8000cea: b94a cbnz r2, 8000d00 <__aeabi_uldivmod+0x18>
|
|
8000cec: 2900 cmp r1, #0
|
|
8000cee: bf08 it eq
|
|
8000cf0: 2800 cmpeq r0, #0
|
|
8000cf2: bf1c itt ne
|
|
8000cf4: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
|
|
8000cf8: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
|
|
8000cfc: f000 b96e b.w 8000fdc <__aeabi_idiv0>
|
|
8000d00: f1ad 0c08 sub.w ip, sp, #8
|
|
8000d04: e96d ce04 strd ip, lr, [sp, #-16]!
|
|
8000d08: f000 f806 bl 8000d18 <__udivmoddi4>
|
|
8000d0c: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000d10: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000d14: b004 add sp, #16
|
|
8000d16: 4770 bx lr
|
|
|
|
08000d18 <__udivmoddi4>:
|
|
8000d18: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8000d1c: 9d08 ldr r5, [sp, #32]
|
|
8000d1e: 4604 mov r4, r0
|
|
8000d20: 468c mov ip, r1
|
|
8000d22: 2b00 cmp r3, #0
|
|
8000d24: f040 8083 bne.w 8000e2e <__udivmoddi4+0x116>
|
|
8000d28: 428a cmp r2, r1
|
|
8000d2a: 4617 mov r7, r2
|
|
8000d2c: d947 bls.n 8000dbe <__udivmoddi4+0xa6>
|
|
8000d2e: fab2 f282 clz r2, r2
|
|
8000d32: b142 cbz r2, 8000d46 <__udivmoddi4+0x2e>
|
|
8000d34: f1c2 0020 rsb r0, r2, #32
|
|
8000d38: fa24 f000 lsr.w r0, r4, r0
|
|
8000d3c: 4091 lsls r1, r2
|
|
8000d3e: 4097 lsls r7, r2
|
|
8000d40: ea40 0c01 orr.w ip, r0, r1
|
|
8000d44: 4094 lsls r4, r2
|
|
8000d46: ea4f 4817 mov.w r8, r7, lsr #16
|
|
8000d4a: 0c23 lsrs r3, r4, #16
|
|
8000d4c: fbbc f6f8 udiv r6, ip, r8
|
|
8000d50: fa1f fe87 uxth.w lr, r7
|
|
8000d54: fb08 c116 mls r1, r8, r6, ip
|
|
8000d58: ea43 4301 orr.w r3, r3, r1, lsl #16
|
|
8000d5c: fb06 f10e mul.w r1, r6, lr
|
|
8000d60: 4299 cmp r1, r3
|
|
8000d62: d909 bls.n 8000d78 <__udivmoddi4+0x60>
|
|
8000d64: 18fb adds r3, r7, r3
|
|
8000d66: f106 30ff add.w r0, r6, #4294967295 ; 0xffffffff
|
|
8000d6a: f080 8119 bcs.w 8000fa0 <__udivmoddi4+0x288>
|
|
8000d6e: 4299 cmp r1, r3
|
|
8000d70: f240 8116 bls.w 8000fa0 <__udivmoddi4+0x288>
|
|
8000d74: 3e02 subs r6, #2
|
|
8000d76: 443b add r3, r7
|
|
8000d78: 1a5b subs r3, r3, r1
|
|
8000d7a: b2a4 uxth r4, r4
|
|
8000d7c: fbb3 f0f8 udiv r0, r3, r8
|
|
8000d80: fb08 3310 mls r3, r8, r0, r3
|
|
8000d84: ea44 4403 orr.w r4, r4, r3, lsl #16
|
|
8000d88: fb00 fe0e mul.w lr, r0, lr
|
|
8000d8c: 45a6 cmp lr, r4
|
|
8000d8e: d909 bls.n 8000da4 <__udivmoddi4+0x8c>
|
|
8000d90: 193c adds r4, r7, r4
|
|
8000d92: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
|
|
8000d96: f080 8105 bcs.w 8000fa4 <__udivmoddi4+0x28c>
|
|
8000d9a: 45a6 cmp lr, r4
|
|
8000d9c: f240 8102 bls.w 8000fa4 <__udivmoddi4+0x28c>
|
|
8000da0: 3802 subs r0, #2
|
|
8000da2: 443c add r4, r7
|
|
8000da4: ea40 4006 orr.w r0, r0, r6, lsl #16
|
|
8000da8: eba4 040e sub.w r4, r4, lr
|
|
8000dac: 2600 movs r6, #0
|
|
8000dae: b11d cbz r5, 8000db8 <__udivmoddi4+0xa0>
|
|
8000db0: 40d4 lsrs r4, r2
|
|
8000db2: 2300 movs r3, #0
|
|
8000db4: e9c5 4300 strd r4, r3, [r5]
|
|
8000db8: 4631 mov r1, r6
|
|
8000dba: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8000dbe: b902 cbnz r2, 8000dc2 <__udivmoddi4+0xaa>
|
|
8000dc0: deff udf #255 ; 0xff
|
|
8000dc2: fab2 f282 clz r2, r2
|
|
8000dc6: 2a00 cmp r2, #0
|
|
8000dc8: d150 bne.n 8000e6c <__udivmoddi4+0x154>
|
|
8000dca: 1bcb subs r3, r1, r7
|
|
8000dcc: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000dd0: fa1f f887 uxth.w r8, r7
|
|
8000dd4: 2601 movs r6, #1
|
|
8000dd6: fbb3 fcfe udiv ip, r3, lr
|
|
8000dda: 0c21 lsrs r1, r4, #16
|
|
8000ddc: fb0e 331c mls r3, lr, ip, r3
|
|
8000de0: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000de4: fb08 f30c mul.w r3, r8, ip
|
|
8000de8: 428b cmp r3, r1
|
|
8000dea: d907 bls.n 8000dfc <__udivmoddi4+0xe4>
|
|
8000dec: 1879 adds r1, r7, r1
|
|
8000dee: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
|
|
8000df2: d202 bcs.n 8000dfa <__udivmoddi4+0xe2>
|
|
8000df4: 428b cmp r3, r1
|
|
8000df6: f200 80e9 bhi.w 8000fcc <__udivmoddi4+0x2b4>
|
|
8000dfa: 4684 mov ip, r0
|
|
8000dfc: 1ac9 subs r1, r1, r3
|
|
8000dfe: b2a3 uxth r3, r4
|
|
8000e00: fbb1 f0fe udiv r0, r1, lr
|
|
8000e04: fb0e 1110 mls r1, lr, r0, r1
|
|
8000e08: ea43 4401 orr.w r4, r3, r1, lsl #16
|
|
8000e0c: fb08 f800 mul.w r8, r8, r0
|
|
8000e10: 45a0 cmp r8, r4
|
|
8000e12: d907 bls.n 8000e24 <__udivmoddi4+0x10c>
|
|
8000e14: 193c adds r4, r7, r4
|
|
8000e16: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
|
|
8000e1a: d202 bcs.n 8000e22 <__udivmoddi4+0x10a>
|
|
8000e1c: 45a0 cmp r8, r4
|
|
8000e1e: f200 80d9 bhi.w 8000fd4 <__udivmoddi4+0x2bc>
|
|
8000e22: 4618 mov r0, r3
|
|
8000e24: eba4 0408 sub.w r4, r4, r8
|
|
8000e28: ea40 400c orr.w r0, r0, ip, lsl #16
|
|
8000e2c: e7bf b.n 8000dae <__udivmoddi4+0x96>
|
|
8000e2e: 428b cmp r3, r1
|
|
8000e30: d909 bls.n 8000e46 <__udivmoddi4+0x12e>
|
|
8000e32: 2d00 cmp r5, #0
|
|
8000e34: f000 80b1 beq.w 8000f9a <__udivmoddi4+0x282>
|
|
8000e38: 2600 movs r6, #0
|
|
8000e3a: e9c5 0100 strd r0, r1, [r5]
|
|
8000e3e: 4630 mov r0, r6
|
|
8000e40: 4631 mov r1, r6
|
|
8000e42: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8000e46: fab3 f683 clz r6, r3
|
|
8000e4a: 2e00 cmp r6, #0
|
|
8000e4c: d14a bne.n 8000ee4 <__udivmoddi4+0x1cc>
|
|
8000e4e: 428b cmp r3, r1
|
|
8000e50: d302 bcc.n 8000e58 <__udivmoddi4+0x140>
|
|
8000e52: 4282 cmp r2, r0
|
|
8000e54: f200 80b8 bhi.w 8000fc8 <__udivmoddi4+0x2b0>
|
|
8000e58: 1a84 subs r4, r0, r2
|
|
8000e5a: eb61 0103 sbc.w r1, r1, r3
|
|
8000e5e: 2001 movs r0, #1
|
|
8000e60: 468c mov ip, r1
|
|
8000e62: 2d00 cmp r5, #0
|
|
8000e64: d0a8 beq.n 8000db8 <__udivmoddi4+0xa0>
|
|
8000e66: e9c5 4c00 strd r4, ip, [r5]
|
|
8000e6a: e7a5 b.n 8000db8 <__udivmoddi4+0xa0>
|
|
8000e6c: f1c2 0320 rsb r3, r2, #32
|
|
8000e70: fa20 f603 lsr.w r6, r0, r3
|
|
8000e74: 4097 lsls r7, r2
|
|
8000e76: fa01 f002 lsl.w r0, r1, r2
|
|
8000e7a: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000e7e: 40d9 lsrs r1, r3
|
|
8000e80: 4330 orrs r0, r6
|
|
8000e82: 0c03 lsrs r3, r0, #16
|
|
8000e84: fbb1 f6fe udiv r6, r1, lr
|
|
8000e88: fa1f f887 uxth.w r8, r7
|
|
8000e8c: fb0e 1116 mls r1, lr, r6, r1
|
|
8000e90: ea43 4301 orr.w r3, r3, r1, lsl #16
|
|
8000e94: fb06 f108 mul.w r1, r6, r8
|
|
8000e98: 4299 cmp r1, r3
|
|
8000e9a: fa04 f402 lsl.w r4, r4, r2
|
|
8000e9e: d909 bls.n 8000eb4 <__udivmoddi4+0x19c>
|
|
8000ea0: 18fb adds r3, r7, r3
|
|
8000ea2: f106 3cff add.w ip, r6, #4294967295 ; 0xffffffff
|
|
8000ea6: f080 808d bcs.w 8000fc4 <__udivmoddi4+0x2ac>
|
|
8000eaa: 4299 cmp r1, r3
|
|
8000eac: f240 808a bls.w 8000fc4 <__udivmoddi4+0x2ac>
|
|
8000eb0: 3e02 subs r6, #2
|
|
8000eb2: 443b add r3, r7
|
|
8000eb4: 1a5b subs r3, r3, r1
|
|
8000eb6: b281 uxth r1, r0
|
|
8000eb8: fbb3 f0fe udiv r0, r3, lr
|
|
8000ebc: fb0e 3310 mls r3, lr, r0, r3
|
|
8000ec0: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000ec4: fb00 f308 mul.w r3, r0, r8
|
|
8000ec8: 428b cmp r3, r1
|
|
8000eca: d907 bls.n 8000edc <__udivmoddi4+0x1c4>
|
|
8000ecc: 1879 adds r1, r7, r1
|
|
8000ece: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
|
|
8000ed2: d273 bcs.n 8000fbc <__udivmoddi4+0x2a4>
|
|
8000ed4: 428b cmp r3, r1
|
|
8000ed6: d971 bls.n 8000fbc <__udivmoddi4+0x2a4>
|
|
8000ed8: 3802 subs r0, #2
|
|
8000eda: 4439 add r1, r7
|
|
8000edc: 1acb subs r3, r1, r3
|
|
8000ede: ea40 4606 orr.w r6, r0, r6, lsl #16
|
|
8000ee2: e778 b.n 8000dd6 <__udivmoddi4+0xbe>
|
|
8000ee4: f1c6 0c20 rsb ip, r6, #32
|
|
8000ee8: fa03 f406 lsl.w r4, r3, r6
|
|
8000eec: fa22 f30c lsr.w r3, r2, ip
|
|
8000ef0: 431c orrs r4, r3
|
|
8000ef2: fa20 f70c lsr.w r7, r0, ip
|
|
8000ef6: fa01 f306 lsl.w r3, r1, r6
|
|
8000efa: ea4f 4e14 mov.w lr, r4, lsr #16
|
|
8000efe: fa21 f10c lsr.w r1, r1, ip
|
|
8000f02: 431f orrs r7, r3
|
|
8000f04: 0c3b lsrs r3, r7, #16
|
|
8000f06: fbb1 f9fe udiv r9, r1, lr
|
|
8000f0a: fa1f f884 uxth.w r8, r4
|
|
8000f0e: fb0e 1119 mls r1, lr, r9, r1
|
|
8000f12: ea43 4101 orr.w r1, r3, r1, lsl #16
|
|
8000f16: fb09 fa08 mul.w sl, r9, r8
|
|
8000f1a: 458a cmp sl, r1
|
|
8000f1c: fa02 f206 lsl.w r2, r2, r6
|
|
8000f20: fa00 f306 lsl.w r3, r0, r6
|
|
8000f24: d908 bls.n 8000f38 <__udivmoddi4+0x220>
|
|
8000f26: 1861 adds r1, r4, r1
|
|
8000f28: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
|
|
8000f2c: d248 bcs.n 8000fc0 <__udivmoddi4+0x2a8>
|
|
8000f2e: 458a cmp sl, r1
|
|
8000f30: d946 bls.n 8000fc0 <__udivmoddi4+0x2a8>
|
|
8000f32: f1a9 0902 sub.w r9, r9, #2
|
|
8000f36: 4421 add r1, r4
|
|
8000f38: eba1 010a sub.w r1, r1, sl
|
|
8000f3c: b2bf uxth r7, r7
|
|
8000f3e: fbb1 f0fe udiv r0, r1, lr
|
|
8000f42: fb0e 1110 mls r1, lr, r0, r1
|
|
8000f46: ea47 4701 orr.w r7, r7, r1, lsl #16
|
|
8000f4a: fb00 f808 mul.w r8, r0, r8
|
|
8000f4e: 45b8 cmp r8, r7
|
|
8000f50: d907 bls.n 8000f62 <__udivmoddi4+0x24a>
|
|
8000f52: 19e7 adds r7, r4, r7
|
|
8000f54: f100 31ff add.w r1, r0, #4294967295 ; 0xffffffff
|
|
8000f58: d22e bcs.n 8000fb8 <__udivmoddi4+0x2a0>
|
|
8000f5a: 45b8 cmp r8, r7
|
|
8000f5c: d92c bls.n 8000fb8 <__udivmoddi4+0x2a0>
|
|
8000f5e: 3802 subs r0, #2
|
|
8000f60: 4427 add r7, r4
|
|
8000f62: ea40 4009 orr.w r0, r0, r9, lsl #16
|
|
8000f66: eba7 0708 sub.w r7, r7, r8
|
|
8000f6a: fba0 8902 umull r8, r9, r0, r2
|
|
8000f6e: 454f cmp r7, r9
|
|
8000f70: 46c6 mov lr, r8
|
|
8000f72: 4649 mov r1, r9
|
|
8000f74: d31a bcc.n 8000fac <__udivmoddi4+0x294>
|
|
8000f76: d017 beq.n 8000fa8 <__udivmoddi4+0x290>
|
|
8000f78: b15d cbz r5, 8000f92 <__udivmoddi4+0x27a>
|
|
8000f7a: ebb3 020e subs.w r2, r3, lr
|
|
8000f7e: eb67 0701 sbc.w r7, r7, r1
|
|
8000f82: fa07 fc0c lsl.w ip, r7, ip
|
|
8000f86: 40f2 lsrs r2, r6
|
|
8000f88: ea4c 0202 orr.w r2, ip, r2
|
|
8000f8c: 40f7 lsrs r7, r6
|
|
8000f8e: e9c5 2700 strd r2, r7, [r5]
|
|
8000f92: 2600 movs r6, #0
|
|
8000f94: 4631 mov r1, r6
|
|
8000f96: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8000f9a: 462e mov r6, r5
|
|
8000f9c: 4628 mov r0, r5
|
|
8000f9e: e70b b.n 8000db8 <__udivmoddi4+0xa0>
|
|
8000fa0: 4606 mov r6, r0
|
|
8000fa2: e6e9 b.n 8000d78 <__udivmoddi4+0x60>
|
|
8000fa4: 4618 mov r0, r3
|
|
8000fa6: e6fd b.n 8000da4 <__udivmoddi4+0x8c>
|
|
8000fa8: 4543 cmp r3, r8
|
|
8000faa: d2e5 bcs.n 8000f78 <__udivmoddi4+0x260>
|
|
8000fac: ebb8 0e02 subs.w lr, r8, r2
|
|
8000fb0: eb69 0104 sbc.w r1, r9, r4
|
|
8000fb4: 3801 subs r0, #1
|
|
8000fb6: e7df b.n 8000f78 <__udivmoddi4+0x260>
|
|
8000fb8: 4608 mov r0, r1
|
|
8000fba: e7d2 b.n 8000f62 <__udivmoddi4+0x24a>
|
|
8000fbc: 4660 mov r0, ip
|
|
8000fbe: e78d b.n 8000edc <__udivmoddi4+0x1c4>
|
|
8000fc0: 4681 mov r9, r0
|
|
8000fc2: e7b9 b.n 8000f38 <__udivmoddi4+0x220>
|
|
8000fc4: 4666 mov r6, ip
|
|
8000fc6: e775 b.n 8000eb4 <__udivmoddi4+0x19c>
|
|
8000fc8: 4630 mov r0, r6
|
|
8000fca: e74a b.n 8000e62 <__udivmoddi4+0x14a>
|
|
8000fcc: f1ac 0c02 sub.w ip, ip, #2
|
|
8000fd0: 4439 add r1, r7
|
|
8000fd2: e713 b.n 8000dfc <__udivmoddi4+0xe4>
|
|
8000fd4: 3802 subs r0, #2
|
|
8000fd6: 443c add r4, r7
|
|
8000fd8: e724 b.n 8000e24 <__udivmoddi4+0x10c>
|
|
8000fda: bf00 nop
|
|
|
|
08000fdc <__aeabi_idiv0>:
|
|
8000fdc: 4770 bx lr
|
|
8000fde: bf00 nop
|
|
|
|
08000fe0 <CayenneLppReset>:
|
|
|
|
/* USER CODE END CayenneLppCursor */
|
|
}
|
|
|
|
void CayenneLppReset(void)
|
|
{
|
|
8000fe0: b480 push {r7}
|
|
8000fe2: af00 add r7, sp, #0
|
|
CayenneLppCursor = 0;
|
|
8000fe4: f240 4368 movw r3, #1128 ; 0x468
|
|
8000fe8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8000fec: 2200 movs r2, #0
|
|
8000fee: 701a strb r2, [r3, #0]
|
|
/* USER CODE BEGIN CayenneLppReset */
|
|
|
|
/* USER CODE END CayenneLppReset */
|
|
}
|
|
8000ff0: bf00 nop
|
|
8000ff2: 46bd mov sp, r7
|
|
8000ff4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000ff8: 4770 bx lr
|
|
|
|
08000ffa <CayenneLppGetSize>:
|
|
|
|
uint8_t CayenneLppGetSize(void)
|
|
{
|
|
8000ffa: b480 push {r7}
|
|
8000ffc: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN CayenneLppGetSize */
|
|
|
|
/* USER CODE END CayenneLppGetSize */
|
|
return CayenneLppCursor;
|
|
8000ffe: f240 4368 movw r3, #1128 ; 0x468
|
|
8001002: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001006: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8001008: 4618 mov r0, r3
|
|
800100a: 46bd mov sp, r7
|
|
800100c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001010: 4770 bx lr
|
|
|
|
08001012 <CayenneLppCopy>:
|
|
/* USER CODE END CayenneLppGetBuffer */
|
|
return CayenneLppBuffer;
|
|
}
|
|
|
|
uint8_t CayenneLppCopy(uint8_t *dst)
|
|
{
|
|
8001012: b580 push {r7, lr}
|
|
8001014: b082 sub sp, #8
|
|
8001016: af00 add r7, sp, #0
|
|
8001018: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN CayenneLppCopy_1 */
|
|
|
|
/* USER CODE END CayenneLppCopy_1 */
|
|
UTIL_MEM_cpy_8(dst, CayenneLppBuffer, CayenneLppCursor);
|
|
800101a: f240 4368 movw r3, #1128 ; 0x468
|
|
800101e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001022: 781b ldrb r3, [r3, #0]
|
|
8001024: b29b uxth r3, r3
|
|
8001026: 461a mov r2, r3
|
|
8001028: f240 5178 movw r1, #1400 ; 0x578
|
|
800102c: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001030: 6878 ldr r0, [r7, #4]
|
|
8001032: f003 fc59 bl 80048e8 <UTIL_MEM_cpy_8>
|
|
/* USER CODE BEGIN CayenneLppCopy_2 */
|
|
|
|
/* USER CODE END CayenneLppCopy_2 */
|
|
return CayenneLppCursor;
|
|
8001036: f240 4368 movw r3, #1128 ; 0x468
|
|
800103a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800103e: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8001040: 4618 mov r0, r3
|
|
8001042: 3708 adds r7, #8
|
|
8001044: 46bd mov sp, r7
|
|
8001046: bd80 pop {r7, pc}
|
|
|
|
08001048 <CayenneLppAddTemperature>:
|
|
/* USER CODE END CayenneLppAddPresence_2 */
|
|
return CayenneLppCursor;
|
|
}
|
|
|
|
uint8_t CayenneLppAddTemperature(uint8_t channel, int16_t celsius)
|
|
{
|
|
8001048: b480 push {r7}
|
|
800104a: b085 sub sp, #20
|
|
800104c: af00 add r7, sp, #0
|
|
800104e: 4603 mov r3, r0
|
|
8001050: 460a mov r2, r1
|
|
8001052: 71fb strb r3, [r7, #7]
|
|
8001054: 4613 mov r3, r2
|
|
8001056: 80bb strh r3, [r7, #4]
|
|
/* USER CODE BEGIN CayenneLppAddTemperature_1 */
|
|
|
|
/* USER CODE END CayenneLppAddTemperature_1 */
|
|
if ((CayenneLppCursor + LPP_TEMPERATURE_SIZE) > CAYENNE_LPP_MAXBUFFER_SIZE)
|
|
8001058: f240 4368 movw r3, #1128 ; 0x468
|
|
800105c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001060: 781b ldrb r3, [r3, #0]
|
|
8001062: 2bee cmp r3, #238 ; 0xee
|
|
8001064: d901 bls.n 800106a <CayenneLppAddTemperature+0x22>
|
|
{
|
|
return 0;
|
|
8001066: 2300 movs r3, #0
|
|
8001068: e059 b.n 800111e <CayenneLppAddTemperature+0xd6>
|
|
}
|
|
int16_t val = celsius * 10;
|
|
800106a: 88bb ldrh r3, [r7, #4]
|
|
800106c: 461a mov r2, r3
|
|
800106e: 0092 lsls r2, r2, #2
|
|
8001070: 4413 add r3, r2
|
|
8001072: 005b lsls r3, r3, #1
|
|
8001074: b29b uxth r3, r3
|
|
8001076: 81fb strh r3, [r7, #14]
|
|
CayenneLppBuffer[CayenneLppCursor++] = channel;
|
|
8001078: f240 4368 movw r3, #1128 ; 0x468
|
|
800107c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001080: 781a ldrb r2, [r3, #0]
|
|
8001082: 1c53 adds r3, r2, #1
|
|
8001084: b2d9 uxtb r1, r3
|
|
8001086: f240 4368 movw r3, #1128 ; 0x468
|
|
800108a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800108e: 7019 strb r1, [r3, #0]
|
|
8001090: 4611 mov r1, r2
|
|
8001092: f240 5378 movw r3, #1400 ; 0x578
|
|
8001096: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800109a: 79fa ldrb r2, [r7, #7]
|
|
800109c: 545a strb r2, [r3, r1]
|
|
CayenneLppBuffer[CayenneLppCursor++] = LPP_TEMPERATURE;
|
|
800109e: f240 4368 movw r3, #1128 ; 0x468
|
|
80010a2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80010a6: 781a ldrb r2, [r3, #0]
|
|
80010a8: 1c53 adds r3, r2, #1
|
|
80010aa: b2d9 uxtb r1, r3
|
|
80010ac: f240 4368 movw r3, #1128 ; 0x468
|
|
80010b0: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80010b4: 7019 strb r1, [r3, #0]
|
|
80010b6: f240 5378 movw r3, #1400 ; 0x578
|
|
80010ba: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80010be: 2167 movs r1, #103 ; 0x67
|
|
80010c0: 5499 strb r1, [r3, r2]
|
|
CayenneLppBuffer[CayenneLppCursor++] = val >> 8;
|
|
80010c2: f9b7 300e ldrsh.w r3, [r7, #14]
|
|
80010c6: 121b asrs r3, r3, #8
|
|
80010c8: b219 sxth r1, r3
|
|
80010ca: f240 4368 movw r3, #1128 ; 0x468
|
|
80010ce: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80010d2: 781a ldrb r2, [r3, #0]
|
|
80010d4: 1c53 adds r3, r2, #1
|
|
80010d6: b2d8 uxtb r0, r3
|
|
80010d8: f240 4368 movw r3, #1128 ; 0x468
|
|
80010dc: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80010e0: 7018 strb r0, [r3, #0]
|
|
80010e2: b2c9 uxtb r1, r1
|
|
80010e4: f240 5378 movw r3, #1400 ; 0x578
|
|
80010e8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80010ec: 5499 strb r1, [r3, r2]
|
|
CayenneLppBuffer[CayenneLppCursor++] = val;
|
|
80010ee: f240 4368 movw r3, #1128 ; 0x468
|
|
80010f2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80010f6: 781a ldrb r2, [r3, #0]
|
|
80010f8: 1c53 adds r3, r2, #1
|
|
80010fa: b2d9 uxtb r1, r3
|
|
80010fc: f240 4368 movw r3, #1128 ; 0x468
|
|
8001100: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001104: 7019 strb r1, [r3, #0]
|
|
8001106: 89fb ldrh r3, [r7, #14]
|
|
8001108: b2d9 uxtb r1, r3
|
|
800110a: f240 5378 movw r3, #1400 ; 0x578
|
|
800110e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001112: 5499 strb r1, [r3, r2]
|
|
/* USER CODE BEGIN CayenneLppAddTemperature_2 */
|
|
|
|
/* USER CODE END CayenneLppAddTemperature_2 */
|
|
return CayenneLppCursor;
|
|
8001114: f240 4368 movw r3, #1128 ; 0x468
|
|
8001118: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800111c: 781b ldrb r3, [r3, #0]
|
|
}
|
|
800111e: 4618 mov r0, r3
|
|
8001120: 3714 adds r7, #20
|
|
8001122: 46bd mov sp, r7
|
|
8001124: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001128: 4770 bx lr
|
|
|
|
0800112a <CayenneLppAddRelativeHumidity>:
|
|
|
|
uint8_t CayenneLppAddRelativeHumidity(uint8_t channel, uint16_t rh)
|
|
{
|
|
800112a: b480 push {r7}
|
|
800112c: b083 sub sp, #12
|
|
800112e: af00 add r7, sp, #0
|
|
8001130: 4603 mov r3, r0
|
|
8001132: 460a mov r2, r1
|
|
8001134: 71fb strb r3, [r7, #7]
|
|
8001136: 4613 mov r3, r2
|
|
8001138: 80bb strh r3, [r7, #4]
|
|
/* USER CODE BEGIN CayenneLppAddRelativeHumidity_1 */
|
|
|
|
/* USER CODE END CayenneLppAddRelativeHumidity_1 */
|
|
if ((CayenneLppCursor + LPP_RELATIVE_HUMIDITY_SIZE) > CAYENNE_LPP_MAXBUFFER_SIZE)
|
|
800113a: f240 4368 movw r3, #1128 ; 0x468
|
|
800113e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001142: 781b ldrb r3, [r3, #0]
|
|
8001144: 2bef cmp r3, #239 ; 0xef
|
|
8001146: d901 bls.n 800114c <CayenneLppAddRelativeHumidity+0x22>
|
|
{
|
|
return 0;
|
|
8001148: 2300 movs r3, #0
|
|
800114a: e03e b.n 80011ca <CayenneLppAddRelativeHumidity+0xa0>
|
|
}
|
|
CayenneLppBuffer[CayenneLppCursor++] = channel;
|
|
800114c: f240 4368 movw r3, #1128 ; 0x468
|
|
8001150: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001154: 781a ldrb r2, [r3, #0]
|
|
8001156: 1c53 adds r3, r2, #1
|
|
8001158: b2d9 uxtb r1, r3
|
|
800115a: f240 4368 movw r3, #1128 ; 0x468
|
|
800115e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001162: 7019 strb r1, [r3, #0]
|
|
8001164: 4611 mov r1, r2
|
|
8001166: f240 5378 movw r3, #1400 ; 0x578
|
|
800116a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800116e: 79fa ldrb r2, [r7, #7]
|
|
8001170: 545a strb r2, [r3, r1]
|
|
CayenneLppBuffer[CayenneLppCursor++] = LPP_RELATIVE_HUMIDITY;
|
|
8001172: f240 4368 movw r3, #1128 ; 0x468
|
|
8001176: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800117a: 781a ldrb r2, [r3, #0]
|
|
800117c: 1c53 adds r3, r2, #1
|
|
800117e: b2d9 uxtb r1, r3
|
|
8001180: f240 4368 movw r3, #1128 ; 0x468
|
|
8001184: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001188: 7019 strb r1, [r3, #0]
|
|
800118a: f240 5378 movw r3, #1400 ; 0x578
|
|
800118e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001192: 2168 movs r1, #104 ; 0x68
|
|
8001194: 5499 strb r1, [r3, r2]
|
|
CayenneLppBuffer[CayenneLppCursor++] = rh * 2;
|
|
8001196: 88bb ldrh r3, [r7, #4]
|
|
8001198: b2d9 uxtb r1, r3
|
|
800119a: f240 4368 movw r3, #1128 ; 0x468
|
|
800119e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80011a2: 781a ldrb r2, [r3, #0]
|
|
80011a4: 1c53 adds r3, r2, #1
|
|
80011a6: b2d8 uxtb r0, r3
|
|
80011a8: f240 4368 movw r3, #1128 ; 0x468
|
|
80011ac: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80011b0: 7018 strb r0, [r3, #0]
|
|
80011b2: 004b lsls r3, r1, #1
|
|
80011b4: b2d9 uxtb r1, r3
|
|
80011b6: f240 5378 movw r3, #1400 ; 0x578
|
|
80011ba: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80011be: 5499 strb r1, [r3, r2]
|
|
/* USER CODE BEGIN CayenneLppAddRelativeHumidity_2 */
|
|
|
|
/* USER CODE END CayenneLppAddRelativeHumidity_2 */
|
|
return CayenneLppCursor;
|
|
80011c0: f240 4368 movw r3, #1128 ; 0x468
|
|
80011c4: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80011c8: 781b ldrb r3, [r3, #0]
|
|
}
|
|
80011ca: 4618 mov r0, r3
|
|
80011cc: 370c adds r7, #12
|
|
80011ce: 46bd mov sp, r7
|
|
80011d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80011d4: 4770 bx lr
|
|
|
|
080011d6 <CayenneLppAddBarometricPressure>:
|
|
/* USER CODE END CayenneLppAddAccelerometer_2 */
|
|
return CayenneLppCursor;
|
|
}
|
|
|
|
uint8_t CayenneLppAddBarometricPressure(uint8_t channel, uint16_t hpa)
|
|
{
|
|
80011d6: b480 push {r7}
|
|
80011d8: b083 sub sp, #12
|
|
80011da: af00 add r7, sp, #0
|
|
80011dc: 4603 mov r3, r0
|
|
80011de: 460a mov r2, r1
|
|
80011e0: 71fb strb r3, [r7, #7]
|
|
80011e2: 4613 mov r3, r2
|
|
80011e4: 80bb strh r3, [r7, #4]
|
|
/* USER CODE BEGIN CayenneLppAddBarometricPressure_1 */
|
|
|
|
/* USER CODE END CayenneLppAddBarometricPressure_1 */
|
|
if ((CayenneLppCursor + LPP_BAROMETRIC_PRESSURE_SIZE) > CAYENNE_LPP_MAXBUFFER_SIZE)
|
|
80011e6: f240 4368 movw r3, #1128 ; 0x468
|
|
80011ea: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80011ee: 781b ldrb r3, [r3, #0]
|
|
80011f0: 2bee cmp r3, #238 ; 0xee
|
|
80011f2: d901 bls.n 80011f8 <CayenneLppAddBarometricPressure+0x22>
|
|
{
|
|
return 0;
|
|
80011f4: 2300 movs r3, #0
|
|
80011f6: e057 b.n 80012a8 <CayenneLppAddBarometricPressure+0xd2>
|
|
}
|
|
hpa *= 10;
|
|
80011f8: 88bb ldrh r3, [r7, #4]
|
|
80011fa: 461a mov r2, r3
|
|
80011fc: 0092 lsls r2, r2, #2
|
|
80011fe: 4413 add r3, r2
|
|
8001200: 005b lsls r3, r3, #1
|
|
8001202: 80bb strh r3, [r7, #4]
|
|
|
|
CayenneLppBuffer[CayenneLppCursor++] = channel;
|
|
8001204: f240 4368 movw r3, #1128 ; 0x468
|
|
8001208: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800120c: 781a ldrb r2, [r3, #0]
|
|
800120e: 1c53 adds r3, r2, #1
|
|
8001210: b2d9 uxtb r1, r3
|
|
8001212: f240 4368 movw r3, #1128 ; 0x468
|
|
8001216: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800121a: 7019 strb r1, [r3, #0]
|
|
800121c: 4611 mov r1, r2
|
|
800121e: f240 5378 movw r3, #1400 ; 0x578
|
|
8001222: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001226: 79fa ldrb r2, [r7, #7]
|
|
8001228: 545a strb r2, [r3, r1]
|
|
CayenneLppBuffer[CayenneLppCursor++] = LPP_BAROMETRIC_PRESSURE;
|
|
800122a: f240 4368 movw r3, #1128 ; 0x468
|
|
800122e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001232: 781a ldrb r2, [r3, #0]
|
|
8001234: 1c53 adds r3, r2, #1
|
|
8001236: b2d9 uxtb r1, r3
|
|
8001238: f240 4368 movw r3, #1128 ; 0x468
|
|
800123c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001240: 7019 strb r1, [r3, #0]
|
|
8001242: f240 5378 movw r3, #1400 ; 0x578
|
|
8001246: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800124a: 2173 movs r1, #115 ; 0x73
|
|
800124c: 5499 strb r1, [r3, r2]
|
|
CayenneLppBuffer[CayenneLppCursor++] = hpa >> 8;
|
|
800124e: 88bb ldrh r3, [r7, #4]
|
|
8001250: 0a1b lsrs r3, r3, #8
|
|
8001252: b299 uxth r1, r3
|
|
8001254: f240 4368 movw r3, #1128 ; 0x468
|
|
8001258: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800125c: 781a ldrb r2, [r3, #0]
|
|
800125e: 1c53 adds r3, r2, #1
|
|
8001260: b2d8 uxtb r0, r3
|
|
8001262: f240 4368 movw r3, #1128 ; 0x468
|
|
8001266: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800126a: 7018 strb r0, [r3, #0]
|
|
800126c: b2c9 uxtb r1, r1
|
|
800126e: f240 5378 movw r3, #1400 ; 0x578
|
|
8001272: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001276: 5499 strb r1, [r3, r2]
|
|
CayenneLppBuffer[CayenneLppCursor++] = hpa;
|
|
8001278: f240 4368 movw r3, #1128 ; 0x468
|
|
800127c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001280: 781a ldrb r2, [r3, #0]
|
|
8001282: 1c53 adds r3, r2, #1
|
|
8001284: b2d9 uxtb r1, r3
|
|
8001286: f240 4368 movw r3, #1128 ; 0x468
|
|
800128a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800128e: 7019 strb r1, [r3, #0]
|
|
8001290: 88bb ldrh r3, [r7, #4]
|
|
8001292: b2d9 uxtb r1, r3
|
|
8001294: f240 5378 movw r3, #1400 ; 0x578
|
|
8001298: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800129c: 5499 strb r1, [r3, r2]
|
|
/* USER CODE BEGIN CayenneLppAddBarometricPressure_2 */
|
|
|
|
/* USER CODE END CayenneLppAddBarometricPressure_2 */
|
|
return CayenneLppCursor;
|
|
800129e: f240 4368 movw r3, #1128 ; 0x468
|
|
80012a2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80012a6: 781b ldrb r3, [r3, #0]
|
|
}
|
|
80012a8: 4618 mov r0, r3
|
|
80012aa: 370c adds r7, #12
|
|
80012ac: 46bd mov sp, r7
|
|
80012ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80012b2: 4770 bx lr
|
|
|
|
080012b4 <memory_erasePage>:
|
|
|
|
|
|
FLASH_EraseInitTypeDef Flash_EraseConfig;
|
|
|
|
HAL_StatusTypeDef memory_erasePage(uint8_t pageNumber)
|
|
{
|
|
80012b4: b580 push {r7, lr}
|
|
80012b6: b084 sub sp, #16
|
|
80012b8: af00 add r7, sp, #0
|
|
80012ba: 4603 mov r3, r0
|
|
80012bc: 71fb strb r3, [r7, #7]
|
|
HAL_StatusTypeDef rslt= HAL_OK;
|
|
80012be: 2300 movs r3, #0
|
|
80012c0: 73fb strb r3, [r7, #15]
|
|
uint32_t pageFault=0;
|
|
80012c2: 2300 movs r3, #0
|
|
80012c4: 60bb str r3, [r7, #8]
|
|
|
|
Flash_EraseConfig.TypeErase= FLASH_TYPEERASE_PAGES;
|
|
80012c6: f240 636c movw r3, #1644 ; 0x66c
|
|
80012ca: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80012ce: 2200 movs r2, #0
|
|
80012d0: 601a str r2, [r3, #0]
|
|
Flash_EraseConfig.Banks =FLASH_BANK_1;
|
|
80012d2: f240 636c movw r3, #1644 ; 0x66c
|
|
80012d6: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80012da: 2201 movs r2, #1
|
|
80012dc: 605a str r2, [r3, #4]
|
|
Flash_EraseConfig.Page =pageNumber;
|
|
80012de: 79fa ldrb r2, [r7, #7]
|
|
80012e0: f240 636c movw r3, #1644 ; 0x66c
|
|
80012e4: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80012e8: 609a str r2, [r3, #8]
|
|
Flash_EraseConfig.NbPages= 1 ; //1page =4kB
|
|
80012ea: f240 636c movw r3, #1644 ; 0x66c
|
|
80012ee: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80012f2: 2201 movs r2, #1
|
|
80012f4: 60da str r2, [r3, #12]
|
|
rslt=HAL_FLASH_Unlock();
|
|
80012f6: f005 fa6d bl 80067d4 <HAL_FLASH_Unlock>
|
|
80012fa: 4603 mov r3, r0
|
|
80012fc: 73fb strb r3, [r7, #15]
|
|
|
|
rslt=HAL_FLASHEx_Erase(&Flash_EraseConfig, &pageFault);
|
|
80012fe: f107 0308 add.w r3, r7, #8
|
|
8001302: 4619 mov r1, r3
|
|
8001304: f240 606c movw r0, #1644 ; 0x66c
|
|
8001308: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800130c: f005 fb75 bl 80069fa <HAL_FLASHEx_Erase>
|
|
8001310: 4603 mov r3, r0
|
|
8001312: 73fb strb r3, [r7, #15]
|
|
rslt=HAL_FLASH_Lock();
|
|
8001314: f005 fa8c bl 8006830 <HAL_FLASH_Lock>
|
|
8001318: 4603 mov r3, r0
|
|
800131a: 73fb strb r3, [r7, #15]
|
|
|
|
return rslt;
|
|
800131c: 7bfb ldrb r3, [r7, #15]
|
|
|
|
}
|
|
800131e: 4618 mov r0, r3
|
|
8001320: 3710 adds r7, #16
|
|
8001322: 46bd mov sp, r7
|
|
8001324: bd80 pop {r7, pc}
|
|
|
|
08001326 <memory_write>:
|
|
|
|
|
|
|
|
HAL_StatusTypeDef memory_write(uint8_t *p_wr,uint32_t addressToWrite)
|
|
{
|
|
8001326: b580 push {r7, lr}
|
|
8001328: b086 sub sp, #24
|
|
800132a: af00 add r7, sp, #0
|
|
800132c: 6078 str r0, [r7, #4]
|
|
800132e: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef rslt= HAL_OK;
|
|
8001330: 2300 movs r3, #0
|
|
8001332: 73fb strb r3, [r7, #15]
|
|
|
|
uint64_t *dataToWrite=0;
|
|
8001334: 2300 movs r3, #0
|
|
8001336: 60bb str r3, [r7, #8]
|
|
dataToWrite= (uint64_t *) p_wr;
|
|
8001338: 687b ldr r3, [r7, #4]
|
|
800133a: 60bb str r3, [r7, #8]
|
|
|
|
uint8_t len=sizeof(dataToWrite)/sizeof(uint64_t);
|
|
800133c: 2300 movs r3, #0
|
|
800133e: 75fb strb r3, [r7, #23]
|
|
if(len<=1)
|
|
8001340: 7dfb ldrb r3, [r7, #23]
|
|
8001342: 2b01 cmp r3, #1
|
|
8001344: d801 bhi.n 800134a <memory_write+0x24>
|
|
len=1;
|
|
8001346: 2301 movs r3, #1
|
|
8001348: 75fb strb r3, [r7, #23]
|
|
|
|
rslt=HAL_FLASH_Unlock();
|
|
800134a: f005 fa43 bl 80067d4 <HAL_FLASH_Unlock>
|
|
800134e: 4603 mov r3, r0
|
|
8001350: 73fb strb r3, [r7, #15]
|
|
if(rslt==HAL_OK)
|
|
8001352: 7bfb ldrb r3, [r7, #15]
|
|
8001354: 2b00 cmp r3, #0
|
|
8001356: d123 bne.n 80013a0 <memory_write+0x7a>
|
|
{
|
|
|
|
for(uint32_t i=0; i<=len; i++)
|
|
8001358: 2300 movs r3, #0
|
|
800135a: 613b str r3, [r7, #16]
|
|
800135c: e016 b.n 800138c <memory_write+0x66>
|
|
{
|
|
rslt=HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addressToWrite, dataToWrite[i]);
|
|
800135e: 693b ldr r3, [r7, #16]
|
|
8001360: 00db lsls r3, r3, #3
|
|
8001362: 68ba ldr r2, [r7, #8]
|
|
8001364: 4413 add r3, r2
|
|
8001366: e9d3 2300 ldrd r2, r3, [r3]
|
|
800136a: 6839 ldr r1, [r7, #0]
|
|
800136c: 2000 movs r0, #0
|
|
800136e: f005 f9a9 bl 80066c4 <HAL_FLASH_Program>
|
|
8001372: 4603 mov r3, r0
|
|
8001374: 73fb strb r3, [r7, #15]
|
|
if(rslt!= HAL_OK)
|
|
8001376: 7bfb ldrb r3, [r7, #15]
|
|
8001378: 2b00 cmp r3, #0
|
|
800137a: d001 beq.n 8001380 <memory_write+0x5a>
|
|
{
|
|
return rslt;
|
|
800137c: 7bfb ldrb r3, [r7, #15]
|
|
800137e: e010 b.n 80013a2 <memory_write+0x7c>
|
|
}
|
|
addressToWrite+=8;
|
|
8001380: 683b ldr r3, [r7, #0]
|
|
8001382: 3308 adds r3, #8
|
|
8001384: 603b str r3, [r7, #0]
|
|
for(uint32_t i=0; i<=len; i++)
|
|
8001386: 693b ldr r3, [r7, #16]
|
|
8001388: 3301 adds r3, #1
|
|
800138a: 613b str r3, [r7, #16]
|
|
800138c: 7dfb ldrb r3, [r7, #23]
|
|
800138e: 693a ldr r2, [r7, #16]
|
|
8001390: 429a cmp r2, r3
|
|
8001392: d9e4 bls.n 800135e <memory_write+0x38>
|
|
}
|
|
rslt=HAL_FLASH_Lock();
|
|
8001394: f005 fa4c bl 8006830 <HAL_FLASH_Lock>
|
|
8001398: 4603 mov r3, r0
|
|
800139a: 73fb strb r3, [r7, #15]
|
|
return rslt;
|
|
800139c: 7bfb ldrb r3, [r7, #15]
|
|
800139e: e000 b.n 80013a2 <memory_write+0x7c>
|
|
}
|
|
else
|
|
return rslt;
|
|
80013a0: 7bfb ldrb r3, [r7, #15]
|
|
|
|
}
|
|
80013a2: 4618 mov r0, r3
|
|
80013a4: 3718 adds r7, #24
|
|
80013a6: 46bd mov sp, r7
|
|
80013a8: bd80 pop {r7, pc}
|
|
|
|
080013aa <memory_read>:
|
|
|
|
HAL_StatusTypeDef memory_read(uint8_t *p_rd,uint32_t addressToRead, size_t size)
|
|
{
|
|
80013aa: b580 push {r7, lr}
|
|
80013ac: b086 sub sp, #24
|
|
80013ae: af00 add r7, sp, #0
|
|
80013b0: 60f8 str r0, [r7, #12]
|
|
80013b2: 60b9 str r1, [r7, #8]
|
|
80013b4: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef rslt=HAL_OK;
|
|
80013b6: 2300 movs r3, #0
|
|
80013b8: 74fb strb r3, [r7, #19]
|
|
rslt=HAL_FLASH_Unlock();
|
|
80013ba: f005 fa0b bl 80067d4 <HAL_FLASH_Unlock>
|
|
80013be: 4603 mov r3, r0
|
|
80013c0: 74fb strb r3, [r7, #19]
|
|
if(rslt==HAL_OK)
|
|
80013c2: 7cfb ldrb r3, [r7, #19]
|
|
80013c4: 2b00 cmp r3, #0
|
|
80013c6: d114 bne.n 80013f2 <memory_read+0x48>
|
|
{
|
|
for(uint32_t i=0; i<size; i++)
|
|
80013c8: 2300 movs r3, #0
|
|
80013ca: 617b str r3, [r7, #20]
|
|
80013cc: e00b b.n 80013e6 <memory_read+0x3c>
|
|
{
|
|
*((uint8_t *)p_rd + i) = *(uint8_t *)addressToRead;
|
|
80013ce: 68ba ldr r2, [r7, #8]
|
|
80013d0: 68f9 ldr r1, [r7, #12]
|
|
80013d2: 697b ldr r3, [r7, #20]
|
|
80013d4: 440b add r3, r1
|
|
80013d6: 7812 ldrb r2, [r2, #0]
|
|
80013d8: 701a strb r2, [r3, #0]
|
|
addressToRead++;
|
|
80013da: 68bb ldr r3, [r7, #8]
|
|
80013dc: 3301 adds r3, #1
|
|
80013de: 60bb str r3, [r7, #8]
|
|
for(uint32_t i=0; i<size; i++)
|
|
80013e0: 697b ldr r3, [r7, #20]
|
|
80013e2: 3301 adds r3, #1
|
|
80013e4: 617b str r3, [r7, #20]
|
|
80013e6: 697a ldr r2, [r7, #20]
|
|
80013e8: 687b ldr r3, [r7, #4]
|
|
80013ea: 429a cmp r2, r3
|
|
80013ec: d3ef bcc.n 80013ce <memory_read+0x24>
|
|
}
|
|
return rslt;
|
|
80013ee: 7cfb ldrb r3, [r7, #19]
|
|
80013f0: e000 b.n 80013f4 <memory_read+0x4a>
|
|
}
|
|
else
|
|
return rslt;
|
|
80013f2: 7cfb ldrb r3, [r7, #19]
|
|
}
|
|
80013f4: 4618 mov r0, r3
|
|
80013f6: 3718 adds r7, #24
|
|
80013f8: 46bd mov sp, r7
|
|
80013fa: bd80 pop {r7, pc}
|
|
|
|
080013fc <user_i2c_read>:
|
|
#include "i2c.h"
|
|
|
|
|
|
|
|
int8_t user_i2c_read(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len)
|
|
{
|
|
80013fc: b580 push {r7, lr}
|
|
80013fe: b08a sub sp, #40 ; 0x28
|
|
8001400: af04 add r7, sp, #16
|
|
8001402: 603a str r2, [r7, #0]
|
|
8001404: 461a mov r2, r3
|
|
8001406: 4603 mov r3, r0
|
|
8001408: 71fb strb r3, [r7, #7]
|
|
800140a: 460b mov r3, r1
|
|
800140c: 71bb strb r3, [r7, #6]
|
|
800140e: 4613 mov r3, r2
|
|
8001410: 80bb strh r3, [r7, #4]
|
|
int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */
|
|
8001412: 2300 movs r3, #0
|
|
8001414: 75fb strb r3, [r7, #23]
|
|
uint32_t error=0;
|
|
8001416: 2300 movs r3, #0
|
|
8001418: 613b str r3, [r7, #16]
|
|
uint8_t read_addr=(dev_id<<1);
|
|
800141a: 79fb ldrb r3, [r7, #7]
|
|
800141c: 005b lsls r3, r3, #1
|
|
800141e: 73fb strb r3, [r7, #15]
|
|
|
|
|
|
|
|
|
|
rslt=HAL_I2C_Mem_Read(&hi2c1,(uint16_t)read_addr,reg_addr,I2C_MEMADD_SIZE_8BIT,reg_data, len, 1000);
|
|
8001420: 7bfb ldrb r3, [r7, #15]
|
|
8001422: b299 uxth r1, r3
|
|
8001424: 79bb ldrb r3, [r7, #6]
|
|
8001426: b29a uxth r2, r3
|
|
8001428: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
800142c: 9302 str r3, [sp, #8]
|
|
800142e: 88bb ldrh r3, [r7, #4]
|
|
8001430: 9301 str r3, [sp, #4]
|
|
8001432: 683b ldr r3, [r7, #0]
|
|
8001434: 9300 str r3, [sp, #0]
|
|
8001436: 2301 movs r3, #1
|
|
8001438: f640 0044 movw r0, #2116 ; 0x844
|
|
800143c: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001440: f006 f835 bl 80074ae <HAL_I2C_Mem_Read>
|
|
8001444: 4603 mov r3, r0
|
|
8001446: 75fb strb r3, [r7, #23]
|
|
* | Read | (reg_data[len - 1]) |
|
|
* | Stop | - |
|
|
* |------------+---------------------|
|
|
*/
|
|
|
|
return rslt;
|
|
8001448: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
800144c: 4618 mov r0, r3
|
|
800144e: 3718 adds r7, #24
|
|
8001450: 46bd mov sp, r7
|
|
8001452: bd80 pop {r7, pc}
|
|
|
|
08001454 <user_i2c_write>:
|
|
|
|
|
|
int8_t user_i2c_write(uint8_t dev_id, uint8_t reg_addr, uint8_t *reg_data, uint16_t len)
|
|
{
|
|
8001454: b580 push {r7, lr}
|
|
8001456: b088 sub sp, #32
|
|
8001458: af04 add r7, sp, #16
|
|
800145a: 603a str r2, [r7, #0]
|
|
800145c: 461a mov r2, r3
|
|
800145e: 4603 mov r3, r0
|
|
8001460: 71fb strb r3, [r7, #7]
|
|
8001462: 460b mov r3, r1
|
|
8001464: 71bb strb r3, [r7, #6]
|
|
8001466: 4613 mov r3, r2
|
|
8001468: 80bb strh r3, [r7, #4]
|
|
int8_t rslt = 0; /* Return 0 for Success, non-zero for failure */
|
|
800146a: 2300 movs r3, #0
|
|
800146c: 73fb strb r3, [r7, #15]
|
|
|
|
uint8_t write_addr=(dev_id<<1);
|
|
800146e: 79fb ldrb r3, [r7, #7]
|
|
8001470: 005b lsls r3, r3, #1
|
|
8001472: 73bb strb r3, [r7, #14]
|
|
rslt=HAL_I2C_Mem_Write(&hi2c1,(uint16_t)write_addr,reg_addr,I2C_MEMADD_SIZE_8BIT,reg_data, len, 1000);
|
|
8001474: 7bbb ldrb r3, [r7, #14]
|
|
8001476: b299 uxth r1, r3
|
|
8001478: 79bb ldrb r3, [r7, #6]
|
|
800147a: b29a uxth r2, r3
|
|
800147c: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
8001480: 9302 str r3, [sp, #8]
|
|
8001482: 88bb ldrh r3, [r7, #4]
|
|
8001484: 9301 str r3, [sp, #4]
|
|
8001486: 683b ldr r3, [r7, #0]
|
|
8001488: 9300 str r3, [sp, #0]
|
|
800148a: 2301 movs r3, #1
|
|
800148c: f640 0044 movw r0, #2116 ; 0x844
|
|
8001490: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001494: f005 fef6 bl 8007284 <HAL_I2C_Mem_Write>
|
|
8001498: 4603 mov r3, r0
|
|
800149a: 73fb strb r3, [r7, #15]
|
|
* | Write | (reg_data[len - 1]) |
|
|
* | Stop | - |
|
|
* |------------+---------------------|
|
|
*/
|
|
|
|
return rslt;
|
|
800149c: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
80014a0: 4618 mov r0, r3
|
|
80014a2: 3710 adds r7, #16
|
|
80014a4: 46bd mov sp, r7
|
|
80014a6: bd80 pop {r7, pc}
|
|
|
|
080014a8 <LoRa_init>:
|
|
uint8_t lowpoweron[]="AT+LOWPOWER=AUTOON\r\n";
|
|
uint8_t lowpoweroff[]="AT+LOWPOWER=AUTOOFF\r\n";
|
|
|
|
|
|
HAL_StatusTypeDef LoRa_init()
|
|
{
|
|
80014a8: b580 push {r7, lr}
|
|
80014aa: b08a sub sp, #40 ; 0x28
|
|
80014ac: af00 add r7, sp, #0
|
|
uint8_t rslt=HAL_OK;
|
|
80014ae: 2300 movs r3, #0
|
|
80014b0: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
uint8_t wkup[32]={0xff,0xff,0xff,0xff};
|
|
80014b4: f24e 2244 movw r2, #57924 ; 0xe244
|
|
80014b8: f6c0 0200 movt r2, #2048 ; 0x800
|
|
80014bc: 1d3b adds r3, r7, #4
|
|
80014be: e892 0003 ldmia.w r2, {r0, r1}
|
|
80014c2: 6018 str r0, [r3, #0]
|
|
80014c4: 3304 adds r3, #4
|
|
80014c6: 7019 strb r1, [r3, #0]
|
|
80014c8: f107 0309 add.w r3, r7, #9
|
|
80014cc: 2200 movs r2, #0
|
|
80014ce: 601a str r2, [r3, #0]
|
|
80014d0: 605a str r2, [r3, #4]
|
|
80014d2: 609a str r2, [r3, #8]
|
|
80014d4: 60da str r2, [r3, #12]
|
|
80014d6: 611a str r2, [r3, #16]
|
|
80014d8: 615a str r2, [r3, #20]
|
|
80014da: f8c3 2017 str.w r2, [r3, #23]
|
|
sprintf((char*)&wkup+4,"%s",lowpoweroff);
|
|
80014de: 1d3b adds r3, r7, #4
|
|
80014e0: 3304 adds r3, #4
|
|
80014e2: f240 2234 movw r2, #564 ; 0x234
|
|
80014e6: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
80014ea: f24e 2118 movw r1, #57880 ; 0xe218
|
|
80014ee: f6c0 0100 movt r1, #2048 ; 0x800
|
|
80014f2: 4618 mov r0, r3
|
|
80014f4: f00a fa40 bl 800b978 <siprintf>
|
|
|
|
at_send(&huart2,wkup,1000,strlen((char*)wkup));
|
|
80014f8: 1d3b adds r3, r7, #4
|
|
80014fa: 4618 mov r0, r3
|
|
80014fc: f7fe fe68 bl 80001d0 <strlen>
|
|
8001500: 4603 mov r3, r0
|
|
8001502: b2db uxtb r3, r3
|
|
8001504: 1d39 adds r1, r7, #4
|
|
8001506: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
800150a: f640 109c movw r0, #2460 ; 0x99c
|
|
800150e: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001512: f001 fe6f bl 80031f4 <at_send>
|
|
rslt=at_send(&huart2,ping , 1000, strlen((char*)ping));
|
|
8001516: f240 0000 movw r0, #0
|
|
800151a: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800151e: f7fe fe57 bl 80001d0 <strlen>
|
|
8001522: 4603 mov r3, r0
|
|
8001524: b2db uxtb r3, r3
|
|
8001526: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
800152a: f240 0100 movw r1, #0
|
|
800152e: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001532: f640 109c movw r0, #2460 ; 0x99c
|
|
8001536: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800153a: f001 fe5b bl 80031f4 <at_send>
|
|
800153e: 4603 mov r3, r0
|
|
8001540: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
rslt=at_send(&huart2,(uint8_t*)"AT+UART=TIMEOUT,0\r\n",2000,strlen((char*)("AT+UART=TIMEOUT, 0\r\n")));
|
|
8001544: 2314 movs r3, #20
|
|
8001546: f44f 62fa mov.w r2, #2000 ; 0x7d0
|
|
800154a: f24e 211c movw r1, #57884 ; 0xe21c
|
|
800154e: f6c0 0100 movt r1, #2048 ; 0x800
|
|
8001552: f640 109c movw r0, #2460 ; 0x99c
|
|
8001556: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800155a: f001 fe4b bl 80031f4 <at_send>
|
|
800155e: 4603 mov r3, r0
|
|
8001560: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
rslt=at_send(&huart2,(uint8_t*)"AT+UART=BR,115200\r\n",2000,strlen((char*)("AT+UART=BR,115200\r\n")));
|
|
8001564: 2313 movs r3, #19
|
|
8001566: f44f 62fa mov.w r2, #2000 ; 0x7d0
|
|
800156a: f24e 2130 movw r1, #57904 ; 0xe230
|
|
800156e: f6c0 0100 movt r1, #2048 ; 0x800
|
|
8001572: f640 109c movw r0, #2460 ; 0x99c
|
|
8001576: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800157a: f001 fe3b bl 80031f4 <at_send>
|
|
800157e: 4603 mov r3, r0
|
|
8001580: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
huart2.Init.BaudRate=115200;
|
|
8001584: f640 139c movw r3, #2460 ; 0x99c
|
|
8001588: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800158c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
8001590: 605a str r2, [r3, #4]
|
|
HAL_UART_Init(&huart2);
|
|
8001592: f640 109c movw r0, #2460 ; 0x99c
|
|
8001596: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800159a: f008 fc65 bl 8009e68 <HAL_UART_Init>
|
|
rslt=at_send(&huart2, getVer, 1000,strlen((char*)getVer));
|
|
800159e: f240 0008 movw r0, #8
|
|
80015a2: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80015a6: f7fe fe13 bl 80001d0 <strlen>
|
|
80015aa: 4603 mov r3, r0
|
|
80015ac: b2db uxtb r3, r3
|
|
80015ae: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
80015b2: f240 0108 movw r1, #8
|
|
80015b6: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
80015ba: f640 109c movw r0, #2460 ; 0x99c
|
|
80015be: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80015c2: f001 fe17 bl 80031f4 <at_send>
|
|
80015c6: 4603 mov r3, r0
|
|
80015c8: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
rslt=at_send(&huart2, setDevEui, 1000,strlen((char*)setDevEui));
|
|
80015cc: f240 0014 movw r0, #20
|
|
80015d0: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80015d4: f7fe fdfc bl 80001d0 <strlen>
|
|
80015d8: 4603 mov r3, r0
|
|
80015da: b2db uxtb r3, r3
|
|
80015dc: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
80015e0: f240 0114 movw r1, #20
|
|
80015e4: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
80015e8: f640 109c movw r0, #2460 ; 0x99c
|
|
80015ec: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80015f0: f001 fe00 bl 80031f4 <at_send>
|
|
80015f4: 4603 mov r3, r0
|
|
80015f6: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
rslt=at_send(&huart2, getAppEui, 1000,strlen((char*)getAppEui));
|
|
80015fa: f240 0034 movw r0, #52 ; 0x34
|
|
80015fe: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001602: f7fe fde5 bl 80001d0 <strlen>
|
|
8001606: 4603 mov r3, r0
|
|
8001608: b2db uxtb r3, r3
|
|
800160a: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
800160e: f240 0134 movw r1, #52 ; 0x34
|
|
8001612: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001616: f640 109c movw r0, #2460 ; 0x99c
|
|
800161a: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800161e: f001 fde9 bl 80031f4 <at_send>
|
|
8001622: 4603 mov r3, r0
|
|
8001624: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
rslt=at_send(&huart2,setKey,1000,strlen((char*)setKey));
|
|
8001628: f240 0044 movw r0, #68 ; 0x44
|
|
800162c: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001630: f7fe fdce bl 80001d0 <strlen>
|
|
8001634: 4603 mov r3, r0
|
|
8001636: b2db uxtb r3, r3
|
|
8001638: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
800163c: f240 0144 movw r1, #68 ; 0x44
|
|
8001640: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001644: f640 109c movw r0, #2460 ; 0x99c
|
|
8001648: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800164c: f001 fdd2 bl 80031f4 <at_send>
|
|
8001650: 4603 mov r3, r0
|
|
8001652: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
rslt=at_send(&huart2,DR,1000,strlen((char*)DR));
|
|
8001656: f240 0098 movw r0, #152 ; 0x98
|
|
800165a: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800165e: f7fe fdb7 bl 80001d0 <strlen>
|
|
8001662: 4603 mov r3, r0
|
|
8001664: b2db uxtb r3, r3
|
|
8001666: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
800166a: f240 0198 movw r1, #152 ; 0x98
|
|
800166e: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001672: f640 109c movw r0, #2460 ; 0x99c
|
|
8001676: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800167a: f001 fdbb bl 80031f4 <at_send>
|
|
800167e: 4603 mov r3, r0
|
|
8001680: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
rslt=at_send(&huart2,ADR,1000,strlen((char*)ADR));
|
|
8001684: f240 00a4 movw r0, #164 ; 0xa4
|
|
8001688: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800168c: f7fe fda0 bl 80001d0 <strlen>
|
|
8001690: 4603 mov r3, r0
|
|
8001692: b2db uxtb r3, r3
|
|
8001694: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
8001698: f240 01a4 movw r1, #164 ; 0xa4
|
|
800169c: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
80016a0: f640 109c movw r0, #2460 ; 0x99c
|
|
80016a4: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80016a8: f001 fda4 bl 80031f4 <at_send>
|
|
80016ac: 4603 mov r3, r0
|
|
80016ae: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
|
|
|
|
if(LoRa_join())
|
|
80016b2: f000 f828 bl 8001706 <LoRa_join>
|
|
80016b6: 4603 mov r3, r0
|
|
80016b8: 2b00 cmp r3, #0
|
|
80016ba: d001 beq.n 80016c0 <LoRa_init+0x218>
|
|
{
|
|
return HAL_ERROR;
|
|
80016bc: 2301 movs r3, #1
|
|
80016be: e01e b.n 80016fe <LoRa_init+0x256>
|
|
}
|
|
else
|
|
{
|
|
AppData.is_join=1;
|
|
80016c0: f240 2310 movw r3, #528 ; 0x210
|
|
80016c4: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80016c8: 2201 movs r2, #1
|
|
80016ca: 725a strb r2, [r3, #9]
|
|
}
|
|
|
|
|
|
|
|
rslt=at_send(&huart2, lowpoweron, 1000, strlen((char*)lowpoweron));
|
|
80016cc: f240 201c movw r0, #540 ; 0x21c
|
|
80016d0: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80016d4: f7fe fd7c bl 80001d0 <strlen>
|
|
80016d8: 4603 mov r3, r0
|
|
80016da: b2db uxtb r3, r3
|
|
80016dc: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
80016e0: f240 211c movw r1, #540 ; 0x21c
|
|
80016e4: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
80016e8: f640 109c movw r0, #2460 ; 0x99c
|
|
80016ec: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80016f0: f001 fd80 bl 80031f4 <at_send>
|
|
80016f4: 4603 mov r3, r0
|
|
80016f6: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
return rslt;
|
|
80016fa: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
80016fe: 4618 mov r0, r3
|
|
8001700: 3728 adds r7, #40 ; 0x28
|
|
8001702: 46bd mov sp, r7
|
|
8001704: bd80 pop {r7, pc}
|
|
|
|
08001706 <LoRa_join>:
|
|
|
|
HAL_StatusTypeDef LoRa_join()
|
|
{
|
|
8001706: b580 push {r7, lr}
|
|
8001708: b084 sub sp, #16
|
|
800170a: af02 add r7, sp, #8
|
|
uint8_t rslt=HAL_OK;
|
|
800170c: 2300 movs r3, #0
|
|
800170e: 71fb strb r3, [r7, #7]
|
|
|
|
rslt=at_send(&huart2, modeOTAA, 1000,strlen((char*)modeOTAA));
|
|
8001710: f240 0078 movw r0, #120 ; 0x78
|
|
8001714: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001718: f7fe fd5a bl 80001d0 <strlen>
|
|
800171c: 4603 mov r3, r0
|
|
800171e: b2db uxtb r3, r3
|
|
8001720: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
8001724: f240 0178 movw r1, #120 ; 0x78
|
|
8001728: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
800172c: f640 109c movw r0, #2460 ; 0x99c
|
|
8001730: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001734: f001 fd5e bl 80031f4 <at_send>
|
|
8001738: 4603 mov r3, r0
|
|
800173a: 71fb strb r3, [r7, #7]
|
|
rslt=at_Com(&huart2, join,rcv, 10000,strlen((char*)join));
|
|
800173c: f240 008c movw r0, #140 ; 0x8c
|
|
8001740: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001744: f7fe fd44 bl 80001d0 <strlen>
|
|
8001748: 4603 mov r3, r0
|
|
800174a: b2db uxtb r3, r3
|
|
800174c: 9300 str r3, [sp, #0]
|
|
800174e: f242 7310 movw r3, #10000 ; 0x2710
|
|
8001752: f240 426c movw r2, #1132 ; 0x46c
|
|
8001756: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
800175a: f240 018c movw r1, #140 ; 0x8c
|
|
800175e: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001762: f640 109c movw r0, #2460 ; 0x99c
|
|
8001766: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800176a: f001 fcbe bl 80030ea <at_Com>
|
|
800176e: 4603 mov r3, r0
|
|
8001770: 71fb strb r3, [r7, #7]
|
|
char* ack=strstr((char*)rcv,(char*)joinedrcv);
|
|
8001772: f240 11f8 movw r1, #504 ; 0x1f8
|
|
8001776: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
800177a: f240 406c movw r0, #1132 ; 0x46c
|
|
800177e: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001782: f00a f919 bl 800b9b8 <strstr>
|
|
8001786: 6038 str r0, [r7, #0]
|
|
if(ack!=NULL)
|
|
8001788: 683b ldr r3, [r7, #0]
|
|
800178a: 2b00 cmp r3, #0
|
|
800178c: d001 beq.n 8001792 <LoRa_join+0x8c>
|
|
return HAL_BUSY;
|
|
800178e: 2302 movs r3, #2
|
|
8001790: e000 b.n 8001794 <LoRa_join+0x8e>
|
|
return rslt;
|
|
8001792: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8001794: 4618 mov r0, r3
|
|
8001796: 3708 adds r7, #8
|
|
8001798: 46bd mov sp, r7
|
|
800179a: bd80 pop {r7, pc}
|
|
|
|
0800179c <LoRa_send>:
|
|
|
|
HAL_StatusTypeDef LoRa_send(uint8_t port, uint8_t *message,uint8_t size)
|
|
{
|
|
800179c: b590 push {r4, r7, lr}
|
|
800179e: b0c9 sub sp, #292 ; 0x124
|
|
80017a0: af02 add r7, sp, #8
|
|
80017a2: 463b mov r3, r7
|
|
80017a4: 6019 str r1, [r3, #0]
|
|
80017a6: 4611 mov r1, r2
|
|
80017a8: 1dfb adds r3, r7, #7
|
|
80017aa: 4602 mov r2, r0
|
|
80017ac: 701a strb r2, [r3, #0]
|
|
80017ae: 1dbb adds r3, r7, #6
|
|
80017b0: 460a mov r2, r1
|
|
80017b2: 701a strb r2, [r3, #0]
|
|
uint8_t rslt=HAL_OK;
|
|
80017b4: 2300 movs r3, #0
|
|
80017b6: f887 3113 strb.w r3, [r7, #275] ; 0x113
|
|
uint8_t rcv[256]={0};
|
|
80017ba: f107 030c add.w r3, r7, #12
|
|
80017be: 2200 movs r2, #0
|
|
80017c0: 601a str r2, [r3, #0]
|
|
80017c2: 3304 adds r3, #4
|
|
80017c4: 22fc movs r2, #252 ; 0xfc
|
|
80017c6: 2100 movs r1, #0
|
|
80017c8: 4618 mov r0, r3
|
|
80017ca: f009 fbd5 bl 800af78 <memset>
|
|
|
|
setPort[8]=port+'0';
|
|
80017ce: 1dfb adds r3, r7, #7
|
|
80017d0: 781b ldrb r3, [r3, #0]
|
|
80017d2: 3330 adds r3, #48 ; 0x30
|
|
80017d4: b2da uxtb r2, r3
|
|
80017d6: f240 03b0 movw r3, #176 ; 0xb0
|
|
80017da: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80017de: 721a strb r2, [r3, #8]
|
|
|
|
|
|
printf("%s",setPort);
|
|
80017e0: f240 01b0 movw r1, #176 ; 0xb0
|
|
80017e4: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
80017e8: f24e 2018 movw r0, #57880 ; 0xe218
|
|
80017ec: f6c0 0000 movt r0, #2048 ; 0x800
|
|
80017f0: f00a f834 bl 800b85c <iprintf>
|
|
rslt+=at_send(&huart2, setPort , 1000,strlen((char*)setPort));
|
|
80017f4: f240 00b0 movw r0, #176 ; 0xb0
|
|
80017f8: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80017fc: f7fe fce8 bl 80001d0 <strlen>
|
|
8001800: 4603 mov r3, r0
|
|
8001802: b2db uxtb r3, r3
|
|
8001804: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
8001808: f240 01b0 movw r1, #176 ; 0xb0
|
|
800180c: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001810: f640 109c movw r0, #2460 ; 0x99c
|
|
8001814: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001818: f001 fcec bl 80031f4 <at_send>
|
|
800181c: 4603 mov r3, r0
|
|
800181e: 461a mov r2, r3
|
|
8001820: f897 3113 ldrb.w r3, [r7, #275] ; 0x113
|
|
8001824: 4413 add r3, r2
|
|
8001826: f887 3113 strb.w r3, [r7, #275] ; 0x113
|
|
uint8_t len=strlen((char*)sendMsg);
|
|
800182a: f240 00bc movw r0, #188 ; 0xbc
|
|
800182e: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001832: f7fe fccd bl 80001d0 <strlen>
|
|
8001836: 4603 mov r3, r0
|
|
8001838: f887 3112 strb.w r3, [r7, #274] ; 0x112
|
|
for(int i=0;i<size;i++)
|
|
800183c: 2300 movs r3, #0
|
|
800183e: f8c7 3114 str.w r3, [r7, #276] ; 0x114
|
|
8001842: e01c b.n 800187e <LoRa_send+0xe2>
|
|
{
|
|
sprintf((char*)&sendMsg[len+2*i],"%02x",message[i]);
|
|
8001844: f897 2112 ldrb.w r2, [r7, #274] ; 0x112
|
|
8001848: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114
|
|
800184c: 005b lsls r3, r3, #1
|
|
800184e: 441a add r2, r3
|
|
8001850: f240 03bc movw r3, #188 ; 0xbc
|
|
8001854: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001858: 18d0 adds r0, r2, r3
|
|
800185a: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114
|
|
800185e: 463a mov r2, r7
|
|
8001860: 6812 ldr r2, [r2, #0]
|
|
8001862: 4413 add r3, r2
|
|
8001864: 781b ldrb r3, [r3, #0]
|
|
8001866: 461a mov r2, r3
|
|
8001868: f24e 2164 movw r1, #57956 ; 0xe264
|
|
800186c: f6c0 0100 movt r1, #2048 ; 0x800
|
|
8001870: f00a f882 bl 800b978 <siprintf>
|
|
for(int i=0;i<size;i++)
|
|
8001874: f8d7 3114 ldr.w r3, [r7, #276] ; 0x114
|
|
8001878: 3301 adds r3, #1
|
|
800187a: f8c7 3114 str.w r3, [r7, #276] ; 0x114
|
|
800187e: 1dbb adds r3, r7, #6
|
|
8001880: 781b ldrb r3, [r3, #0]
|
|
8001882: f8d7 2114 ldr.w r2, [r7, #276] ; 0x114
|
|
8001886: 429a cmp r2, r3
|
|
8001888: dbdc blt.n 8001844 <LoRa_send+0xa8>
|
|
}
|
|
strcat((char*)&sendMsg[len+2*size],"\r\n");
|
|
800188a: f897 2112 ldrb.w r2, [r7, #274] ; 0x112
|
|
800188e: 1dbb adds r3, r7, #6
|
|
8001890: 781b ldrb r3, [r3, #0]
|
|
8001892: 005b lsls r3, r3, #1
|
|
8001894: 441a add r2, r3
|
|
8001896: f240 03bc movw r3, #188 ; 0xbc
|
|
800189a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800189e: 18d4 adds r4, r2, r3
|
|
80018a0: 4620 mov r0, r4
|
|
80018a2: f7fe fc95 bl 80001d0 <strlen>
|
|
80018a6: 4603 mov r3, r0
|
|
80018a8: 18e2 adds r2, r4, r3
|
|
80018aa: f24e 236c movw r3, #57964 ; 0xe26c
|
|
80018ae: f6c0 0300 movt r3, #2048 ; 0x800
|
|
80018b2: 8819 ldrh r1, [r3, #0]
|
|
80018b4: 789b ldrb r3, [r3, #2]
|
|
80018b6: 8011 strh r1, [r2, #0]
|
|
80018b8: 7093 strb r3, [r2, #2]
|
|
|
|
//uint8_t exemple[]="AT+CMSGHEX=12345678\r\n";
|
|
printf("%s",sendMsg);
|
|
80018ba: f240 01bc movw r1, #188 ; 0xbc
|
|
80018be: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
80018c2: f24e 2018 movw r0, #57880 ; 0xe218
|
|
80018c6: f6c0 0000 movt r0, #2048 ; 0x800
|
|
80018ca: f009 ffc7 bl 800b85c <iprintf>
|
|
rslt+=at_send(&huart2,(uint8_t*)"AT+LW=DTR\r\n",1000,strlen((char*)"AT+LW=DTR\r\n"));
|
|
80018ce: 230b movs r3, #11
|
|
80018d0: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
80018d4: f24e 2170 movw r1, #57968 ; 0xe270
|
|
80018d8: f6c0 0100 movt r1, #2048 ; 0x800
|
|
80018dc: f640 109c movw r0, #2460 ; 0x99c
|
|
80018e0: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80018e4: f001 fc86 bl 80031f4 <at_send>
|
|
80018e8: 4603 mov r3, r0
|
|
80018ea: 461a mov r2, r3
|
|
80018ec: f897 3113 ldrb.w r3, [r7, #275] ; 0x113
|
|
80018f0: 4413 add r3, r2
|
|
80018f2: f887 3113 strb.w r3, [r7, #275] ; 0x113
|
|
rslt+=at_Com(&huart2,sendMsg,rcv,12000,len+2*size+2);
|
|
80018f6: 1dbb adds r3, r7, #6
|
|
80018f8: 781b ldrb r3, [r3, #0]
|
|
80018fa: 005b lsls r3, r3, #1
|
|
80018fc: b2da uxtb r2, r3
|
|
80018fe: f897 3112 ldrb.w r3, [r7, #274] ; 0x112
|
|
8001902: 4413 add r3, r2
|
|
8001904: b2db uxtb r3, r3
|
|
8001906: 3302 adds r3, #2
|
|
8001908: b2db uxtb r3, r3
|
|
800190a: f107 020c add.w r2, r7, #12
|
|
800190e: 9300 str r3, [sp, #0]
|
|
8001910: f642 63e0 movw r3, #12000 ; 0x2ee0
|
|
8001914: f240 01bc movw r1, #188 ; 0xbc
|
|
8001918: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
800191c: f640 109c movw r0, #2460 ; 0x99c
|
|
8001920: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001924: f001 fbe1 bl 80030ea <at_Com>
|
|
8001928: 4603 mov r3, r0
|
|
800192a: 461a mov r2, r3
|
|
800192c: f897 3113 ldrb.w r3, [r7, #275] ; 0x113
|
|
8001930: 4413 add r3, r2
|
|
8001932: f887 3113 strb.w r3, [r7, #275] ; 0x113
|
|
char* ack=strstr((char*)rcv,(char*)ackrcv);
|
|
8001936: f107 030c add.w r3, r7, #12
|
|
800193a: f240 11bc movw r1, #444 ; 0x1bc
|
|
800193e: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001942: 4618 mov r0, r3
|
|
8001944: f00a f838 bl 800b9b8 <strstr>
|
|
8001948: f8c7 010c str.w r0, [r7, #268] ; 0x10c
|
|
if(ack!=NULL)
|
|
800194c: f8d7 310c ldr.w r3, [r7, #268] ; 0x10c
|
|
8001950: 2b00 cmp r3, #0
|
|
8001952: d006 beq.n 8001962 <LoRa_send+0x1c6>
|
|
{
|
|
AppData.is_send=1;
|
|
8001954: f240 2310 movw r3, #528 ; 0x210
|
|
8001958: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800195c: 2201 movs r2, #1
|
|
800195e: 721a strb r2, [r3, #8]
|
|
8001960: e011 b.n 8001986 <LoRa_send+0x1ea>
|
|
}
|
|
else if(strstr((char*)rcv,(char*)notjoined)!=NULL)
|
|
8001962: f107 030c add.w r3, r7, #12
|
|
8001966: f240 11d0 movw r1, #464 ; 0x1d0
|
|
800196a: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
800196e: 4618 mov r0, r3
|
|
8001970: f00a f822 bl 800b9b8 <strstr>
|
|
8001974: 4603 mov r3, r0
|
|
8001976: 2b00 cmp r3, #0
|
|
8001978: d005 beq.n 8001986 <LoRa_send+0x1ea>
|
|
{
|
|
AppData.is_join=0;
|
|
800197a: f240 2310 movw r3, #528 ; 0x210
|
|
800197e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001982: 2200 movs r2, #0
|
|
8001984: 725a strb r2, [r3, #9]
|
|
|
|
}
|
|
memset((char*)&sendMsg[len],0,2*size+2);
|
|
8001986: f897 2112 ldrb.w r2, [r7, #274] ; 0x112
|
|
800198a: f240 03bc movw r3, #188 ; 0xbc
|
|
800198e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001992: 18d0 adds r0, r2, r3
|
|
8001994: 1dbb adds r3, r7, #6
|
|
8001996: 781b ldrb r3, [r3, #0]
|
|
8001998: 3301 adds r3, #1
|
|
800199a: 005b lsls r3, r3, #1
|
|
800199c: 461a mov r2, r3
|
|
800199e: 2100 movs r1, #0
|
|
80019a0: f009 faea bl 800af78 <memset>
|
|
return rslt;
|
|
80019a4: f897 3113 ldrb.w r3, [r7, #275] ; 0x113
|
|
}
|
|
80019a8: 4618 mov r0, r3
|
|
80019aa: f507 778e add.w r7, r7, #284 ; 0x11c
|
|
80019ae: 46bd mov sp, r7
|
|
80019b0: bd90 pop {r4, r7, pc}
|
|
|
|
080019b2 <LoRa_process>:
|
|
|
|
HAL_StatusTypeDef LoRa_process()
|
|
{
|
|
80019b2: b580 push {r7, lr}
|
|
80019b4: b08a sub sp, #40 ; 0x28
|
|
80019b6: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef rslt=HAL_OK;
|
|
80019b8: 2300 movs r3, #0
|
|
80019ba: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
AppData.is_send=0;
|
|
80019be: f240 2310 movw r3, #528 ; 0x210
|
|
80019c2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80019c6: 2200 movs r2, #0
|
|
80019c8: 721a strb r2, [r3, #8]
|
|
int8_t try=2;
|
|
80019ca: 2302 movs r3, #2
|
|
80019cc: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
uint8_t wkup[32]={0xff,0xff,0xff,0xff};
|
|
80019d0: f24e 2244 movw r2, #57924 ; 0xe244
|
|
80019d4: f6c0 0200 movt r2, #2048 ; 0x800
|
|
80019d8: 1d3b adds r3, r7, #4
|
|
80019da: e892 0003 ldmia.w r2, {r0, r1}
|
|
80019de: 6018 str r0, [r3, #0]
|
|
80019e0: 3304 adds r3, #4
|
|
80019e2: 7019 strb r1, [r3, #0]
|
|
80019e4: f107 0309 add.w r3, r7, #9
|
|
80019e8: 2200 movs r2, #0
|
|
80019ea: 601a str r2, [r3, #0]
|
|
80019ec: 605a str r2, [r3, #4]
|
|
80019ee: 609a str r2, [r3, #8]
|
|
80019f0: 60da str r2, [r3, #12]
|
|
80019f2: 611a str r2, [r3, #16]
|
|
80019f4: 615a str r2, [r3, #20]
|
|
80019f6: f8c3 2017 str.w r2, [r3, #23]
|
|
sprintf((char*)&wkup+4,"%s",lowpoweroff);
|
|
80019fa: 1d3b adds r3, r7, #4
|
|
80019fc: 3304 adds r3, #4
|
|
80019fe: f240 2234 movw r2, #564 ; 0x234
|
|
8001a02: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
8001a06: f24e 2118 movw r1, #57880 ; 0xe218
|
|
8001a0a: f6c0 0100 movt r1, #2048 ; 0x800
|
|
8001a0e: 4618 mov r0, r3
|
|
8001a10: f009 ffb2 bl 800b978 <siprintf>
|
|
|
|
at_send(&huart2,wkup,1000,strlen((char*)wkup));
|
|
8001a14: 1d3b adds r3, r7, #4
|
|
8001a16: 4618 mov r0, r3
|
|
8001a18: f7fe fbda bl 80001d0 <strlen>
|
|
8001a1c: 4603 mov r3, r0
|
|
8001a1e: b2db uxtb r3, r3
|
|
8001a20: 1d39 adds r1, r7, #4
|
|
8001a22: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
8001a26: f640 109c movw r0, #2460 ; 0x99c
|
|
8001a2a: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001a2e: f001 fbe1 bl 80031f4 <at_send>
|
|
|
|
do
|
|
{
|
|
if(AppData.is_join)
|
|
8001a32: f240 2310 movw r3, #528 ; 0x210
|
|
8001a36: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001a3a: 7a5b ldrb r3, [r3, #9]
|
|
8001a3c: 2b00 cmp r3, #0
|
|
8001a3e: d049 beq.n 8001ad4 <LoRa_process+0x122>
|
|
{
|
|
queue.cursor--;
|
|
8001a40: f240 6390 movw r3, #1680 ; 0x690
|
|
8001a44: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001a48: 791b ldrb r3, [r3, #4]
|
|
8001a4a: 3b01 subs r3, #1
|
|
8001a4c: b2da uxtb r2, r3
|
|
8001a4e: f240 6390 movw r3, #1680 ; 0x690
|
|
8001a52: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001a56: 711a strb r2, [r3, #4]
|
|
buffer_get(&queue, AppData.Buffer,sizeof(uint64_t));
|
|
8001a58: f240 2310 movw r3, #528 ; 0x210
|
|
8001a5c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001a60: 685b ldr r3, [r3, #4]
|
|
8001a62: 2208 movs r2, #8
|
|
8001a64: 4619 mov r1, r3
|
|
8001a66: f240 6090 movw r0, #1680 ; 0x690
|
|
8001a6a: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001a6e: f000 fe05 bl 800267c <buffer_get>
|
|
rslt=LoRa_send(AppData.Port,AppData.Buffer,AppData.BufferSize);
|
|
8001a72: f240 2310 movw r3, #528 ; 0x210
|
|
8001a76: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001a7a: 7818 ldrb r0, [r3, #0]
|
|
8001a7c: f240 2310 movw r3, #528 ; 0x210
|
|
8001a80: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001a84: 6859 ldr r1, [r3, #4]
|
|
8001a86: f240 2310 movw r3, #528 ; 0x210
|
|
8001a8a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001a8e: 785b ldrb r3, [r3, #1]
|
|
8001a90: 461a mov r2, r3
|
|
8001a92: f7ff fe83 bl 800179c <LoRa_send>
|
|
8001a96: 4603 mov r3, r0
|
|
8001a98: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
if(AppData.is_send)
|
|
8001a9c: f240 2310 movw r3, #528 ; 0x210
|
|
8001aa0: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001aa4: 7a1b ldrb r3, [r3, #8]
|
|
8001aa6: 2b00 cmp r3, #0
|
|
8001aa8: d006 beq.n 8001ab8 <LoRa_process+0x106>
|
|
{
|
|
buffer_flush(&queue);
|
|
8001aaa: f240 6090 movw r0, #1680 ; 0x690
|
|
8001aae: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001ab2: f000 fdfe bl 80026b2 <buffer_flush>
|
|
break;
|
|
8001ab6: e02b b.n 8001b10 <LoRa_process+0x15e>
|
|
}
|
|
else
|
|
try--;
|
|
8001ab8: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
8001abc: b2db uxtb r3, r3
|
|
8001abe: 3b01 subs r3, #1
|
|
8001ac0: b2db uxtb r3, r3
|
|
8001ac2: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
__movecursor(&queue);
|
|
8001ac6: f240 6090 movw r0, #1680 ; 0x690
|
|
8001aca: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001ace: f000 fdba bl 8002646 <__movecursor>
|
|
8001ad2: e012 b.n 8001afa <LoRa_process+0x148>
|
|
|
|
}
|
|
else
|
|
{
|
|
if(LoRa_join())
|
|
8001ad4: f7ff fe17 bl 8001706 <LoRa_join>
|
|
8001ad8: 4603 mov r3, r0
|
|
8001ada: 2b00 cmp r3, #0
|
|
8001adc: d007 beq.n 8001aee <LoRa_process+0x13c>
|
|
{
|
|
try--;
|
|
8001ade: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
8001ae2: b2db uxtb r3, r3
|
|
8001ae4: 3b01 subs r3, #1
|
|
8001ae6: b2db uxtb r3, r3
|
|
8001ae8: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
8001aec: e005 b.n 8001afa <LoRa_process+0x148>
|
|
}
|
|
else
|
|
{
|
|
AppData.is_join=1;
|
|
8001aee: f240 2310 movw r3, #528 ; 0x210
|
|
8001af2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001af6: 2201 movs r2, #1
|
|
8001af8: 725a strb r2, [r3, #9]
|
|
}
|
|
}
|
|
|
|
}while(queue.cursor!=0 && try>=0);
|
|
8001afa: f240 6390 movw r3, #1680 ; 0x690
|
|
8001afe: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001b02: 791b ldrb r3, [r3, #4]
|
|
8001b04: 2b00 cmp r3, #0
|
|
8001b06: d003 beq.n 8001b10 <LoRa_process+0x15e>
|
|
8001b08: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
8001b0c: 2b00 cmp r3, #0
|
|
8001b0e: da90 bge.n 8001a32 <LoRa_process+0x80>
|
|
rslt=at_send(&huart2, lowpoweron, 1000, strlen((char*)lowpoweron));
|
|
8001b10: f240 201c movw r0, #540 ; 0x21c
|
|
8001b14: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001b18: f7fe fb5a bl 80001d0 <strlen>
|
|
8001b1c: 4603 mov r3, r0
|
|
8001b1e: b2db uxtb r3, r3
|
|
8001b20: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
8001b24: f240 211c movw r1, #540 ; 0x21c
|
|
8001b28: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001b2c: f640 109c movw r0, #2460 ; 0x99c
|
|
8001b30: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001b34: f001 fb5e bl 80031f4 <at_send>
|
|
8001b38: 4603 mov r3, r0
|
|
8001b3a: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
|
|
return rslt;
|
|
8001b3e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
|
|
}
|
|
8001b42: 4618 mov r0, r3
|
|
8001b44: 3728 adds r7, #40 ; 0x28
|
|
8001b46: 46bd mov sp, r7
|
|
8001b48: bd80 pop {r7, pc}
|
|
|
|
08001b4a <CayenneMakeBuffer>:
|
|
|
|
|
|
|
|
void CayenneMakeBuffer(void)
|
|
{
|
|
8001b4a: b5b0 push {r4, r5, r7, lr}
|
|
8001b4c: b098 sub sp, #96 ; 0x60
|
|
8001b4e: af02 add r7, sp, #8
|
|
/* USER CODE BEGIN SendTxData_1 */
|
|
uint16_t pressure = 0;
|
|
8001b50: 2300 movs r3, #0
|
|
8001b52: f8a7 3056 strh.w r3, [r7, #86] ; 0x56
|
|
int16_t temperature_bme = 0;
|
|
8001b56: 2300 movs r3, #0
|
|
8001b58: f8a7 3054 strh.w r3, [r7, #84] ; 0x54
|
|
int16_t temperature_ntc =0;
|
|
8001b5c: 2300 movs r3, #0
|
|
8001b5e: f8a7 3052 strh.w r3, [r7, #82] ; 0x52
|
|
sensor_t sensor_data={0};
|
|
8001b62: 463b mov r3, r7
|
|
8001b64: 224c movs r2, #76 ; 0x4c
|
|
8001b66: 2100 movs r1, #0
|
|
8001b68: 4618 mov r0, r3
|
|
8001b6a: f009 fa05 bl 800af78 <memset>
|
|
uint16_t weight=0;
|
|
8001b6e: 2300 movs r3, #0
|
|
8001b70: f8a7 3050 strh.w r3, [r7, #80] ; 0x50
|
|
//UTIL_TIMER_Time_t nextTxIn = 0;
|
|
|
|
#ifdef CAYENNE_LPP
|
|
uint8_t channel = 0;
|
|
8001b74: 2300 movs r3, #0
|
|
8001b76: f887 304f strb.w r3, [r7, #79] ; 0x4f
|
|
uint16_t altitudeGps = 0;
|
|
#endif /* CAYENNE_LPP */
|
|
|
|
// EnvSensors_Read(&sensor_data);
|
|
|
|
Bme680Sensors_Init();
|
|
8001b7a: f001 f88d bl 8002c98 <Bme680Sensors_Init>
|
|
//ADS1232Sensors_Init(&sensor_data);
|
|
Bme680Sensors_Read(&sensor_data);
|
|
8001b7e: 463b mov r3, r7
|
|
8001b80: 4618 mov r0, r3
|
|
8001b82: f001 f879 bl 8002c78 <Bme680Sensors_Read>
|
|
NTCRead(&hadc1,&sensor_data);
|
|
8001b86: 463b mov r3, r7
|
|
8001b88: 4619 mov r1, r3
|
|
8001b8a: f640 1014 movw r0, #2324 ; 0x914
|
|
8001b8e: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001b92: f001 f891 bl 8002cb8 <NTCRead>
|
|
printf("NTC_TEMP=%f °C NTC_HUM=%f%\r\n",sensor_data.ntc_temp,sensor_data.ntc_humidity);
|
|
8001b96: 69fb ldr r3, [r7, #28]
|
|
8001b98: 4618 mov r0, r3
|
|
8001b9a: f7fe fcd5 bl 8000548 <__aeabi_f2d>
|
|
8001b9e: 4604 mov r4, r0
|
|
8001ba0: 460d mov r5, r1
|
|
8001ba2: 6a3b ldr r3, [r7, #32]
|
|
8001ba4: 4618 mov r0, r3
|
|
8001ba6: f7fe fccf bl 8000548 <__aeabi_f2d>
|
|
8001baa: 4602 mov r2, r0
|
|
8001bac: 460b mov r3, r1
|
|
8001bae: e9cd 2300 strd r2, r3, [sp]
|
|
8001bb2: 4622 mov r2, r4
|
|
8001bb4: 462b mov r3, r5
|
|
8001bb6: f24e 207c movw r0, #57980 ; 0xe27c
|
|
8001bba: f6c0 0000 movt r0, #2048 ; 0x800
|
|
8001bbe: f009 fe4d bl 800b85c <iprintf>
|
|
// ADS1232Read(&huart5,&sensor_data);
|
|
|
|
sensor_data.scale.weight = (sensor_data.scale.m*sensor_data.scale.c + sensor_data.scale.wzs -sensor_data.scale.wt)*100;
|
|
8001bc2: ed97 7a0c vldr s14, [r7, #48] ; 0x30
|
|
8001bc6: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8001bc8: ee07 3a90 vmov s15, r3
|
|
8001bcc: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001bd0: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001bd4: edd7 7a0e vldr s15, [r7, #56] ; 0x38
|
|
8001bd8: ee37 7a27 vadd.f32 s14, s14, s15
|
|
8001bdc: f897 302c ldrb.w r3, [r7, #44] ; 0x2c
|
|
8001be0: ee07 3a90 vmov s15, r3
|
|
8001be4: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001be8: ee77 7a67 vsub.f32 s15, s14, s15
|
|
8001bec: 2300 movs r3, #0
|
|
8001bee: f2c4 23c8 movt r3, #17096 ; 0x42c8
|
|
8001bf2: ee07 3a10 vmov s14, r3
|
|
8001bf6: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001bfa: edc7 7a0a vstr s15, [r7, #40] ; 0x28
|
|
printf("adc code = %x weight= %f\r\n",sensor_data.scale.c,sensor_data.scale.weight);
|
|
8001bfe: 6bfc ldr r4, [r7, #60] ; 0x3c
|
|
8001c00: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8001c02: 4618 mov r0, r3
|
|
8001c04: f7fe fca0 bl 8000548 <__aeabi_f2d>
|
|
8001c08: 4602 mov r2, r0
|
|
8001c0a: 460b mov r3, r1
|
|
8001c0c: 4621 mov r1, r4
|
|
8001c0e: f24e 209c movw r0, #58012 ; 0xe29c
|
|
8001c12: f6c0 0000 movt r0, #2048 ; 0x800
|
|
8001c16: f009 fe21 bl 800b85c <iprintf>
|
|
//sprintf(&weight,"%06.3f",sensor_data.scale.weight);
|
|
temperature_bme = (uint16_t)(sensor_data.temperature);
|
|
8001c1a: edd7 7a01 vldr s15, [r7, #4]
|
|
8001c1e: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001c22: ee17 3a90 vmov r3, s15
|
|
8001c26: b29b uxth r3, r3
|
|
8001c28: f8a7 3054 strh.w r3, [r7, #84] ; 0x54
|
|
temperature_ntc = (uint16_t)(sensor_data.ntc_temp*100);
|
|
8001c2c: edd7 7a07 vldr s15, [r7, #28]
|
|
8001c30: 2300 movs r3, #0
|
|
8001c32: f2c4 23c8 movt r3, #17096 ; 0x42c8
|
|
8001c36: ee07 3a10 vmov s14, r3
|
|
8001c3a: ee67 7a87 vmul.f32 s15, s15, s14
|
|
8001c3e: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001c42: ee17 3a90 vmov r3, s15
|
|
8001c46: b29b uxth r3, r3
|
|
8001c48: f8a7 3052 strh.w r3, [r7, #82] ; 0x52
|
|
pressure = (sensor_data.pressure / 100); /* in hPa / 10 */
|
|
8001c4c: ed97 7a00 vldr s14, [r7]
|
|
8001c50: 2300 movs r3, #0
|
|
8001c52: f2c4 23c8 movt r3, #17096 ; 0x42c8
|
|
8001c56: ee06 3a90 vmov s13, r3
|
|
8001c5a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8001c5e: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001c62: ee17 3a90 vmov r3, s15
|
|
8001c66: f8a7 3056 strh.w r3, [r7, #86] ; 0x56
|
|
// weight = (int)(sensor_data.scale.weight < 0 ? (sensor_data.scale.weight - 0.5) : (sensor_data.scale.weight + 0.5));
|
|
weight =sensor_data.scale.weight;
|
|
8001c6a: edd7 7a0a vldr s15, [r7, #40] ; 0x28
|
|
8001c6e: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001c72: ee17 3a90 vmov r3, s15
|
|
8001c76: f8a7 3050 strh.w r3, [r7, #80] ; 0x50
|
|
AppData.Port = LORAWAN_USER_APP_PORT;
|
|
8001c7a: f240 2310 movw r3, #528 ; 0x210
|
|
8001c7e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001c82: 2202 movs r2, #2
|
|
8001c84: 701a strb r2, [r3, #0]
|
|
#ifdef CAYENNE_LPP
|
|
CayenneLppReset();
|
|
8001c86: f7ff f9ab bl 8000fe0 <CayenneLppReset>
|
|
CayenneLppAddBarometricPressure(channel++, (uint16_t)(sensor_data.pressure/100));
|
|
8001c8a: f897 204f ldrb.w r2, [r7, #79] ; 0x4f
|
|
8001c8e: 1c53 adds r3, r2, #1
|
|
8001c90: f887 304f strb.w r3, [r7, #79] ; 0x4f
|
|
8001c94: ed97 7a00 vldr s14, [r7]
|
|
8001c98: 2300 movs r3, #0
|
|
8001c9a: f2c4 23c8 movt r3, #17096 ; 0x42c8
|
|
8001c9e: ee06 3a90 vmov s13, r3
|
|
8001ca2: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8001ca6: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001caa: ee17 3a90 vmov r3, s15
|
|
8001cae: b29b uxth r3, r3
|
|
8001cb0: 4619 mov r1, r3
|
|
8001cb2: 4610 mov r0, r2
|
|
8001cb4: f7ff fa8f bl 80011d6 <CayenneLppAddBarometricPressure>
|
|
CayenneLppAddTemperature(channel++, (uint16_t)temperature_bme);
|
|
8001cb8: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
|
|
8001cbc: 1c5a adds r2, r3, #1
|
|
8001cbe: f887 204f strb.w r2, [r7, #79] ; 0x4f
|
|
8001cc2: f9b7 2054 ldrsh.w r2, [r7, #84] ; 0x54
|
|
8001cc6: 4611 mov r1, r2
|
|
8001cc8: 4618 mov r0, r3
|
|
8001cca: f7ff f9bd bl 8001048 <CayenneLppAddTemperature>
|
|
CayenneLppAddTemperature(channel++, (uint16_t)temperature_ntc);
|
|
8001cce: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
|
|
8001cd2: 1c5a adds r2, r3, #1
|
|
8001cd4: f887 204f strb.w r2, [r7, #79] ; 0x4f
|
|
8001cd8: f9b7 2052 ldrsh.w r2, [r7, #82] ; 0x52
|
|
8001cdc: 4611 mov r1, r2
|
|
8001cde: 4618 mov r0, r3
|
|
8001ce0: f7ff f9b2 bl 8001048 <CayenneLppAddTemperature>
|
|
//CayenneLppAddAnalogInput(channel++, (uint16_t) weight);
|
|
//CayenneLppAddAnalogInput(channel++,sensor_data.raw_weight);
|
|
CayenneLppAddRelativeHumidity(channel++, (uint16_t)(sensor_data.humidity/1000));
|
|
8001ce4: f897 204f ldrb.w r2, [r7, #79] ; 0x4f
|
|
8001ce8: 1c53 adds r3, r2, #1
|
|
8001cea: f887 304f strb.w r3, [r7, #79] ; 0x4f
|
|
8001cee: ed97 7a02 vldr s14, [r7, #8]
|
|
8001cf2: 2300 movs r3, #0
|
|
8001cf4: f2c4 437a movt r3, #17530 ; 0x447a
|
|
8001cf8: ee06 3a90 vmov s13, r3
|
|
8001cfc: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8001d00: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001d04: ee17 3a90 vmov r3, s15
|
|
8001d08: b29b uxth r3, r3
|
|
8001d0a: 4619 mov r1, r3
|
|
8001d0c: 4610 mov r0, r2
|
|
8001d0e: f7ff fa0c bl 800112a <CayenneLppAddRelativeHumidity>
|
|
CayenneLppAddRelativeHumidity(channel++, (uint16_t)(sensor_data.ntc_humidity));
|
|
8001d12: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
|
|
8001d16: 1c5a adds r2, r3, #1
|
|
8001d18: f887 204f strb.w r2, [r7, #79] ; 0x4f
|
|
8001d1c: edd7 7a08 vldr s15, [r7, #32]
|
|
8001d20: eefc 7ae7 vcvt.u32.f32 s15, s15
|
|
8001d24: ee17 2a90 vmov r2, s15
|
|
8001d28: b292 uxth r2, r2
|
|
8001d2a: 4611 mov r1, r2
|
|
8001d2c: 4618 mov r0, r3
|
|
8001d2e: f7ff f9fc bl 800112a <CayenneLppAddRelativeHumidity>
|
|
|
|
|
|
|
|
|
|
CayenneLppCopy(AppData.Buffer);
|
|
8001d32: f240 2310 movw r3, #528 ; 0x210
|
|
8001d36: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001d3a: 685b ldr r3, [r3, #4]
|
|
8001d3c: 4618 mov r0, r3
|
|
8001d3e: f7ff f968 bl 8001012 <CayenneLppCopy>
|
|
AppData.BufferSize = CayenneLppGetSize();
|
|
8001d42: f7ff f95a bl 8000ffa <CayenneLppGetSize>
|
|
8001d46: 4603 mov r3, r0
|
|
8001d48: 461a mov r2, r3
|
|
8001d4a: f240 2310 movw r3, #528 ; 0x210
|
|
8001d4e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001d52: 705a strb r2, [r3, #1]
|
|
|
|
buffer_flush(&queue);
|
|
8001d54: f240 6090 movw r0, #1680 ; 0x690
|
|
8001d58: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001d5c: f000 fca9 bl 80026b2 <buffer_flush>
|
|
buffer_put(&queue, AppData.Buffer);
|
|
8001d60: f240 2310 movw r3, #528 ; 0x210
|
|
8001d64: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001d68: 685b ldr r3, [r3, #4]
|
|
8001d6a: 4619 mov r1, r3
|
|
8001d6c: f240 6090 movw r0, #1680 ; 0x690
|
|
8001d70: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001d74: f000 fc4e bl 8002614 <buffer_put>
|
|
__movecursor(&queue);
|
|
8001d78: f240 6090 movw r0, #1680 ; 0x690
|
|
8001d7c: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001d80: f000 fc61 bl 8002646 <__movecursor>
|
|
#endif /* CAYENNE_LPP */
|
|
|
|
|
|
/* USER CODE END SendTxData_1 */
|
|
}
|
|
8001d84: bf00 nop
|
|
8001d86: 3758 adds r7, #88 ; 0x58
|
|
8001d88: 46bd mov sp, r7
|
|
8001d8a: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
08001d8c <ITM_SendChar>:
|
|
\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
|
|
\param [in] ch Character to transmit.
|
|
\returns Character to transmit.
|
|
*/
|
|
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
|
|
{
|
|
8001d8c: b480 push {r7}
|
|
8001d8e: b083 sub sp, #12
|
|
8001d90: af00 add r7, sp, #0
|
|
8001d92: 6078 str r0, [r7, #4]
|
|
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
|
8001d94: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000
|
|
8001d98: f8d3 3e80 ldr.w r3, [r3, #3712] ; 0xe80
|
|
8001d9c: f003 0301 and.w r3, r3, #1
|
|
8001da0: 2b00 cmp r3, #0
|
|
8001da2: d013 beq.n 8001dcc <ITM_SendChar+0x40>
|
|
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
|
|
8001da4: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000
|
|
8001da8: f8d3 3e00 ldr.w r3, [r3, #3584] ; 0xe00
|
|
8001dac: f003 0301 and.w r3, r3, #1
|
|
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
|
|
8001db0: 2b00 cmp r3, #0
|
|
8001db2: d00b beq.n 8001dcc <ITM_SendChar+0x40>
|
|
{
|
|
while (ITM->PORT[0U].u32 == 0UL)
|
|
8001db4: e000 b.n 8001db8 <ITM_SendChar+0x2c>
|
|
{
|
|
__NOP();
|
|
8001db6: bf00 nop
|
|
while (ITM->PORT[0U].u32 == 0UL)
|
|
8001db8: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000
|
|
8001dbc: 681b ldr r3, [r3, #0]
|
|
8001dbe: 2b00 cmp r3, #0
|
|
8001dc0: d0f9 beq.n 8001db6 <ITM_SendChar+0x2a>
|
|
}
|
|
ITM->PORT[0U].u8 = (uint8_t)ch;
|
|
8001dc2: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000
|
|
8001dc6: 687a ldr r2, [r7, #4]
|
|
8001dc8: b2d2 uxtb r2, r2
|
|
8001dca: 701a strb r2, [r3, #0]
|
|
}
|
|
return (ch);
|
|
8001dcc: 687b ldr r3, [r7, #4]
|
|
}
|
|
8001dce: 4618 mov r0, r3
|
|
8001dd0: 370c adds r7, #12
|
|
8001dd2: 46bd mov sp, r7
|
|
8001dd4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001dd8: 4770 bx lr
|
|
|
|
08001dda <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8001dda: b580 push {r7, lr}
|
|
8001ddc: b082 sub sp, #8
|
|
8001dde: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8001de0: f002 fda2 bl 8004928 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8001de4: f000 f867 bl 8001eb6 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8001de8: f000 faef bl 80023ca <MX_GPIO_Init>
|
|
MX_USART2_UART_Init();
|
|
8001dec: f000 fa9e bl 800232c <MX_USART2_UART_Init>
|
|
MX_ADC1_Init();
|
|
8001df0: f000 f8c7 bl 8001f82 <MX_ADC1_Init>
|
|
MX_I2C1_Init();
|
|
8001df4: f000 f982 bl 80020fc <MX_I2C1_Init>
|
|
MX_RTC_Init();
|
|
8001df8: f000 f9e3 bl 80021c2 <MX_RTC_Init>
|
|
MX_UART5_Init();
|
|
8001dfc: f000 fa47 bl 800228e <MX_UART5_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
buffer_init(&queue, adressList,3, BASEADRESSFLASH);
|
|
8001e00: f44f 4368 mov.w r3, #59392 ; 0xe800
|
|
8001e04: f6c0 0303 movt r3, #2051 ; 0x803
|
|
8001e08: 2203 movs r2, #3
|
|
8001e0a: f240 71c4 movw r1, #1988 ; 0x7c4
|
|
8001e0e: f2c2 0100 movt r1, #8192 ; 0x2000
|
|
8001e12: f240 6090 movw r0, #1680 ; 0x690
|
|
8001e16: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001e1a: f000 fbcc bl 80025b6 <buffer_init>
|
|
for(int i=125;i<=127;i++)
|
|
8001e1e: 237d movs r3, #125 ; 0x7d
|
|
8001e20: 607b str r3, [r7, #4]
|
|
8001e22: e007 b.n 8001e34 <main+0x5a>
|
|
memory_erasePage(i);
|
|
8001e24: 687b ldr r3, [r7, #4]
|
|
8001e26: b2db uxtb r3, r3
|
|
8001e28: 4618 mov r0, r3
|
|
8001e2a: f7ff fa43 bl 80012b4 <memory_erasePage>
|
|
for(int i=125;i<=127;i++)
|
|
8001e2e: 687b ldr r3, [r7, #4]
|
|
8001e30: 3301 adds r3, #1
|
|
8001e32: 607b str r3, [r7, #4]
|
|
8001e34: 687b ldr r3, [r7, #4]
|
|
8001e36: 2b7f cmp r3, #127 ; 0x7f
|
|
8001e38: ddf4 ble.n 8001e24 <main+0x4a>
|
|
printf("start\r\n");
|
|
8001e3a: f24e 20b8 movw r0, #58040 ; 0xe2b8
|
|
8001e3e: f6c0 0000 movt r0, #2048 ; 0x800
|
|
8001e42: f009 fd91 bl 800b968 <puts>
|
|
printf("LoRa init\r\n");
|
|
8001e46: f24e 20c0 movw r0, #58048 ; 0xe2c0
|
|
8001e4a: f6c0 0000 movt r0, #2048 ; 0x800
|
|
8001e4e: f009 fd8b bl 800b968 <puts>
|
|
LoRa_init();
|
|
8001e52: f7ff fb29 bl 80014a8 <LoRa_init>
|
|
|
|
//ADS1232Power(&huart5,SET);
|
|
|
|
|
|
// creation du payload
|
|
printf("measurement\r\n");
|
|
8001e56: f24e 20cc movw r0, #58060 ; 0xe2cc
|
|
8001e5a: f6c0 0000 movt r0, #2048 ; 0x800
|
|
8001e5e: f009 fd83 bl 800b968 <puts>
|
|
CayenneMakeBuffer();
|
|
8001e62: f7ff fe72 bl 8001b4a <CayenneMakeBuffer>
|
|
// enregistrement du payload
|
|
|
|
// ADS1232Power(&huart5,RESET );
|
|
|
|
// envoi du payload
|
|
printf("LoRa processing\r\n");
|
|
8001e66: f24e 20dc movw r0, #58076 ; 0xe2dc
|
|
8001e6a: f6c0 0000 movt r0, #2048 ; 0x800
|
|
8001e6e: f009 fd7b bl 800b968 <puts>
|
|
if(!LoRa_process())
|
|
8001e72: f7ff fd9e bl 80019b2 <LoRa_process>
|
|
printf("invalid date : configuration aborted \r\n");
|
|
}*/
|
|
|
|
|
|
}
|
|
printf("et maintenant au dodo \r\n");
|
|
8001e76: f24e 20f0 movw r0, #58096 ; 0xe2f0
|
|
8001e7a: f6c0 0000 movt r0, #2048 ; 0x800
|
|
8001e7e: f009 fd73 bl 800b968 <puts>
|
|
//HAL_ADCEx_EnterADCDeepPowerDownMode(&hadc1);
|
|
// stopWithAlarm(&hrtc,&sAlarm);
|
|
|
|
|
|
HAL_SuspendTick();
|
|
8001e82: f002 fdf2 bl 8004a6a <HAL_SuspendTick>
|
|
HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON,PWR_SLEEPENTRY_WFI);
|
|
8001e86: 2101 movs r1, #1
|
|
8001e88: 2000 movs r0, #0
|
|
8001e8a: f005 fef7 bl 8007c7c <HAL_PWR_EnterSTOPMode>
|
|
HAL_ResumeTick();
|
|
8001e8e: f002 fdff bl 8004a90 <HAL_ResumeTick>
|
|
SystemClock_Config();
|
|
8001e92: f000 f810 bl 8001eb6 <SystemClock_Config>
|
|
|
|
hadc1.State = HAL_ADC_STATE_RESET;
|
|
8001e96: f640 1314 movw r3, #2324 ; 0x914
|
|
8001e9a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001e9e: 2200 movs r2, #0
|
|
8001ea0: 655a str r2, [r3, #84] ; 0x54
|
|
MX_ADC1_Init();
|
|
8001ea2: f000 f86e bl 8001f82 <MX_ADC1_Init>
|
|
HAL_ADCEx_Calibration_Start(&hadc1,ADC_SINGLE_ENDED);
|
|
8001ea6: 217f movs r1, #127 ; 0x7f
|
|
8001ea8: f640 1014 movw r0, #2324 ; 0x914
|
|
8001eac: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8001eb0: f004 f94b bl 800614a <HAL_ADCEx_Calibration_Start>
|
|
printf("measurement\r\n");
|
|
8001eb4: e7cf b.n 8001e56 <main+0x7c>
|
|
|
|
08001eb6 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8001eb6: b580 push {r7, lr}
|
|
8001eb8: b096 sub sp, #88 ; 0x58
|
|
8001eba: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8001ebc: f107 0314 add.w r3, r7, #20
|
|
8001ec0: 2244 movs r2, #68 ; 0x44
|
|
8001ec2: 2100 movs r1, #0
|
|
8001ec4: 4618 mov r0, r3
|
|
8001ec6: f009 f857 bl 800af78 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8001eca: 463b mov r3, r7
|
|
8001ecc: 2200 movs r2, #0
|
|
8001ece: 601a str r2, [r3, #0]
|
|
8001ed0: 605a str r2, [r3, #4]
|
|
8001ed2: 609a str r2, [r3, #8]
|
|
8001ed4: 60da str r2, [r3, #12]
|
|
8001ed6: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
|
8001ed8: f44f 7000 mov.w r0, #512 ; 0x200
|
|
8001edc: f005 fef3 bl 8007cc6 <HAL_PWREx_ControlVoltageScaling>
|
|
8001ee0: 4603 mov r3, r0
|
|
8001ee2: 2b00 cmp r3, #0
|
|
8001ee4: d001 beq.n 8001eea <SystemClock_Config+0x34>
|
|
{
|
|
Error_Handler();
|
|
8001ee6: f000 fb61 bl 80025ac <Error_Handler>
|
|
}
|
|
/** Configure LSE Drive Capability
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
8001eea: f005 feb4 bl 8007c56 <HAL_PWR_EnableBkUpAccess>
|
|
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
|
|
8001eee: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8001ef2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8001ef6: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8001efa: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8001efe: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8001f02: f022 0218 bic.w r2, r2, #24
|
|
8001f06: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
|
|
8001f0a: 2314 movs r3, #20
|
|
8001f0c: 617b str r3, [r7, #20]
|
|
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
|
8001f0e: 2301 movs r3, #1
|
|
8001f10: 61fb str r3, [r7, #28]
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
8001f12: 2301 movs r3, #1
|
|
8001f14: 62fb str r3, [r7, #44] ; 0x2c
|
|
RCC_OscInitStruct.MSICalibrationValue = 0;
|
|
8001f16: 2300 movs r3, #0
|
|
8001f18: 633b str r3, [r7, #48] ; 0x30
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
|
8001f1a: 2360 movs r3, #96 ; 0x60
|
|
8001f1c: 637b str r3, [r7, #52] ; 0x34
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8001f1e: 2302 movs r3, #2
|
|
8001f20: 63fb str r3, [r7, #60] ; 0x3c
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
|
8001f22: 2301 movs r3, #1
|
|
8001f24: 643b str r3, [r7, #64] ; 0x40
|
|
RCC_OscInitStruct.PLL.PLLM = 1;
|
|
8001f26: 2301 movs r3, #1
|
|
8001f28: 647b str r3, [r7, #68] ; 0x44
|
|
RCC_OscInitStruct.PLL.PLLN = 40;
|
|
8001f2a: 2328 movs r3, #40 ; 0x28
|
|
8001f2c: 64bb str r3, [r7, #72] ; 0x48
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
|
8001f2e: 2307 movs r3, #7
|
|
8001f30: 64fb str r3, [r7, #76] ; 0x4c
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
8001f32: 2302 movs r3, #2
|
|
8001f34: 653b str r3, [r7, #80] ; 0x50
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
8001f36: 2302 movs r3, #2
|
|
8001f38: 657b str r3, [r7, #84] ; 0x54
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8001f3a: f107 0314 add.w r3, r7, #20
|
|
8001f3e: 4618 mov r0, r3
|
|
8001f40: f005 ff9e bl 8007e80 <HAL_RCC_OscConfig>
|
|
8001f44: 4603 mov r3, r0
|
|
8001f46: 2b00 cmp r3, #0
|
|
8001f48: d001 beq.n 8001f4e <SystemClock_Config+0x98>
|
|
{
|
|
Error_Handler();
|
|
8001f4a: f000 fb2f bl 80025ac <Error_Handler>
|
|
}
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8001f4e: 230f movs r3, #15
|
|
8001f50: 603b str r3, [r7, #0]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8001f52: 2303 movs r3, #3
|
|
8001f54: 607b str r3, [r7, #4]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8001f56: 2300 movs r3, #0
|
|
8001f58: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8001f5a: 2300 movs r3, #0
|
|
8001f5c: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8001f5e: 2300 movs r3, #0
|
|
8001f60: 613b str r3, [r7, #16]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
8001f62: 463b mov r3, r7
|
|
8001f64: 2104 movs r1, #4
|
|
8001f66: 4618 mov r0, r3
|
|
8001f68: f006 fcbe bl 80088e8 <HAL_RCC_ClockConfig>
|
|
8001f6c: 4603 mov r3, r0
|
|
8001f6e: 2b00 cmp r3, #0
|
|
8001f70: d001 beq.n 8001f76 <SystemClock_Config+0xc0>
|
|
{
|
|
Error_Handler();
|
|
8001f72: f000 fb1b bl 80025ac <Error_Handler>
|
|
}
|
|
/** Enable MSI Auto calibration
|
|
*/
|
|
HAL_RCCEx_EnableMSIPLLMode();
|
|
8001f76: f007 fae2 bl 800953e <HAL_RCCEx_EnableMSIPLLMode>
|
|
}
|
|
8001f7a: bf00 nop
|
|
8001f7c: 3758 adds r7, #88 ; 0x58
|
|
8001f7e: 46bd mov sp, r7
|
|
8001f80: bd80 pop {r7, pc}
|
|
|
|
08001f82 <MX_ADC1_Init>:
|
|
* @brief ADC1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void MX_ADC1_Init(void)
|
|
{
|
|
8001f82: b580 push {r7, lr}
|
|
8001f84: b08a sub sp, #40 ; 0x28
|
|
8001f86: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC1_Init 0 */
|
|
|
|
/* USER CODE END ADC1_Init 0 */
|
|
|
|
ADC_MultiModeTypeDef multimode = {0};
|
|
8001f88: f107 031c add.w r3, r7, #28
|
|
8001f8c: 2200 movs r2, #0
|
|
8001f8e: 601a str r2, [r3, #0]
|
|
8001f90: 605a str r2, [r3, #4]
|
|
8001f92: 609a str r2, [r3, #8]
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
8001f94: 1d3b adds r3, r7, #4
|
|
8001f96: 2200 movs r2, #0
|
|
8001f98: 601a str r2, [r3, #0]
|
|
8001f9a: 605a str r2, [r3, #4]
|
|
8001f9c: 609a str r2, [r3, #8]
|
|
8001f9e: 60da str r2, [r3, #12]
|
|
8001fa0: 611a str r2, [r3, #16]
|
|
8001fa2: 615a str r2, [r3, #20]
|
|
/* USER CODE BEGIN ADC1_Init 1 */
|
|
|
|
/* USER CODE END ADC1_Init 1 */
|
|
/** Common config
|
|
*/
|
|
hadc1.Instance = ADC1;
|
|
8001fa4: f640 1214 movw r2, #2324 ; 0x914
|
|
8001fa8: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
8001fac: 2300 movs r3, #0
|
|
8001fae: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8001fb2: 6013 str r3, [r2, #0]
|
|
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
|
|
8001fb4: f640 1314 movw r3, #2324 ; 0x914
|
|
8001fb8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001fbc: 2200 movs r2, #0
|
|
8001fbe: 605a str r2, [r3, #4]
|
|
hadc1.Init.Resolution = ADC_RESOLUTION_10B;
|
|
8001fc0: f640 1314 movw r3, #2324 ; 0x914
|
|
8001fc4: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001fc8: 2208 movs r2, #8
|
|
8001fca: 609a str r2, [r3, #8]
|
|
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
8001fcc: f640 1314 movw r3, #2324 ; 0x914
|
|
8001fd0: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001fd4: 2200 movs r2, #0
|
|
8001fd6: 60da str r2, [r3, #12]
|
|
hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;
|
|
8001fd8: f640 1314 movw r3, #2324 ; 0x914
|
|
8001fdc: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001fe0: 2201 movs r2, #1
|
|
8001fe2: 611a str r2, [r3, #16]
|
|
hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV;
|
|
8001fe4: f640 1314 movw r3, #2324 ; 0x914
|
|
8001fe8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001fec: 2208 movs r2, #8
|
|
8001fee: 615a str r2, [r3, #20]
|
|
hadc1.Init.LowPowerAutoWait = DISABLE;
|
|
8001ff0: f640 1314 movw r3, #2324 ; 0x914
|
|
8001ff4: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8001ff8: 2200 movs r2, #0
|
|
8001ffa: 761a strb r2, [r3, #24]
|
|
hadc1.Init.ContinuousConvMode = DISABLE;
|
|
8001ffc: f640 1314 movw r3, #2324 ; 0x914
|
|
8002000: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002004: 2200 movs r2, #0
|
|
8002006: 765a strb r2, [r3, #25]
|
|
hadc1.Init.NbrOfConversion = 2;
|
|
8002008: f640 1314 movw r3, #2324 ; 0x914
|
|
800200c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002010: 2202 movs r2, #2
|
|
8002012: 61da str r2, [r3, #28]
|
|
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
|
8002014: f640 1314 movw r3, #2324 ; 0x914
|
|
8002018: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800201c: 2200 movs r2, #0
|
|
800201e: f883 2020 strb.w r2, [r3, #32]
|
|
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
8002022: f640 1314 movw r3, #2324 ; 0x914
|
|
8002026: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800202a: 2200 movs r2, #0
|
|
800202c: 629a str r2, [r3, #40] ; 0x28
|
|
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
|
800202e: f640 1314 movw r3, #2324 ; 0x914
|
|
8002032: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002036: 2200 movs r2, #0
|
|
8002038: 62da str r2, [r3, #44] ; 0x2c
|
|
hadc1.Init.DMAContinuousRequests = DISABLE;
|
|
800203a: f640 1314 movw r3, #2324 ; 0x914
|
|
800203e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002042: 2200 movs r2, #0
|
|
8002044: f883 2030 strb.w r2, [r3, #48] ; 0x30
|
|
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
|
|
8002048: f640 1314 movw r3, #2324 ; 0x914
|
|
800204c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002050: 2200 movs r2, #0
|
|
8002052: 635a str r2, [r3, #52] ; 0x34
|
|
hadc1.Init.OversamplingMode = DISABLE;
|
|
8002054: f640 1314 movw r3, #2324 ; 0x914
|
|
8002058: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800205c: 2200 movs r2, #0
|
|
800205e: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
8002062: f640 1014 movw r0, #2324 ; 0x914
|
|
8002066: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800206a: f002 ff57 bl 8004f1c <HAL_ADC_Init>
|
|
800206e: 4603 mov r3, r0
|
|
8002070: 2b00 cmp r3, #0
|
|
8002072: d001 beq.n 8002078 <MX_ADC1_Init+0xf6>
|
|
{
|
|
Error_Handler();
|
|
8002074: f000 fa9a bl 80025ac <Error_Handler>
|
|
}
|
|
/** Configure the ADC multi-mode
|
|
*/
|
|
multimode.Mode = ADC_MODE_INDEPENDENT;
|
|
8002078: 2300 movs r3, #0
|
|
800207a: 61fb str r3, [r7, #28]
|
|
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
|
|
800207c: f107 031c add.w r3, r7, #28
|
|
8002080: 4619 mov r1, r3
|
|
8002082: f640 1014 movw r0, #2324 ; 0x914
|
|
8002086: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800208a: f004 f8be bl 800620a <HAL_ADCEx_MultiModeConfigChannel>
|
|
800208e: 4603 mov r3, r0
|
|
8002090: 2b00 cmp r3, #0
|
|
8002092: d001 beq.n 8002098 <MX_ADC1_Init+0x116>
|
|
{
|
|
Error_Handler();
|
|
8002094: f000 fa8a bl 80025ac <Error_Handler>
|
|
}
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_5;
|
|
8002098: 2320 movs r3, #32
|
|
800209a: f2c1 43f0 movt r3, #5360 ; 0x14f0
|
|
800209e: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
80020a0: 2306 movs r3, #6
|
|
80020a2: 60bb str r3, [r7, #8]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
|
|
80020a4: 2307 movs r3, #7
|
|
80020a6: 60fb str r3, [r7, #12]
|
|
sConfig.SingleDiff = ADC_SINGLE_ENDED;
|
|
80020a8: 237f movs r3, #127 ; 0x7f
|
|
80020aa: 613b str r3, [r7, #16]
|
|
sConfig.OffsetNumber = ADC_OFFSET_NONE;
|
|
80020ac: 2304 movs r3, #4
|
|
80020ae: 617b str r3, [r7, #20]
|
|
sConfig.Offset = 0;
|
|
80020b0: 2300 movs r3, #0
|
|
80020b2: 61bb str r3, [r7, #24]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80020b4: 1d3b adds r3, r7, #4
|
|
80020b6: 4619 mov r1, r3
|
|
80020b8: f640 1014 movw r0, #2324 ; 0x914
|
|
80020bc: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80020c0: f003 fa70 bl 80055a4 <HAL_ADC_ConfigChannel>
|
|
80020c4: 4603 mov r3, r0
|
|
80020c6: 2b00 cmp r3, #0
|
|
80020c8: d001 beq.n 80020ce <MX_ADC1_Init+0x14c>
|
|
{
|
|
Error_Handler();
|
|
80020ca: f000 fa6f bl 80025ac <Error_Handler>
|
|
}
|
|
/** Configure Regular Channel
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_6;
|
|
80020ce: 2340 movs r3, #64 ; 0x40
|
|
80020d0: f6c1 1320 movt r3, #6432 ; 0x1920
|
|
80020d4: 607b str r3, [r7, #4]
|
|
sConfig.Rank = ADC_REGULAR_RANK_2;
|
|
80020d6: 230c movs r3, #12
|
|
80020d8: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
80020da: 1d3b adds r3, r7, #4
|
|
80020dc: 4619 mov r1, r3
|
|
80020de: f640 1014 movw r0, #2324 ; 0x914
|
|
80020e2: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80020e6: f003 fa5d bl 80055a4 <HAL_ADC_ConfigChannel>
|
|
80020ea: 4603 mov r3, r0
|
|
80020ec: 2b00 cmp r3, #0
|
|
80020ee: d001 beq.n 80020f4 <MX_ADC1_Init+0x172>
|
|
{
|
|
Error_Handler();
|
|
80020f0: f000 fa5c bl 80025ac <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC1_Init 2 */
|
|
|
|
/* USER CODE END ADC1_Init 2 */
|
|
|
|
}
|
|
80020f4: bf00 nop
|
|
80020f6: 3728 adds r7, #40 ; 0x28
|
|
80020f8: 46bd mov sp, r7
|
|
80020fa: bd80 pop {r7, pc}
|
|
|
|
080020fc <MX_I2C1_Init>:
|
|
* @brief I2C1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void MX_I2C1_Init(void)
|
|
{
|
|
80020fc: b580 push {r7, lr}
|
|
80020fe: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8002100: f640 0244 movw r2, #2116 ; 0x844
|
|
8002104: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
8002108: f44f 43a8 mov.w r3, #21504 ; 0x5400
|
|
800210c: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8002110: 6013 str r3, [r2, #0]
|
|
hi2c1.Init.Timing = 0x10909CEC;
|
|
8002112: f640 0244 movw r2, #2116 ; 0x844
|
|
8002116: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
800211a: f649 43ec movw r3, #40172 ; 0x9cec
|
|
800211e: f2c1 0390 movt r3, #4240 ; 0x1090
|
|
8002122: 6053 str r3, [r2, #4]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8002124: f640 0344 movw r3, #2116 ; 0x844
|
|
8002128: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800212c: 2200 movs r2, #0
|
|
800212e: 609a str r2, [r3, #8]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8002130: f640 0344 movw r3, #2116 ; 0x844
|
|
8002134: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002138: 2201 movs r2, #1
|
|
800213a: 60da str r2, [r3, #12]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
800213c: f640 0344 movw r3, #2116 ; 0x844
|
|
8002140: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002144: 2200 movs r2, #0
|
|
8002146: 611a str r2, [r3, #16]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
8002148: f640 0344 movw r3, #2116 ; 0x844
|
|
800214c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002150: 2200 movs r2, #0
|
|
8002152: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
8002154: f640 0344 movw r3, #2116 ; 0x844
|
|
8002158: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800215c: 2200 movs r2, #0
|
|
800215e: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8002160: f640 0344 movw r3, #2116 ; 0x844
|
|
8002164: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002168: 2200 movs r2, #0
|
|
800216a: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
800216c: f640 0344 movw r3, #2116 ; 0x844
|
|
8002170: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002174: 2200 movs r2, #0
|
|
8002176: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
8002178: f640 0044 movw r0, #2116 ; 0x844
|
|
800217c: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002180: f004 fff1 bl 8007166 <HAL_I2C_Init>
|
|
8002184: 4603 mov r3, r0
|
|
8002186: 2b00 cmp r3, #0
|
|
8002188: d001 beq.n 800218e <MX_I2C1_Init+0x92>
|
|
{
|
|
Error_Handler();
|
|
800218a: f000 fa0f bl 80025ac <Error_Handler>
|
|
}
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
800218e: 2100 movs r1, #0
|
|
8002190: f640 0044 movw r0, #2116 ; 0x844
|
|
8002194: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002198: f005 fcc6 bl 8007b28 <HAL_I2CEx_ConfigAnalogFilter>
|
|
800219c: 4603 mov r3, r0
|
|
800219e: 2b00 cmp r3, #0
|
|
80021a0: d001 beq.n 80021a6 <MX_I2C1_Init+0xaa>
|
|
{
|
|
Error_Handler();
|
|
80021a2: f000 fa03 bl 80025ac <Error_Handler>
|
|
}
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
|
|
80021a6: 2100 movs r1, #0
|
|
80021a8: f640 0044 movw r0, #2116 ; 0x844
|
|
80021ac: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80021b0: f005 fd05 bl 8007bbe <HAL_I2CEx_ConfigDigitalFilter>
|
|
80021b4: 4603 mov r3, r0
|
|
80021b6: 2b00 cmp r3, #0
|
|
80021b8: d001 beq.n 80021be <MX_I2C1_Init+0xc2>
|
|
{
|
|
Error_Handler();
|
|
80021ba: f000 f9f7 bl 80025ac <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
80021be: bf00 nop
|
|
80021c0: bd80 pop {r7, pc}
|
|
|
|
080021c2 <MX_RTC_Init>:
|
|
* @brief RTC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_RTC_Init(void)
|
|
{
|
|
80021c2: b580 push {r7, lr}
|
|
80021c4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN RTC_Init 0 */
|
|
/*si la carte ne se réveille pas supprimer sDate sTime sAlarm*/
|
|
/* USER CODE END RTC_Init 0 */
|
|
|
|
/* USER CODE BEGIN RTC_Init 1 */
|
|
__HAL_RCC_RTC_ENABLE();
|
|
80021c6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80021ca: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80021ce: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
80021d2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80021d6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80021da: f442 4200 orr.w r2, r2, #32768 ; 0x8000
|
|
80021de: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
|
|
/* USER CODE END RTC_Init 1 */
|
|
/** Initialize RTC Only
|
|
*/
|
|
hrtc.Instance = RTC;
|
|
80021e2: f640 1278 movw r2, #2424 ; 0x978
|
|
80021e6: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
80021ea: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
80021ee: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
80021f2: 6013 str r3, [r2, #0]
|
|
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
|
|
80021f4: f640 1378 movw r3, #2424 ; 0x978
|
|
80021f8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80021fc: 2200 movs r2, #0
|
|
80021fe: 605a str r2, [r3, #4]
|
|
hrtc.Init.AsynchPrediv = 127;
|
|
8002200: f640 1378 movw r3, #2424 ; 0x978
|
|
8002204: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002208: 227f movs r2, #127 ; 0x7f
|
|
800220a: 609a str r2, [r3, #8]
|
|
hrtc.Init.SynchPrediv = 255;
|
|
800220c: f640 1378 movw r3, #2424 ; 0x978
|
|
8002210: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002214: 22ff movs r2, #255 ; 0xff
|
|
8002216: 60da str r2, [r3, #12]
|
|
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
|
|
8002218: f640 1378 movw r3, #2424 ; 0x978
|
|
800221c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002220: 2200 movs r2, #0
|
|
8002222: 611a str r2, [r3, #16]
|
|
hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_POS1;
|
|
8002224: f640 1378 movw r3, #2424 ; 0x978
|
|
8002228: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800222c: 2202 movs r2, #2
|
|
800222e: 615a str r2, [r3, #20]
|
|
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
|
8002230: f640 1378 movw r3, #2424 ; 0x978
|
|
8002234: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002238: 2200 movs r2, #0
|
|
800223a: 619a str r2, [r3, #24]
|
|
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
|
800223c: f640 1378 movw r3, #2424 ; 0x978
|
|
8002240: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002244: 2200 movs r2, #0
|
|
8002246: 61da str r2, [r3, #28]
|
|
if (HAL_RTC_Init(&hrtc) != HAL_OK)
|
|
8002248: f640 1078 movw r0, #2424 ; 0x978
|
|
800224c: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002250: f007 fbdb bl 8009a0a <HAL_RTC_Init>
|
|
8002254: 4603 mov r3, r0
|
|
8002256: 2b00 cmp r3, #0
|
|
8002258: d001 beq.n 800225e <MX_RTC_Init+0x9c>
|
|
{
|
|
Error_Handler();
|
|
800225a: f000 f9a7 bl 80025ac <Error_Handler>
|
|
}
|
|
/** Enable Calibration
|
|
*/
|
|
if (HAL_RTCEx_SetCalibrationOutPut(&hrtc, RTC_CALIBOUTPUT_1HZ) != HAL_OK)
|
|
800225e: f44f 2100 mov.w r1, #524288 ; 0x80000
|
|
8002262: f640 1078 movw r0, #2424 ; 0x978
|
|
8002266: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800226a: f007 fdb6 bl 8009dda <HAL_RTCEx_SetCalibrationOutPut>
|
|
800226e: 4603 mov r3, r0
|
|
8002270: 2b00 cmp r3, #0
|
|
8002272: d001 beq.n 8002278 <MX_RTC_Init+0xb6>
|
|
{
|
|
Error_Handler();
|
|
8002274: f000 f99a bl 80025ac <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN RTC_Init 2 */
|
|
HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 10*60, RTC_WAKEUPCLOCK_CK_SPRE_16BITS);
|
|
8002278: 2204 movs r2, #4
|
|
800227a: f44f 7116 mov.w r1, #600 ; 0x258
|
|
800227e: f640 1078 movw r0, #2424 ; 0x978
|
|
8002282: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002286: f007 fce5 bl 8009c54 <HAL_RTCEx_SetWakeUpTimer_IT>
|
|
/* USER CODE END RTC_Init 2 */
|
|
|
|
}
|
|
800228a: bf00 nop
|
|
800228c: bd80 pop {r7, pc}
|
|
|
|
0800228e <MX_UART5_Init>:
|
|
* @brief UART5 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART5_Init(void)
|
|
{
|
|
800228e: b580 push {r7, lr}
|
|
8002290: af00 add r7, sp, #0
|
|
/* USER CODE END UART5_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART5_Init 1 */
|
|
|
|
/* USER CODE END UART5_Init 1 */
|
|
huart5.Instance = UART5;
|
|
8002292: f640 0290 movw r2, #2192 ; 0x890
|
|
8002296: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
800229a: f44f 43a0 mov.w r3, #20480 ; 0x5000
|
|
800229e: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
80022a2: 6013 str r3, [r2, #0]
|
|
huart5.Init.BaudRate = 115200;
|
|
80022a4: f640 0390 movw r3, #2192 ; 0x890
|
|
80022a8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80022ac: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
80022b0: 605a str r2, [r3, #4]
|
|
huart5.Init.WordLength = UART_WORDLENGTH_8B;
|
|
80022b2: f640 0390 movw r3, #2192 ; 0x890
|
|
80022b6: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80022ba: 2200 movs r2, #0
|
|
80022bc: 609a str r2, [r3, #8]
|
|
huart5.Init.StopBits = UART_STOPBITS_1;
|
|
80022be: f640 0390 movw r3, #2192 ; 0x890
|
|
80022c2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80022c6: 2200 movs r2, #0
|
|
80022c8: 60da str r2, [r3, #12]
|
|
huart5.Init.Parity = UART_PARITY_NONE;
|
|
80022ca: f640 0390 movw r3, #2192 ; 0x890
|
|
80022ce: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80022d2: 2200 movs r2, #0
|
|
80022d4: 611a str r2, [r3, #16]
|
|
huart5.Init.Mode = UART_MODE_TX_RX;
|
|
80022d6: f640 0390 movw r3, #2192 ; 0x890
|
|
80022da: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80022de: 220c movs r2, #12
|
|
80022e0: 615a str r2, [r3, #20]
|
|
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80022e2: f640 0390 movw r3, #2192 ; 0x890
|
|
80022e6: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80022ea: 2200 movs r2, #0
|
|
80022ec: 619a str r2, [r3, #24]
|
|
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80022ee: f640 0390 movw r3, #2192 ; 0x890
|
|
80022f2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80022f6: 2200 movs r2, #0
|
|
80022f8: 61da str r2, [r3, #28]
|
|
huart5.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
80022fa: f640 0390 movw r3, #2192 ; 0x890
|
|
80022fe: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002302: 2200 movs r2, #0
|
|
8002304: 621a str r2, [r3, #32]
|
|
huart5.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8002306: f640 0390 movw r3, #2192 ; 0x890
|
|
800230a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800230e: 2200 movs r2, #0
|
|
8002310: 625a str r2, [r3, #36] ; 0x24
|
|
if (HAL_UART_Init(&huart5) != HAL_OK)
|
|
8002312: f640 0090 movw r0, #2192 ; 0x890
|
|
8002316: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
800231a: f007 fda5 bl 8009e68 <HAL_UART_Init>
|
|
800231e: 4603 mov r3, r0
|
|
8002320: 2b00 cmp r3, #0
|
|
8002322: d001 beq.n 8002328 <MX_UART5_Init+0x9a>
|
|
{
|
|
Error_Handler();
|
|
8002324: f000 f942 bl 80025ac <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART5_Init 2 */
|
|
//ADS1232Power(&huart5,SET);
|
|
/* USER CODE END UART5_Init 2 */
|
|
|
|
}
|
|
8002328: bf00 nop
|
|
800232a: bd80 pop {r7, pc}
|
|
|
|
0800232c <MX_USART2_UART_Init>:
|
|
* @brief USART2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART2_UART_Init(void)
|
|
{
|
|
800232c: b580 push {r7, lr}
|
|
800232e: af00 add r7, sp, #0
|
|
/* USER CODE END USART2_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART2_Init 1 */
|
|
|
|
/* USER CODE END USART2_Init 1 */
|
|
huart2.Instance = USART2;
|
|
8002330: f640 129c movw r2, #2460 ; 0x99c
|
|
8002334: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
8002338: f44f 4388 mov.w r3, #17408 ; 0x4400
|
|
800233c: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8002340: 6013 str r3, [r2, #0]
|
|
huart2.Init.BaudRate = 9600;
|
|
8002342: f640 139c movw r3, #2460 ; 0x99c
|
|
8002346: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800234a: f44f 5216 mov.w r2, #9600 ; 0x2580
|
|
800234e: 605a str r2, [r3, #4]
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8002350: f640 139c movw r3, #2460 ; 0x99c
|
|
8002354: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002358: 2200 movs r2, #0
|
|
800235a: 609a str r2, [r3, #8]
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
800235c: f640 139c movw r3, #2460 ; 0x99c
|
|
8002360: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002364: 2200 movs r2, #0
|
|
8002366: 60da str r2, [r3, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
8002368: f640 139c movw r3, #2460 ; 0x99c
|
|
800236c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002370: 2200 movs r2, #0
|
|
8002372: 611a str r2, [r3, #16]
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
8002374: f640 139c movw r3, #2460 ; 0x99c
|
|
8002378: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800237c: 220c movs r2, #12
|
|
800237e: 615a str r2, [r3, #20]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8002380: f640 139c movw r3, #2460 ; 0x99c
|
|
8002384: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002388: 2200 movs r2, #0
|
|
800238a: 619a str r2, [r3, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
800238c: f640 139c movw r3, #2460 ; 0x99c
|
|
8002390: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002394: 2200 movs r2, #0
|
|
8002396: 61da str r2, [r3, #28]
|
|
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8002398: f640 139c movw r3, #2460 ; 0x99c
|
|
800239c: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80023a0: 2200 movs r2, #0
|
|
80023a2: 621a str r2, [r3, #32]
|
|
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
80023a4: f640 139c movw r3, #2460 ; 0x99c
|
|
80023a8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80023ac: 2200 movs r2, #0
|
|
80023ae: 625a str r2, [r3, #36] ; 0x24
|
|
if (HAL_UART_Init(&huart2) != HAL_OK)
|
|
80023b0: f640 109c movw r0, #2460 ; 0x99c
|
|
80023b4: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
80023b8: f007 fd56 bl 8009e68 <HAL_UART_Init>
|
|
80023bc: 4603 mov r3, r0
|
|
80023be: 2b00 cmp r3, #0
|
|
80023c0: d001 beq.n 80023c6 <MX_USART2_UART_Init+0x9a>
|
|
{
|
|
Error_Handler();
|
|
80023c2: f000 f8f3 bl 80025ac <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART2_Init 2 */
|
|
|
|
/* USER CODE END USART2_Init 2 */
|
|
|
|
}
|
|
80023c6: bf00 nop
|
|
80023c8: bd80 pop {r7, pc}
|
|
|
|
080023ca <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
80023ca: b580 push {r7, lr}
|
|
80023cc: b08a sub sp, #40 ; 0x28
|
|
80023ce: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80023d0: f107 0314 add.w r3, r7, #20
|
|
80023d4: 2200 movs r2, #0
|
|
80023d6: 601a str r2, [r3, #0]
|
|
80023d8: 605a str r2, [r3, #4]
|
|
80023da: 609a str r2, [r3, #8]
|
|
80023dc: 60da str r2, [r3, #12]
|
|
80023de: 611a str r2, [r3, #16]
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80023e0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80023e4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80023e8: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
80023ea: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80023ee: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80023f2: f042 0204 orr.w r2, r2, #4
|
|
80023f6: 64da str r2, [r3, #76] ; 0x4c
|
|
80023f8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80023fc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002400: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
8002402: f003 0304 and.w r3, r3, #4
|
|
8002406: 613b str r3, [r7, #16]
|
|
8002408: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
800240a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800240e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002412: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8002414: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002418: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800241c: f042 0280 orr.w r2, r2, #128 ; 0x80
|
|
8002420: 64da str r2, [r3, #76] ; 0x4c
|
|
8002422: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002426: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800242a: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
800242c: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
8002430: 60fb str r3, [r7, #12]
|
|
8002432: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002434: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002438: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800243c: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
800243e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002442: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002446: f042 0201 orr.w r2, r2, #1
|
|
800244a: 64da str r2, [r3, #76] ; 0x4c
|
|
800244c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002450: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002454: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
8002456: f003 0301 and.w r3, r3, #1
|
|
800245a: 60bb str r3, [r7, #8]
|
|
800245c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800245e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002462: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002466: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8002468: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800246c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002470: f042 0202 orr.w r2, r2, #2
|
|
8002474: 64da str r2, [r3, #76] ; 0x4c
|
|
8002476: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800247a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800247e: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
8002480: f003 0302 and.w r3, r3, #2
|
|
8002484: 607b str r3, [r7, #4]
|
|
8002486: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8002488: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800248c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002490: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8002492: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002496: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800249a: f042 0208 orr.w r2, r2, #8
|
|
800249e: 64da str r2, [r3, #76] ; 0x4c
|
|
80024a0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80024a4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80024a8: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
80024aa: f003 0308 and.w r3, r3, #8
|
|
80024ae: 603b str r3, [r7, #0]
|
|
80024b0: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, LD2_Pin|GPIO_PIN_8, GPIO_PIN_RESET);
|
|
80024b2: 2200 movs r2, #0
|
|
80024b4: f44f 7190 mov.w r1, #288 ; 0x120
|
|
80024b8: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
80024bc: f004 fe3b bl 8007136 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, GPIO_PIN_7, GPIO_PIN_RESET);
|
|
80024c0: 2200 movs r2, #0
|
|
80024c2: 2180 movs r1, #128 ; 0x80
|
|
80024c4: f44f 6000 mov.w r0, #2048 ; 0x800
|
|
80024c8: f6c4 0000 movt r0, #18432 ; 0x4800
|
|
80024cc: f004 fe33 bl 8007136 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin : B1_Pin */
|
|
GPIO_InitStruct.Pin = B1_Pin;
|
|
80024d0: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80024d4: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
80024d6: 2300 movs r3, #0
|
|
80024d8: f2c1 0321 movt r3, #4129 ; 0x1021
|
|
80024dc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80024de: 2300 movs r3, #0
|
|
80024e0: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
|
|
80024e2: f107 0314 add.w r3, r7, #20
|
|
80024e6: 4619 mov r1, r3
|
|
80024e8: f44f 6000 mov.w r0, #2048 ; 0x800
|
|
80024ec: f6c4 0000 movt r0, #18432 ; 0x4800
|
|
80024f0: f004 fc53 bl 8006d9a <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LD2_Pin PA8 */
|
|
GPIO_InitStruct.Pin = LD2_Pin|GPIO_PIN_8;
|
|
80024f4: f44f 7390 mov.w r3, #288 ; 0x120
|
|
80024f8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80024fa: 2301 movs r3, #1
|
|
80024fc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80024fe: 2300 movs r3, #0
|
|
8002500: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8002502: 2300 movs r3, #0
|
|
8002504: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002506: f107 0314 add.w r3, r7, #20
|
|
800250a: 4619 mov r1, r3
|
|
800250c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
8002510: f004 fc43 bl 8006d9a <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : PC7 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_7;
|
|
8002514: 2380 movs r3, #128 ; 0x80
|
|
8002516: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8002518: 2301 movs r3, #1
|
|
800251a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800251c: 2300 movs r3, #0
|
|
800251e: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8002520: 2300 movs r3, #0
|
|
8002522: 623b str r3, [r7, #32]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8002524: f107 0314 add.w r3, r7, #20
|
|
8002528: 4619 mov r1, r3
|
|
800252a: f44f 6000 mov.w r0, #2048 ; 0x800
|
|
800252e: f6c4 0000 movt r0, #18432 ; 0x4800
|
|
8002532: f004 fc32 bl 8006d9a <HAL_GPIO_Init>
|
|
|
|
}
|
|
8002536: bf00 nop
|
|
8002538: 3728 adds r7, #40 ; 0x28
|
|
800253a: 46bd mov sp, r7
|
|
800253c: bd80 pop {r7, pc}
|
|
|
|
0800253e <__io_putchar>:
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
int __io_putchar(int ch)
|
|
{
|
|
800253e: b580 push {r7, lr}
|
|
8002540: b082 sub sp, #8
|
|
8002542: af00 add r7, sp, #0
|
|
8002544: 6078 str r0, [r7, #4]
|
|
ITM_SendChar(ch);
|
|
8002546: 687b ldr r3, [r7, #4]
|
|
8002548: 4618 mov r0, r3
|
|
800254a: f7ff fc1f bl 8001d8c <ITM_SendChar>
|
|
return(ch);
|
|
800254e: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002550: 4618 mov r0, r3
|
|
8002552: 3708 adds r7, #8
|
|
8002554: 46bd mov sp, r7
|
|
8002556: bd80 pop {r7, pc}
|
|
|
|
08002558 <_write>:
|
|
|
|
int _write(int file, char *ptr, int len)
|
|
{
|
|
8002558: b580 push {r7, lr}
|
|
800255a: b086 sub sp, #24
|
|
800255c: af00 add r7, sp, #0
|
|
800255e: 60f8 str r0, [r7, #12]
|
|
8002560: 60b9 str r1, [r7, #8]
|
|
8002562: 607a str r2, [r7, #4]
|
|
int DataIdx;
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002564: 2300 movs r3, #0
|
|
8002566: 617b str r3, [r7, #20]
|
|
8002568: e009 b.n 800257e <_write+0x26>
|
|
{
|
|
__io_putchar(*ptr++);
|
|
800256a: 68bb ldr r3, [r7, #8]
|
|
800256c: 1c5a adds r2, r3, #1
|
|
800256e: 60ba str r2, [r7, #8]
|
|
8002570: 781b ldrb r3, [r3, #0]
|
|
8002572: 4618 mov r0, r3
|
|
8002574: f7ff ffe3 bl 800253e <__io_putchar>
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002578: 697b ldr r3, [r7, #20]
|
|
800257a: 3301 adds r3, #1
|
|
800257c: 617b str r3, [r7, #20]
|
|
800257e: 697a ldr r2, [r7, #20]
|
|
8002580: 687b ldr r3, [r7, #4]
|
|
8002582: 429a cmp r2, r3
|
|
8002584: dbf1 blt.n 800256a <_write+0x12>
|
|
}
|
|
return len;
|
|
8002586: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002588: 4618 mov r0, r3
|
|
800258a: 3718 adds r7, #24
|
|
800258c: 46bd mov sp, r7
|
|
800258e: bd80 pop {r7, pc}
|
|
|
|
08002590 <HAL_RTCEx_WakeUpTimerEventCallback>:
|
|
|
|
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8002590: b580 push {r7, lr}
|
|
8002592: b082 sub sp, #8
|
|
8002594: af00 add r7, sp, #0
|
|
8002596: 6078 str r0, [r7, #4]
|
|
printf("wake up coucou lalala \r\n");
|
|
8002598: f24e 3008 movw r0, #58120 ; 0xe308
|
|
800259c: f6c0 0000 movt r0, #2048 ; 0x800
|
|
80025a0: f009 f9e2 bl 800b968 <puts>
|
|
}
|
|
80025a4: bf00 nop
|
|
80025a6: 3708 adds r7, #8
|
|
80025a8: 46bd mov sp, r7
|
|
80025aa: bd80 pop {r7, pc}
|
|
|
|
080025ac <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
80025ac: b480 push {r7}
|
|
80025ae: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80025b0: b672 cpsid i
|
|
}
|
|
80025b2: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
80025b4: e7fe b.n 80025b4 <Error_Handler+0x8>
|
|
|
|
080025b6 <buffer_init>:
|
|
|
|
#include "lora_app.h"
|
|
|
|
|
|
void buffer_init(circular_buf_t *buff,uint32_t* list,size_t size,uint32_t baseAdress)
|
|
{
|
|
80025b6: b480 push {r7}
|
|
80025b8: b087 sub sp, #28
|
|
80025ba: af00 add r7, sp, #0
|
|
80025bc: 60f8 str r0, [r7, #12]
|
|
80025be: 60b9 str r1, [r7, #8]
|
|
80025c0: 607a str r2, [r7, #4]
|
|
80025c2: 603b str r3, [r7, #0]
|
|
buff->size=size;
|
|
80025c4: 68fb ldr r3, [r7, #12]
|
|
80025c6: 687a ldr r2, [r7, #4]
|
|
80025c8: 609a str r2, [r3, #8]
|
|
buff->base_adress=baseAdress;
|
|
80025ca: 68fb ldr r3, [r7, #12]
|
|
80025cc: 683a ldr r2, [r7, #0]
|
|
80025ce: 60da str r2, [r3, #12]
|
|
buff->cursor=0;
|
|
80025d0: 68fb ldr r3, [r7, #12]
|
|
80025d2: 2200 movs r2, #0
|
|
80025d4: 711a strb r2, [r3, #4]
|
|
|
|
uint32_t tmp=baseAdress;
|
|
80025d6: 683b ldr r3, [r7, #0]
|
|
80025d8: 617b str r3, [r7, #20]
|
|
|
|
for(int i=0;i<=size;i++)
|
|
80025da: 2300 movs r3, #0
|
|
80025dc: 613b str r3, [r7, #16]
|
|
80025de: e00c b.n 80025fa <buffer_init+0x44>
|
|
{
|
|
// buff->buffer[i]=tmp;
|
|
list[i]=tmp;
|
|
80025e0: 693b ldr r3, [r7, #16]
|
|
80025e2: 009b lsls r3, r3, #2
|
|
80025e4: 68ba ldr r2, [r7, #8]
|
|
80025e6: 4413 add r3, r2
|
|
80025e8: 697a ldr r2, [r7, #20]
|
|
80025ea: 601a str r2, [r3, #0]
|
|
tmp+=0x800;
|
|
80025ec: 697b ldr r3, [r7, #20]
|
|
80025ee: f503 6300 add.w r3, r3, #2048 ; 0x800
|
|
80025f2: 617b str r3, [r7, #20]
|
|
for(int i=0;i<=size;i++)
|
|
80025f4: 693b ldr r3, [r7, #16]
|
|
80025f6: 3301 adds r3, #1
|
|
80025f8: 613b str r3, [r7, #16]
|
|
80025fa: 693b ldr r3, [r7, #16]
|
|
80025fc: 687a ldr r2, [r7, #4]
|
|
80025fe: 429a cmp r2, r3
|
|
8002600: d2ee bcs.n 80025e0 <buffer_init+0x2a>
|
|
}
|
|
buff->buffer=list;
|
|
8002602: 68fb ldr r3, [r7, #12]
|
|
8002604: 68ba ldr r2, [r7, #8]
|
|
8002606: 601a str r2, [r3, #0]
|
|
|
|
}
|
|
8002608: bf00 nop
|
|
800260a: 371c adds r7, #28
|
|
800260c: 46bd mov sp, r7
|
|
800260e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002612: 4770 bx lr
|
|
|
|
08002614 <buffer_put>:
|
|
/*put a paylaod message into the buffer queue */
|
|
HAL_StatusTypeDef buffer_put(circular_buf_t *buff,uint8_t *p_wr)
|
|
{
|
|
8002614: b580 push {r7, lr}
|
|
8002616: b084 sub sp, #16
|
|
8002618: af00 add r7, sp, #0
|
|
800261a: 6078 str r0, [r7, #4]
|
|
800261c: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef rslt=HAL_OK;
|
|
800261e: 2300 movs r3, #0
|
|
8002620: 73fb strb r3, [r7, #15]
|
|
|
|
|
|
rslt=memory_write(p_wr,buff->buffer[buff->cursor]);
|
|
8002622: 687b ldr r3, [r7, #4]
|
|
8002624: 681a ldr r2, [r3, #0]
|
|
8002626: 687b ldr r3, [r7, #4]
|
|
8002628: 791b ldrb r3, [r3, #4]
|
|
800262a: 009b lsls r3, r3, #2
|
|
800262c: 4413 add r3, r2
|
|
800262e: 681b ldr r3, [r3, #0]
|
|
8002630: 4619 mov r1, r3
|
|
8002632: 6838 ldr r0, [r7, #0]
|
|
8002634: f7fe fe77 bl 8001326 <memory_write>
|
|
8002638: 4603 mov r3, r0
|
|
800263a: 73fb strb r3, [r7, #15]
|
|
return rslt;
|
|
800263c: 7bfb ldrb r3, [r7, #15]
|
|
|
|
}
|
|
800263e: 4618 mov r0, r3
|
|
8002640: 3710 adds r7, #16
|
|
8002642: 46bd mov sp, r7
|
|
8002644: bd80 pop {r7, pc}
|
|
|
|
08002646 <__movecursor>:
|
|
|
|
void __movecursor(circular_buf_t *buff)
|
|
{
|
|
8002646: b480 push {r7}
|
|
8002648: b083 sub sp, #12
|
|
800264a: af00 add r7, sp, #0
|
|
800264c: 6078 str r0, [r7, #4]
|
|
if(buff->cursor<=buff->size)
|
|
800264e: 687b ldr r3, [r7, #4]
|
|
8002650: 791b ldrb r3, [r3, #4]
|
|
8002652: 461a mov r2, r3
|
|
8002654: 687b ldr r3, [r7, #4]
|
|
8002656: 689b ldr r3, [r3, #8]
|
|
8002658: 429a cmp r2, r3
|
|
800265a: d806 bhi.n 800266a <__movecursor+0x24>
|
|
{
|
|
buff->cursor++;
|
|
800265c: 687b ldr r3, [r7, #4]
|
|
800265e: 791b ldrb r3, [r3, #4]
|
|
8002660: 3301 adds r3, #1
|
|
8002662: b2da uxtb r2, r3
|
|
8002664: 687b ldr r3, [r7, #4]
|
|
8002666: 711a strb r2, [r3, #4]
|
|
}
|
|
else
|
|
{
|
|
buff->cursor=0;
|
|
}
|
|
}
|
|
8002668: e002 b.n 8002670 <__movecursor+0x2a>
|
|
buff->cursor=0;
|
|
800266a: 687b ldr r3, [r7, #4]
|
|
800266c: 2200 movs r2, #0
|
|
800266e: 711a strb r2, [r3, #4]
|
|
}
|
|
8002670: bf00 nop
|
|
8002672: 370c adds r7, #12
|
|
8002674: 46bd mov sp, r7
|
|
8002676: f85d 7b04 ldr.w r7, [sp], #4
|
|
800267a: 4770 bx lr
|
|
|
|
0800267c <buffer_get>:
|
|
/*get a payload message from the buffer queue*/
|
|
HAL_StatusTypeDef buffer_get(circular_buf_t *buff,uint8_t *p_rd,size_t size)
|
|
{
|
|
800267c: b580 push {r7, lr}
|
|
800267e: b086 sub sp, #24
|
|
8002680: af00 add r7, sp, #0
|
|
8002682: 60f8 str r0, [r7, #12]
|
|
8002684: 60b9 str r1, [r7, #8]
|
|
8002686: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef rslt=HAL_OK;
|
|
8002688: 2300 movs r3, #0
|
|
800268a: 75fb strb r3, [r7, #23]
|
|
|
|
rslt=memory_read(p_rd,buff->buffer[buff->cursor],size);
|
|
800268c: 68fb ldr r3, [r7, #12]
|
|
800268e: 681a ldr r2, [r3, #0]
|
|
8002690: 68fb ldr r3, [r7, #12]
|
|
8002692: 791b ldrb r3, [r3, #4]
|
|
8002694: 009b lsls r3, r3, #2
|
|
8002696: 4413 add r3, r2
|
|
8002698: 681b ldr r3, [r3, #0]
|
|
800269a: 687a ldr r2, [r7, #4]
|
|
800269c: 4619 mov r1, r3
|
|
800269e: 68b8 ldr r0, [r7, #8]
|
|
80026a0: f7fe fe83 bl 80013aa <memory_read>
|
|
80026a4: 4603 mov r3, r0
|
|
80026a6: 75fb strb r3, [r7, #23]
|
|
|
|
return rslt;
|
|
80026a8: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80026aa: 4618 mov r0, r3
|
|
80026ac: 3718 adds r7, #24
|
|
80026ae: 46bd mov sp, r7
|
|
80026b0: bd80 pop {r7, pc}
|
|
|
|
080026b2 <buffer_flush>:
|
|
/*erase de memory page before wrinting in it */
|
|
HAL_StatusTypeDef buffer_flush(circular_buf_t *buff)
|
|
{
|
|
80026b2: b580 push {r7, lr}
|
|
80026b4: b084 sub sp, #16
|
|
80026b6: af00 add r7, sp, #0
|
|
80026b8: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef rslt=HAL_OK;
|
|
80026ba: 2300 movs r3, #0
|
|
80026bc: 73fb strb r3, [r7, #15]
|
|
|
|
if(BASEPAGE+buff->cursor>127)
|
|
80026be: 687b ldr r3, [r7, #4]
|
|
80026c0: 791b ldrb r3, [r3, #4]
|
|
80026c2: 2b02 cmp r3, #2
|
|
80026c4: d901 bls.n 80026ca <buffer_flush+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
80026c6: 2301 movs r3, #1
|
|
80026c8: e009 b.n 80026de <buffer_flush+0x2c>
|
|
}
|
|
else
|
|
rslt=memory_erasePage(BASEPAGE+buff->cursor);
|
|
80026ca: 687b ldr r3, [r7, #4]
|
|
80026cc: 791b ldrb r3, [r3, #4]
|
|
80026ce: 337d adds r3, #125 ; 0x7d
|
|
80026d0: b2db uxtb r3, r3
|
|
80026d2: 4618 mov r0, r3
|
|
80026d4: f7fe fdee bl 80012b4 <memory_erasePage>
|
|
80026d8: 4603 mov r3, r0
|
|
80026da: 73fb strb r3, [r7, #15]
|
|
|
|
return rslt;
|
|
80026dc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80026de: 4618 mov r0, r3
|
|
80026e0: 3710 adds r7, #16
|
|
80026e2: 46bd mov sp, r7
|
|
80026e4: bd80 pop {r7, pc}
|
|
|
|
080026e6 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
80026e6: b480 push {r7}
|
|
80026e8: b083 sub sp, #12
|
|
80026ea: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80026ec: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80026f0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80026f4: 6e1a ldr r2, [r3, #96] ; 0x60
|
|
80026f6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80026fa: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80026fe: f042 0201 orr.w r2, r2, #1
|
|
8002702: 661a str r2, [r3, #96] ; 0x60
|
|
8002704: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002708: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800270c: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
800270e: f003 0301 and.w r3, r3, #1
|
|
8002712: 607b str r3, [r7, #4]
|
|
8002714: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8002716: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800271a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800271e: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8002720: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002724: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002728: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
|
|
800272c: 659a str r2, [r3, #88] ; 0x58
|
|
800272e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002732: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002736: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8002738: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
800273c: 603b str r3, [r7, #0]
|
|
800273e: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8002740: bf00 nop
|
|
8002742: 370c adds r7, #12
|
|
8002744: 46bd mov sp, r7
|
|
8002746: f85d 7b04 ldr.w r7, [sp], #4
|
|
800274a: 4770 bx lr
|
|
|
|
0800274c <HAL_ADC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hadc: ADC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
|
{
|
|
800274c: b580 push {r7, lr}
|
|
800274e: b0ac sub sp, #176 ; 0xb0
|
|
8002750: af00 add r7, sp, #0
|
|
8002752: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002754: f107 039c add.w r3, r7, #156 ; 0x9c
|
|
8002758: 2200 movs r2, #0
|
|
800275a: 601a str r2, [r3, #0]
|
|
800275c: 605a str r2, [r3, #4]
|
|
800275e: 609a str r2, [r3, #8]
|
|
8002760: 60da str r2, [r3, #12]
|
|
8002762: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002764: f107 0314 add.w r3, r7, #20
|
|
8002768: 2288 movs r2, #136 ; 0x88
|
|
800276a: 2100 movs r1, #0
|
|
800276c: 4618 mov r0, r3
|
|
800276e: f008 fc03 bl 800af78 <memset>
|
|
if(hadc->Instance==ADC1)
|
|
8002772: 687b ldr r3, [r7, #4]
|
|
8002774: 681a ldr r2, [r3, #0]
|
|
8002776: 2300 movs r3, #0
|
|
8002778: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
800277c: 429a cmp r2, r3
|
|
800277e: d159 bne.n 8002834 <HAL_ADC_MspInit+0xe8>
|
|
/* USER CODE BEGIN ADC1_MspInit 0 */
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
|
|
8002780: f44f 4380 mov.w r3, #16384 ; 0x4000
|
|
8002784: 617b str r3, [r7, #20]
|
|
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1;
|
|
8002786: f04f 5380 mov.w r3, #268435456 ; 0x10000000
|
|
800278a: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
|
|
800278e: 2301 movs r3, #1
|
|
8002790: 61bb str r3, [r7, #24]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
|
8002792: 2301 movs r3, #1
|
|
8002794: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
|
|
8002796: 2318 movs r3, #24
|
|
8002798: 623b str r3, [r7, #32]
|
|
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
|
800279a: 2307 movs r3, #7
|
|
800279c: 627b str r3, [r7, #36] ; 0x24
|
|
PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
|
800279e: 2302 movs r3, #2
|
|
80027a0: 62bb str r3, [r7, #40] ; 0x28
|
|
PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
|
80027a2: 2302 movs r3, #2
|
|
80027a4: 62fb str r3, [r7, #44] ; 0x2c
|
|
PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_ADC1CLK;
|
|
80027a6: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
80027aa: 633b str r3, [r7, #48] ; 0x30
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
80027ac: f107 0314 add.w r3, r7, #20
|
|
80027b0: 4618 mov r0, r3
|
|
80027b2: f006 fb1b bl 8008dec <HAL_RCCEx_PeriphCLKConfig>
|
|
80027b6: 4603 mov r3, r0
|
|
80027b8: 2b00 cmp r3, #0
|
|
80027ba: d001 beq.n 80027c0 <HAL_ADC_MspInit+0x74>
|
|
{
|
|
Error_Handler();
|
|
80027bc: f7ff fef6 bl 80025ac <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_ADC_CLK_ENABLE();
|
|
80027c0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80027c4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80027c8: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
80027ca: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80027ce: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80027d2: f442 5200 orr.w r2, r2, #8192 ; 0x2000
|
|
80027d6: 64da str r2, [r3, #76] ; 0x4c
|
|
80027d8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80027dc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80027e0: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
80027e2: f403 5300 and.w r3, r3, #8192 ; 0x2000
|
|
80027e6: 613b str r3, [r7, #16]
|
|
80027e8: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80027ea: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80027ee: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80027f2: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
80027f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80027f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80027fc: f042 0201 orr.w r2, r2, #1
|
|
8002800: 64da str r2, [r3, #76] ; 0x4c
|
|
8002802: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002806: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800280a: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
800280c: f003 0301 and.w r3, r3, #1
|
|
8002810: 60fb str r3, [r7, #12]
|
|
8002812: 68fb ldr r3, [r7, #12]
|
|
/**ADC1 GPIO Configuration
|
|
PA0 ------> ADC1_IN5
|
|
PA1 ------> ADC1_IN6
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
|
8002814: 2303 movs r3, #3
|
|
8002816: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG_ADC_CONTROL;
|
|
800281a: 230b movs r3, #11
|
|
800281c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002820: 2300 movs r3, #0
|
|
8002822: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002826: f107 039c add.w r3, r7, #156 ; 0x9c
|
|
800282a: 4619 mov r1, r3
|
|
800282c: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
8002830: f004 fab3 bl 8006d9a <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN ADC1_MspInit 1 */
|
|
|
|
/* USER CODE END ADC1_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8002834: bf00 nop
|
|
8002836: 37b0 adds r7, #176 ; 0xb0
|
|
8002838: 46bd mov sp, r7
|
|
800283a: bd80 pop {r7, pc}
|
|
|
|
0800283c <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
800283c: b580 push {r7, lr}
|
|
800283e: b0ac sub sp, #176 ; 0xb0
|
|
8002840: af00 add r7, sp, #0
|
|
8002842: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002844: f107 039c add.w r3, r7, #156 ; 0x9c
|
|
8002848: 2200 movs r2, #0
|
|
800284a: 601a str r2, [r3, #0]
|
|
800284c: 605a str r2, [r3, #4]
|
|
800284e: 609a str r2, [r3, #8]
|
|
8002850: 60da str r2, [r3, #12]
|
|
8002852: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002854: f107 0314 add.w r3, r7, #20
|
|
8002858: 2288 movs r2, #136 ; 0x88
|
|
800285a: 2100 movs r1, #0
|
|
800285c: 4618 mov r0, r3
|
|
800285e: f008 fb8b bl 800af78 <memset>
|
|
if(hi2c->Instance==I2C1)
|
|
8002862: 687b ldr r3, [r7, #4]
|
|
8002864: 681a ldr r2, [r3, #0]
|
|
8002866: f44f 43a8 mov.w r3, #21504 ; 0x5400
|
|
800286a: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800286e: 429a cmp r2, r3
|
|
8002870: d150 bne.n 8002914 <HAL_I2C_MspInit+0xd8>
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
|
|
8002872: 2340 movs r3, #64 ; 0x40
|
|
8002874: 617b str r3, [r7, #20]
|
|
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
|
|
8002876: 2300 movs r3, #0
|
|
8002878: 667b str r3, [r7, #100] ; 0x64
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
800287a: f107 0314 add.w r3, r7, #20
|
|
800287e: 4618 mov r0, r3
|
|
8002880: f006 fab4 bl 8008dec <HAL_RCCEx_PeriphCLKConfig>
|
|
8002884: 4603 mov r3, r0
|
|
8002886: 2b00 cmp r3, #0
|
|
8002888: d001 beq.n 800288e <HAL_I2C_MspInit+0x52>
|
|
{
|
|
Error_Handler();
|
|
800288a: f7ff fe8f bl 80025ac <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800288e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002892: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002896: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8002898: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800289c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80028a0: f042 0202 orr.w r2, r2, #2
|
|
80028a4: 64da str r2, [r3, #76] ; 0x4c
|
|
80028a6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80028aa: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80028ae: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
80028b0: f003 0302 and.w r3, r3, #2
|
|
80028b4: 613b str r3, [r7, #16]
|
|
80028b6: 693b ldr r3, [r7, #16]
|
|
/**I2C1 GPIO Configuration
|
|
PB8 ------> I2C1_SCL
|
|
PB9 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
|
|
80028b8: f44f 7340 mov.w r3, #768 ; 0x300
|
|
80028bc: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
80028c0: 2312 movs r3, #18
|
|
80028c2: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80028c6: 2300 movs r3, #0
|
|
80028c8: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80028cc: 2303 movs r3, #3
|
|
80028ce: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
80028d2: 2304 movs r3, #4
|
|
80028d4: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80028d8: f107 039c add.w r3, r7, #156 ; 0x9c
|
|
80028dc: 4619 mov r1, r3
|
|
80028de: f44f 6080 mov.w r0, #1024 ; 0x400
|
|
80028e2: f6c4 0000 movt r0, #18432 ; 0x4800
|
|
80028e6: f004 fa58 bl 8006d9a <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
80028ea: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80028ee: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80028f2: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
80028f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80028f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80028fc: f442 1200 orr.w r2, r2, #2097152 ; 0x200000
|
|
8002900: 659a str r2, [r3, #88] ; 0x58
|
|
8002902: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002906: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800290a: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
800290c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
8002910: 60fb str r3, [r7, #12]
|
|
8002912: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN I2C1_MspInit 1 */
|
|
|
|
/* USER CODE END I2C1_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8002914: bf00 nop
|
|
8002916: 37b0 adds r7, #176 ; 0xb0
|
|
8002918: 46bd mov sp, r7
|
|
800291a: bd80 pop {r7, pc}
|
|
|
|
0800291c <HAL_RTC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hrtc: RTC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
|
|
{
|
|
800291c: b580 push {r7, lr}
|
|
800291e: b0aa sub sp, #168 ; 0xa8
|
|
8002920: af00 add r7, sp, #0
|
|
8002922: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002924: f107 0394 add.w r3, r7, #148 ; 0x94
|
|
8002928: 2200 movs r2, #0
|
|
800292a: 601a str r2, [r3, #0]
|
|
800292c: 605a str r2, [r3, #4]
|
|
800292e: 609a str r2, [r3, #8]
|
|
8002930: 60da str r2, [r3, #12]
|
|
8002932: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002934: f107 030c add.w r3, r7, #12
|
|
8002938: 2288 movs r2, #136 ; 0x88
|
|
800293a: 2100 movs r1, #0
|
|
800293c: 4618 mov r0, r3
|
|
800293e: f008 fb1b bl 800af78 <memset>
|
|
if(hrtc->Instance==RTC)
|
|
8002942: 687b ldr r3, [r7, #4]
|
|
8002944: 681a ldr r2, [r3, #0]
|
|
8002946: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
800294a: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800294e: 429a cmp r2, r3
|
|
8002950: d153 bne.n 80029fa <HAL_RTC_MspInit+0xde>
|
|
/* USER CODE BEGIN RTC_MspInit 0 */
|
|
|
|
/* USER CODE END RTC_MspInit 0 */
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
|
8002952: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8002956: 60fb str r3, [r7, #12]
|
|
PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
|
8002958: f44f 7380 mov.w r3, #256 ; 0x100
|
|
800295c: f8c7 3090 str.w r3, [r7, #144] ; 0x90
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002960: f107 030c add.w r3, r7, #12
|
|
8002964: 4618 mov r0, r3
|
|
8002966: f006 fa41 bl 8008dec <HAL_RCCEx_PeriphCLKConfig>
|
|
800296a: 4603 mov r3, r0
|
|
800296c: 2b00 cmp r3, #0
|
|
800296e: d001 beq.n 8002974 <HAL_RTC_MspInit+0x58>
|
|
{
|
|
Error_Handler();
|
|
8002970: f7ff fe1c bl 80025ac <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_RTC_ENABLE();
|
|
8002974: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002978: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800297c: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8002980: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002984: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002988: f442 4200 orr.w r2, r2, #32768 ; 0x8000
|
|
800298c: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8002990: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002994: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002998: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
800299a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800299e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80029a2: f042 0202 orr.w r2, r2, #2
|
|
80029a6: 64da str r2, [r3, #76] ; 0x4c
|
|
80029a8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80029ac: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80029b0: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
80029b2: f003 0302 and.w r3, r3, #2
|
|
80029b6: 60bb str r3, [r7, #8]
|
|
80029b8: 68bb ldr r3, [r7, #8]
|
|
/**RTC GPIO Configuration
|
|
PB2 ------> RTC_OUT_CALIB
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
80029ba: 2304 movs r3, #4
|
|
80029bc: f8c7 3094 str.w r3, [r7, #148] ; 0x94
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80029c0: 2302 movs r3, #2
|
|
80029c2: f8c7 3098 str.w r3, [r7, #152] ; 0x98
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80029c6: 2300 movs r3, #0
|
|
80029c8: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80029cc: 2300 movs r3, #0
|
|
80029ce: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
|
GPIO_InitStruct.Alternate = GPIO_AF0_RTC_50Hz;
|
|
80029d2: 2300 movs r3, #0
|
|
80029d4: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80029d8: f107 0394 add.w r3, r7, #148 ; 0x94
|
|
80029dc: 4619 mov r1, r3
|
|
80029de: f44f 6080 mov.w r0, #1024 ; 0x400
|
|
80029e2: f6c4 0000 movt r0, #18432 ; 0x4800
|
|
80029e6: f004 f9d8 bl 8006d9a <HAL_GPIO_Init>
|
|
|
|
/* RTC interrupt Init */
|
|
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 0, 0);
|
|
80029ea: 2200 movs r2, #0
|
|
80029ec: 2100 movs r1, #0
|
|
80029ee: 2003 movs r0, #3
|
|
80029f0: f003 fdb3 bl 800655a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
|
|
80029f4: 2003 movs r0, #3
|
|
80029f6: f003 fdcc bl 8006592 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN RTC_MspInit 1 */
|
|
|
|
/* USER CODE END RTC_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
80029fa: bf00 nop
|
|
80029fc: 37a8 adds r7, #168 ; 0xa8
|
|
80029fe: 46bd mov sp, r7
|
|
8002a00: bd80 pop {r7, pc}
|
|
|
|
08002a02 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8002a02: b580 push {r7, lr}
|
|
8002a04: b0ae sub sp, #184 ; 0xb8
|
|
8002a06: af00 add r7, sp, #0
|
|
8002a08: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002a0a: f107 03a4 add.w r3, r7, #164 ; 0xa4
|
|
8002a0e: 2200 movs r2, #0
|
|
8002a10: 601a str r2, [r3, #0]
|
|
8002a12: 605a str r2, [r3, #4]
|
|
8002a14: 609a str r2, [r3, #8]
|
|
8002a16: 60da str r2, [r3, #12]
|
|
8002a18: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002a1a: f107 031c add.w r3, r7, #28
|
|
8002a1e: 2288 movs r2, #136 ; 0x88
|
|
8002a20: 2100 movs r1, #0
|
|
8002a22: 4618 mov r0, r3
|
|
8002a24: f008 faa8 bl 800af78 <memset>
|
|
if(huart->Instance==UART5)
|
|
8002a28: 687b ldr r3, [r7, #4]
|
|
8002a2a: 681a ldr r2, [r3, #0]
|
|
8002a2c: f44f 43a0 mov.w r3, #20480 ; 0x5000
|
|
8002a30: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8002a34: 429a cmp r2, r3
|
|
8002a36: f040 8087 bne.w 8002b48 <HAL_UART_MspInit+0x146>
|
|
/* USER CODE BEGIN UART5_MspInit 0 */
|
|
|
|
/* USER CODE END UART5_MspInit 0 */
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART5;
|
|
8002a3a: 2310 movs r3, #16
|
|
8002a3c: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1;
|
|
8002a3e: 2300 movs r3, #0
|
|
8002a40: 667b str r3, [r7, #100] ; 0x64
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002a42: f107 031c add.w r3, r7, #28
|
|
8002a46: 4618 mov r0, r3
|
|
8002a48: f006 f9d0 bl 8008dec <HAL_RCCEx_PeriphCLKConfig>
|
|
8002a4c: 4603 mov r3, r0
|
|
8002a4e: 2b00 cmp r3, #0
|
|
8002a50: d001 beq.n 8002a56 <HAL_UART_MspInit+0x54>
|
|
{
|
|
Error_Handler();
|
|
8002a52: f7ff fdab bl 80025ac <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_UART5_CLK_ENABLE();
|
|
8002a56: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002a5a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002a5e: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8002a60: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002a64: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002a68: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
8002a6c: 659a str r2, [r3, #88] ; 0x58
|
|
8002a6e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002a72: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002a76: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8002a78: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
8002a7c: 61bb str r3, [r7, #24]
|
|
8002a7e: 69bb ldr r3, [r7, #24]
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8002a80: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002a84: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002a88: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8002a8a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002a8e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002a92: f042 0204 orr.w r2, r2, #4
|
|
8002a96: 64da str r2, [r3, #76] ; 0x4c
|
|
8002a98: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002a9c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002aa0: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
8002aa2: f003 0304 and.w r3, r3, #4
|
|
8002aa6: 617b str r3, [r7, #20]
|
|
8002aa8: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8002aaa: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002aae: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002ab2: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8002ab4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002ab8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002abc: f042 0208 orr.w r2, r2, #8
|
|
8002ac0: 64da str r2, [r3, #76] ; 0x4c
|
|
8002ac2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002ac6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002aca: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
8002acc: f003 0308 and.w r3, r3, #8
|
|
8002ad0: 613b str r3, [r7, #16]
|
|
8002ad2: 693b ldr r3, [r7, #16]
|
|
/**UART5 GPIO Configuration
|
|
PC12 ------> UART5_TX
|
|
PD2 ------> UART5_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_12;
|
|
8002ad4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002ad8: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002adc: 2302 movs r3, #2
|
|
8002ade: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002ae2: 2300 movs r3, #0
|
|
8002ae4: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002ae8: 2303 movs r3, #3
|
|
8002aea: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
8002aee: 2308 movs r3, #8
|
|
8002af0: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8002af4: f107 03a4 add.w r3, r7, #164 ; 0xa4
|
|
8002af8: 4619 mov r1, r3
|
|
8002afa: f44f 6000 mov.w r0, #2048 ; 0x800
|
|
8002afe: f6c4 0000 movt r0, #18432 ; 0x4800
|
|
8002b02: f004 f94a bl 8006d9a <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
8002b06: 2304 movs r3, #4
|
|
8002b08: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002b0c: 2302 movs r3, #2
|
|
8002b0e: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002b12: 2300 movs r3, #0
|
|
8002b14: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002b18: 2303 movs r3, #3
|
|
8002b1a: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
|
|
8002b1e: 2308 movs r3, #8
|
|
8002b20: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8002b24: f107 03a4 add.w r3, r7, #164 ; 0xa4
|
|
8002b28: 4619 mov r1, r3
|
|
8002b2a: f44f 6040 mov.w r0, #3072 ; 0xc00
|
|
8002b2e: f6c4 0000 movt r0, #18432 ; 0x4800
|
|
8002b32: f004 f932 bl 8006d9a <HAL_GPIO_Init>
|
|
|
|
/* UART5 interrupt Init */
|
|
HAL_NVIC_SetPriority(UART5_IRQn, 0, 0);
|
|
8002b36: 2200 movs r2, #0
|
|
8002b38: 2100 movs r1, #0
|
|
8002b3a: 2035 movs r0, #53 ; 0x35
|
|
8002b3c: f003 fd0d bl 800655a <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(UART5_IRQn);
|
|
8002b40: 2035 movs r0, #53 ; 0x35
|
|
8002b42: f003 fd26 bl 8006592 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8002b46: e055 b.n 8002bf4 <HAL_UART_MspInit+0x1f2>
|
|
else if(huart->Instance==USART2)
|
|
8002b48: 687b ldr r3, [r7, #4]
|
|
8002b4a: 681a ldr r2, [r3, #0]
|
|
8002b4c: f44f 4388 mov.w r3, #17408 ; 0x4400
|
|
8002b50: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8002b54: 429a cmp r2, r3
|
|
8002b56: d14d bne.n 8002bf4 <HAL_UART_MspInit+0x1f2>
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
|
|
8002b58: 2302 movs r3, #2
|
|
8002b5a: 61fb str r3, [r7, #28]
|
|
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
|
|
8002b5c: 2300 movs r3, #0
|
|
8002b5e: 65bb str r3, [r7, #88] ; 0x58
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002b60: f107 031c add.w r3, r7, #28
|
|
8002b64: 4618 mov r0, r3
|
|
8002b66: f006 f941 bl 8008dec <HAL_RCCEx_PeriphCLKConfig>
|
|
8002b6a: 4603 mov r3, r0
|
|
8002b6c: 2b00 cmp r3, #0
|
|
8002b6e: d001 beq.n 8002b74 <HAL_UART_MspInit+0x172>
|
|
Error_Handler();
|
|
8002b70: f7ff fd1c bl 80025ac <Error_Handler>
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
8002b74: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002b78: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002b7c: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8002b7e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002b82: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002b86: f442 3200 orr.w r2, r2, #131072 ; 0x20000
|
|
8002b8a: 659a str r2, [r3, #88] ; 0x58
|
|
8002b8c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002b90: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002b94: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8002b96: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8002b9a: 60fb str r3, [r7, #12]
|
|
8002b9c: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002b9e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002ba2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002ba6: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8002ba8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002bac: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002bb0: f042 0201 orr.w r2, r2, #1
|
|
8002bb4: 64da str r2, [r3, #76] ; 0x4c
|
|
8002bb6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002bba: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8002bbe: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
8002bc0: f003 0301 and.w r3, r3, #1
|
|
8002bc4: 60bb str r3, [r7, #8]
|
|
8002bc6: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
|
|
8002bc8: 230c movs r3, #12
|
|
8002bca: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002bce: 2302 movs r3, #2
|
|
8002bd0: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002bd4: 2300 movs r3, #0
|
|
8002bd6: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002bda: 2303 movs r3, #3
|
|
8002bdc: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
|
8002be0: 2307 movs r3, #7
|
|
8002be2: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002be6: f107 03a4 add.w r3, r7, #164 ; 0xa4
|
|
8002bea: 4619 mov r1, r3
|
|
8002bec: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
|
|
8002bf0: f004 f8d3 bl 8006d9a <HAL_GPIO_Init>
|
|
}
|
|
8002bf4: bf00 nop
|
|
8002bf6: 37b8 adds r7, #184 ; 0xb8
|
|
8002bf8: 46bd mov sp, r7
|
|
8002bfa: bd80 pop {r7, pc}
|
|
|
|
08002bfc <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8002bfc: b480 push {r7}
|
|
8002bfe: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8002c00: e7fe b.n 8002c00 <NMI_Handler+0x4>
|
|
|
|
08002c02 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8002c02: b480 push {r7}
|
|
8002c04: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8002c06: e7fe b.n 8002c06 <HardFault_Handler+0x4>
|
|
|
|
08002c08 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8002c08: b480 push {r7}
|
|
8002c0a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8002c0c: e7fe b.n 8002c0c <MemManage_Handler+0x4>
|
|
|
|
08002c0e <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8002c0e: b480 push {r7}
|
|
8002c10: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8002c12: e7fe b.n 8002c12 <BusFault_Handler+0x4>
|
|
|
|
08002c14 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8002c14: b480 push {r7}
|
|
8002c16: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8002c18: e7fe b.n 8002c18 <UsageFault_Handler+0x4>
|
|
|
|
08002c1a <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
8002c1a: b480 push {r7}
|
|
8002c1c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8002c1e: bf00 nop
|
|
8002c20: 46bd mov sp, r7
|
|
8002c22: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002c26: 4770 bx lr
|
|
|
|
08002c28 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8002c28: b480 push {r7}
|
|
8002c2a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8002c2c: bf00 nop
|
|
8002c2e: 46bd mov sp, r7
|
|
8002c30: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002c34: 4770 bx lr
|
|
|
|
08002c36 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8002c36: b480 push {r7}
|
|
8002c38: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
8002c3a: bf00 nop
|
|
8002c3c: 46bd mov sp, r7
|
|
8002c3e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002c42: 4770 bx lr
|
|
|
|
08002c44 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8002c44: b580 push {r7, lr}
|
|
8002c46: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
8002c48: f001 fec7 bl 80049da <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
8002c4c: bf00 nop
|
|
8002c4e: bd80 pop {r7, pc}
|
|
|
|
08002c50 <RTC_WKUP_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles RTC wake-up interrupt through EXTI line 20.
|
|
*/
|
|
void RTC_WKUP_IRQHandler(void)
|
|
{
|
|
8002c50: b580 push {r7, lr}
|
|
8002c52: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN RTC_WKUP_IRQn 0 */
|
|
|
|
/* USER CODE END RTC_WKUP_IRQn 0 */
|
|
HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc);
|
|
8002c54: f640 1078 movw r0, #2424 ; 0x978
|
|
8002c58: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002c5c: f007 f897 bl 8009d8e <HAL_RTCEx_WakeUpTimerIRQHandler>
|
|
/* USER CODE BEGIN RTC_WKUP_IRQn 1 */
|
|
|
|
/* USER CODE END RTC_WKUP_IRQn 1 */
|
|
}
|
|
8002c60: bf00 nop
|
|
8002c62: bd80 pop {r7, pc}
|
|
|
|
08002c64 <UART5_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles UART5 global interrupt.
|
|
*/
|
|
void UART5_IRQHandler(void)
|
|
{
|
|
8002c64: b580 push {r7, lr}
|
|
8002c66: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UART5_IRQn 0 */
|
|
|
|
/* USER CODE END UART5_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart5);
|
|
8002c68: f640 0090 movw r0, #2192 ; 0x890
|
|
8002c6c: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002c70: f007 faad bl 800a1ce <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN UART5_IRQn 1 */
|
|
|
|
/* USER CODE END UART5_IRQn 1 */
|
|
}
|
|
8002c74: bf00 nop
|
|
8002c76: bd80 pop {r7, pc}
|
|
|
|
08002c78 <Bme680Sensors_Read>:
|
|
}
|
|
/* USER CODE END EnvSensors_Init */
|
|
|
|
|
|
HAL_StatusTypeDef Bme680Sensors_Read(sensor_t *sensor_data)
|
|
{
|
|
8002c78: b580 push {r7, lr}
|
|
8002c7a: b082 sub sp, #8
|
|
8002c7c: af00 add r7, sp, #0
|
|
8002c7e: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN EnvSensors_Read */
|
|
gas_Sensor_Read_data(&bme_gas_sensor,sensor_data);
|
|
8002c80: 6879 ldr r1, [r7, #4]
|
|
8002c82: f640 2020 movw r0, #2592 ; 0xa20
|
|
8002c86: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002c8a: f001 fd92 bl 80047b2 <gas_Sensor_Read_data>
|
|
|
|
return HAL_OK;
|
|
8002c8e: 2300 movs r3, #0
|
|
/* USER CODE END EnvSensors_Read */
|
|
}
|
|
8002c90: 4618 mov r0, r3
|
|
8002c92: 3708 adds r7, #8
|
|
8002c94: 46bd mov sp, r7
|
|
8002c96: bd80 pop {r7, pc}
|
|
|
|
08002c98 <Bme680Sensors_Init>:
|
|
|
|
|
|
HAL_StatusTypeDef Bme680Sensors_Init(void)
|
|
{
|
|
8002c98: b580 push {r7, lr}
|
|
8002c9a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN Bme682Sensors_Init */
|
|
if(gas_Sensor_Init(&bme_gas_sensor))
|
|
8002c9c: f640 2020 movw r0, #2592 ; 0xa20
|
|
8002ca0: f2c2 0000 movt r0, #8192 ; 0x2000
|
|
8002ca4: f001 fd58 bl 8004758 <gas_Sensor_Init>
|
|
8002ca8: 4603 mov r3, r0
|
|
8002caa: 2b00 cmp r3, #0
|
|
8002cac: d001 beq.n 8002cb2 <Bme680Sensors_Init+0x1a>
|
|
{
|
|
return HAL_ERROR;
|
|
8002cae: 2301 movs r3, #1
|
|
8002cb0: e000 b.n 8002cb4 <Bme680Sensors_Init+0x1c>
|
|
}
|
|
|
|
/* USER CODE END Bme682Sensors_Init*/
|
|
|
|
return HAL_OK;
|
|
8002cb2: 2300 movs r3, #0
|
|
}
|
|
8002cb4: 4618 mov r0, r3
|
|
8002cb6: bd80 pop {r7, pc}
|
|
|
|
08002cb8 <NTCRead>:
|
|
sensor_data->scale.wzs=2.35198355;
|
|
}
|
|
|
|
|
|
HAL_StatusTypeDef NTCRead(ADC_HandleTypeDef *hadc,sensor_t *sensor_data)
|
|
{
|
|
8002cb8: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr}
|
|
8002cbc: b086 sub sp, #24
|
|
8002cbe: af00 add r7, sp, #0
|
|
8002cc0: 6078 str r0, [r7, #4]
|
|
8002cc2: 6039 str r1, [r7, #0]
|
|
uint16_t temp_adc=0;
|
|
8002cc4: 2300 movs r3, #0
|
|
8002cc6: 82fb strh r3, [r7, #22]
|
|
uint16_t hum_adc=0;
|
|
8002cc8: 2300 movs r3, #0
|
|
8002cca: 82bb strh r3, [r7, #20]
|
|
HAL_Delay(100);
|
|
8002ccc: 2064 movs r0, #100 ; 0x64
|
|
8002cce: f001 fea8 bl 8004a22 <HAL_Delay>
|
|
|
|
for(int i=0;i<16;i++)
|
|
8002cd2: 2300 movs r3, #0
|
|
8002cd4: 613b str r3, [r7, #16]
|
|
8002cd6: e020 b.n 8002d1a <NTCRead+0x62>
|
|
{
|
|
HAL_ADC_Start( hadc);
|
|
8002cd8: 6878 ldr r0, [r7, #4]
|
|
8002cda: f002 fa7b bl 80051d4 <HAL_ADC_Start>
|
|
|
|
HAL_Delay(100);
|
|
8002cde: 2064 movs r0, #100 ; 0x64
|
|
8002ce0: f001 fe9f bl 8004a22 <HAL_Delay>
|
|
|
|
HAL_ADC_PollForConversion( hadc, 1000 );
|
|
8002ce4: f44f 717a mov.w r1, #1000 ; 0x3e8
|
|
8002ce8: 6878 ldr r0, [r7, #4]
|
|
8002cea: f002 fb6c bl 80053c6 <HAL_ADC_PollForConversion>
|
|
|
|
temp_adc += HAL_ADC_GetValue ( hadc);
|
|
8002cee: 6878 ldr r0, [r7, #4]
|
|
8002cf0: f002 fc4a bl 8005588 <HAL_ADC_GetValue>
|
|
8002cf4: 4603 mov r3, r0
|
|
8002cf6: b29a uxth r2, r3
|
|
8002cf8: 8afb ldrh r3, [r7, #22]
|
|
8002cfa: 4413 add r3, r2
|
|
8002cfc: 82fb strh r3, [r7, #22]
|
|
|
|
hum_adc+=HAL_ADC_GetValue ( hadc);
|
|
8002cfe: 6878 ldr r0, [r7, #4]
|
|
8002d00: f002 fc42 bl 8005588 <HAL_ADC_GetValue>
|
|
8002d04: 4603 mov r3, r0
|
|
8002d06: b29a uxth r2, r3
|
|
8002d08: 8abb ldrh r3, [r7, #20]
|
|
8002d0a: 4413 add r3, r2
|
|
8002d0c: 82bb strh r3, [r7, #20]
|
|
HAL_ADC_Stop(hadc);
|
|
8002d0e: 6878 ldr r0, [r7, #4]
|
|
8002d10: f002 fb26 bl 8005360 <HAL_ADC_Stop>
|
|
for(int i=0;i<16;i++)
|
|
8002d14: 693b ldr r3, [r7, #16]
|
|
8002d16: 3301 adds r3, #1
|
|
8002d18: 613b str r3, [r7, #16]
|
|
8002d1a: 693b ldr r3, [r7, #16]
|
|
8002d1c: 2b0f cmp r3, #15
|
|
8002d1e: dddb ble.n 8002cd8 <NTCRead+0x20>
|
|
}
|
|
|
|
|
|
temp_adc/=16;
|
|
8002d20: 8afb ldrh r3, [r7, #22]
|
|
8002d22: 091b lsrs r3, r3, #4
|
|
8002d24: 82fb strh r3, [r7, #22]
|
|
hum_adc/=16;
|
|
8002d26: 8abb ldrh r3, [r7, #20]
|
|
8002d28: 091b lsrs r3, r3, #4
|
|
8002d2a: 82bb strh r3, [r7, #20]
|
|
uint16_t vTemp=(temp_adc*3300)/1023;
|
|
8002d2c: 8afb ldrh r3, [r7, #22]
|
|
8002d2e: f640 42e4 movw r2, #3300 ; 0xce4
|
|
8002d32: fb02 f303 mul.w r3, r2, r3
|
|
8002d36: f640 0203 movw r2, #2051 ; 0x803
|
|
8002d3a: f2c8 0220 movt r2, #32800 ; 0x8020
|
|
8002d3e: fb82 1203 smull r1, r2, r2, r3
|
|
8002d42: 441a add r2, r3
|
|
8002d44: 1252 asrs r2, r2, #9
|
|
8002d46: 17db asrs r3, r3, #31
|
|
8002d48: 1ad3 subs r3, r2, r3
|
|
8002d4a: 81fb strh r3, [r7, #14]
|
|
uint16_t vHum=(hum_adc*3300)/1023;
|
|
8002d4c: 8abb ldrh r3, [r7, #20]
|
|
8002d4e: f640 42e4 movw r2, #3300 ; 0xce4
|
|
8002d52: fb02 f303 mul.w r3, r2, r3
|
|
8002d56: f640 0203 movw r2, #2051 ; 0x803
|
|
8002d5a: f2c8 0220 movt r2, #32800 ; 0x8020
|
|
8002d5e: fb82 1203 smull r1, r2, r2, r3
|
|
8002d62: 441a add r2, r3
|
|
8002d64: 1252 asrs r2, r2, #9
|
|
8002d66: 17db asrs r3, r3, #31
|
|
8002d68: 1ad3 subs r3, r2, r3
|
|
8002d6a: 81bb strh r3, [r7, #12]
|
|
|
|
// sensor_data->ntc_temp_adc=vTemp;
|
|
// sensor_data->ntc_hum_adc=vHum;
|
|
sensor_data->ntc_temp_resistance=(vTemp*10000)/(5000-vTemp); //la sonde est alimentée en 5V
|
|
8002d6c: 89fb ldrh r3, [r7, #14]
|
|
8002d6e: f242 7210 movw r2, #10000 ; 0x2710
|
|
8002d72: fb02 f203 mul.w r2, r2, r3
|
|
8002d76: 89fb ldrh r3, [r7, #14]
|
|
8002d78: f5c3 539c rsb r3, r3, #4992 ; 0x1380
|
|
8002d7c: 3308 adds r3, #8
|
|
8002d7e: fb92 f3f3 sdiv r3, r2, r3
|
|
8002d82: 461a mov r2, r3
|
|
8002d84: 683b ldr r3, [r7, #0]
|
|
8002d86: 619a str r2, [r3, #24]
|
|
float ln=log(sensor_data->ntc_temp_resistance);
|
|
8002d88: 683b ldr r3, [r7, #0]
|
|
8002d8a: 699b ldr r3, [r3, #24]
|
|
8002d8c: 4618 mov r0, r3
|
|
8002d8e: f7fd fbb9 bl 8000504 <__aeabi_ui2d>
|
|
8002d92: 4602 mov r2, r0
|
|
8002d94: 460b mov r3, r1
|
|
8002d96: ec43 2b10 vmov d0, r2, r3
|
|
8002d9a: f00b f825 bl 800dde8 <log>
|
|
8002d9e: ec53 2b10 vmov r2, r3, d0
|
|
8002da2: 4610 mov r0, r2
|
|
8002da4: 4619 mov r1, r3
|
|
8002da6: f7fd feff bl 8000ba8 <__aeabi_d2f>
|
|
8002daa: 4603 mov r3, r0
|
|
8002dac: 60bb str r3, [r7, #8]
|
|
sensor_data->ntc_temp=(1/(COEFF_A+(COEFF_B*ln)+(COEFF_C*ln*ln*ln)))-273;
|
|
8002dae: 68b8 ldr r0, [r7, #8]
|
|
8002db0: f7fd fbca bl 8000548 <__aeabi_f2d>
|
|
8002db4: f648 120c movw r2, #35084 ; 0x890c
|
|
8002db8: f6c8 7262 movt r2, #36706 ; 0x8f62
|
|
8002dbc: f64d 43dc movw r3, #56540 ; 0xdcdc
|
|
8002dc0: f6c3 7330 movt r3, #16176 ; 0x3f30
|
|
8002dc4: f7fd fc18 bl 80005f8 <__aeabi_dmul>
|
|
8002dc8: 4602 mov r2, r0
|
|
8002dca: 460b mov r3, r1
|
|
8002dcc: 4610 mov r0, r2
|
|
8002dce: 4619 mov r1, r3
|
|
8002dd0: f647 3218 movw r2, #31512 ; 0x7b18
|
|
8002dd4: f2cf 7209 movt r2, #63241 ; 0xf709
|
|
8002dd8: f240 33c5 movw r3, #965 ; 0x3c5
|
|
8002ddc: f6c3 734c movt r3, #16204 ; 0x3f4c
|
|
8002de0: f7fd fa54 bl 800028c <__adddf3>
|
|
8002de4: 4602 mov r2, r0
|
|
8002de6: 460b mov r3, r1
|
|
8002de8: 4614 mov r4, r2
|
|
8002dea: 461d mov r5, r3
|
|
8002dec: 68b8 ldr r0, [r7, #8]
|
|
8002dee: f7fd fbab bl 8000548 <__aeabi_f2d>
|
|
8002df2: f64e 129c movw r2, #59804 ; 0xe99c
|
|
8002df6: f6c4 7296 movt r2, #20374 ; 0x4f96
|
|
8002dfa: f44f 5348 mov.w r3, #12800 ; 0x3200
|
|
8002dfe: f6c3 6386 movt r3, #16006 ; 0x3e86
|
|
8002e02: f7fd fbf9 bl 80005f8 <__aeabi_dmul>
|
|
8002e06: 4602 mov r2, r0
|
|
8002e08: 460b mov r3, r1
|
|
8002e0a: 4690 mov r8, r2
|
|
8002e0c: 4699 mov r9, r3
|
|
8002e0e: 68b8 ldr r0, [r7, #8]
|
|
8002e10: f7fd fb9a bl 8000548 <__aeabi_f2d>
|
|
8002e14: 4602 mov r2, r0
|
|
8002e16: 460b mov r3, r1
|
|
8002e18: 4640 mov r0, r8
|
|
8002e1a: 4649 mov r1, r9
|
|
8002e1c: f7fd fbec bl 80005f8 <__aeabi_dmul>
|
|
8002e20: 4602 mov r2, r0
|
|
8002e22: 460b mov r3, r1
|
|
8002e24: 4690 mov r8, r2
|
|
8002e26: 4699 mov r9, r3
|
|
8002e28: 68b8 ldr r0, [r7, #8]
|
|
8002e2a: f7fd fb8d bl 8000548 <__aeabi_f2d>
|
|
8002e2e: 4602 mov r2, r0
|
|
8002e30: 460b mov r3, r1
|
|
8002e32: 4640 mov r0, r8
|
|
8002e34: 4649 mov r1, r9
|
|
8002e36: f7fd fbdf bl 80005f8 <__aeabi_dmul>
|
|
8002e3a: 4602 mov r2, r0
|
|
8002e3c: 460b mov r3, r1
|
|
8002e3e: 4620 mov r0, r4
|
|
8002e40: 4629 mov r1, r5
|
|
8002e42: f7fd fa23 bl 800028c <__adddf3>
|
|
8002e46: 4602 mov r2, r0
|
|
8002e48: 460b mov r3, r1
|
|
8002e4a: f04f 0000 mov.w r0, #0
|
|
8002e4e: f04f 0100 mov.w r1, #0
|
|
8002e52: f6c3 71f0 movt r1, #16368 ; 0x3ff0
|
|
8002e56: f7fd fcf9 bl 800084c <__aeabi_ddiv>
|
|
8002e5a: 4602 mov r2, r0
|
|
8002e5c: 460b mov r3, r1
|
|
8002e5e: 4610 mov r0, r2
|
|
8002e60: 4619 mov r1, r3
|
|
8002e62: f04f 0200 mov.w r2, #0
|
|
8002e66: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8002e6a: f2c4 0371 movt r3, #16497 ; 0x4071
|
|
8002e6e: f7fd fa0b bl 8000288 <__aeabi_dsub>
|
|
8002e72: 4602 mov r2, r0
|
|
8002e74: 460b mov r3, r1
|
|
8002e76: 4610 mov r0, r2
|
|
8002e78: 4619 mov r1, r3
|
|
8002e7a: f7fd fe95 bl 8000ba8 <__aeabi_d2f>
|
|
8002e7e: 4602 mov r2, r0
|
|
8002e80: 683b ldr r3, [r7, #0]
|
|
8002e82: 61da str r2, [r3, #28]
|
|
sensor_data->ntc_humidity=0.0375 * vHum- 37.7;
|
|
8002e84: 89bb ldrh r3, [r7, #12]
|
|
8002e86: 4618 mov r0, r3
|
|
8002e88: f7fd fb4c bl 8000524 <__aeabi_i2d>
|
|
8002e8c: f04f 3233 mov.w r2, #858993459 ; 0x33333333
|
|
8002e90: f243 3333 movw r3, #13107 ; 0x3333
|
|
8002e94: f6c3 73a3 movt r3, #16291 ; 0x3fa3
|
|
8002e98: f7fd fbae bl 80005f8 <__aeabi_dmul>
|
|
8002e9c: 4602 mov r2, r0
|
|
8002e9e: 460b mov r3, r1
|
|
8002ea0: 4610 mov r0, r2
|
|
8002ea2: 4619 mov r1, r3
|
|
8002ea4: f649 129a movw r2, #39322 ; 0x999a
|
|
8002ea8: f6c9 1299 movt r2, #39321 ; 0x9999
|
|
8002eac: f64d 1399 movw r3, #55705 ; 0xd999
|
|
8002eb0: f2c4 0342 movt r3, #16450 ; 0x4042
|
|
8002eb4: f7fd f9e8 bl 8000288 <__aeabi_dsub>
|
|
8002eb8: 4602 mov r2, r0
|
|
8002eba: 460b mov r3, r1
|
|
8002ebc: 4610 mov r0, r2
|
|
8002ebe: 4619 mov r1, r3
|
|
8002ec0: f7fd fe72 bl 8000ba8 <__aeabi_d2f>
|
|
8002ec4: 4602 mov r2, r0
|
|
8002ec6: 683b ldr r3, [r7, #0]
|
|
8002ec8: 621a str r2, [r3, #32]
|
|
|
|
|
|
return HAL_OK;
|
|
8002eca: 2300 movs r3, #0
|
|
|
|
|
|
|
|
}
|
|
8002ecc: 4618 mov r0, r3
|
|
8002ece: 3718 adds r7, #24
|
|
8002ed0: 46bd mov sp, r7
|
|
8002ed2: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc}
|
|
|
|
08002ed6 <_getpid>:
|
|
void initialise_monitor_handles()
|
|
{
|
|
}
|
|
|
|
int _getpid(void)
|
|
{
|
|
8002ed6: b480 push {r7}
|
|
8002ed8: af00 add r7, sp, #0
|
|
return 1;
|
|
8002eda: 2301 movs r3, #1
|
|
}
|
|
8002edc: 4618 mov r0, r3
|
|
8002ede: 46bd mov sp, r7
|
|
8002ee0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002ee4: 4770 bx lr
|
|
|
|
08002ee6 <_kill>:
|
|
|
|
int _kill(int pid, int sig)
|
|
{
|
|
8002ee6: b580 push {r7, lr}
|
|
8002ee8: b082 sub sp, #8
|
|
8002eea: af00 add r7, sp, #0
|
|
8002eec: 6078 str r0, [r7, #4]
|
|
8002eee: 6039 str r1, [r7, #0]
|
|
errno = EINVAL;
|
|
8002ef0: f008 f80a bl 800af08 <__errno>
|
|
8002ef4: 4603 mov r3, r0
|
|
8002ef6: 2216 movs r2, #22
|
|
8002ef8: 601a str r2, [r3, #0]
|
|
return -1;
|
|
8002efa: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
|
|
}
|
|
8002efe: 4618 mov r0, r3
|
|
8002f00: 3708 adds r7, #8
|
|
8002f02: 46bd mov sp, r7
|
|
8002f04: bd80 pop {r7, pc}
|
|
|
|
08002f06 <_exit>:
|
|
|
|
void _exit (int status)
|
|
{
|
|
8002f06: b580 push {r7, lr}
|
|
8002f08: b082 sub sp, #8
|
|
8002f0a: af00 add r7, sp, #0
|
|
8002f0c: 6078 str r0, [r7, #4]
|
|
_kill(status, -1);
|
|
8002f0e: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
|
|
8002f12: 6878 ldr r0, [r7, #4]
|
|
8002f14: f7ff ffe7 bl 8002ee6 <_kill>
|
|
while (1) {} /* Make sure we hang here */
|
|
8002f18: e7fe b.n 8002f18 <_exit+0x12>
|
|
|
|
08002f1a <_read>:
|
|
}
|
|
|
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
|
{
|
|
8002f1a: b580 push {r7, lr}
|
|
8002f1c: b086 sub sp, #24
|
|
8002f1e: af00 add r7, sp, #0
|
|
8002f20: 60f8 str r0, [r7, #12]
|
|
8002f22: 60b9 str r1, [r7, #8]
|
|
8002f24: 607a str r2, [r7, #4]
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002f26: 2300 movs r3, #0
|
|
8002f28: 617b str r3, [r7, #20]
|
|
8002f2a: e00a b.n 8002f42 <_read+0x28>
|
|
{
|
|
*ptr++ = __io_getchar();
|
|
8002f2c: f3af 8000 nop.w
|
|
8002f30: 4601 mov r1, r0
|
|
8002f32: 68bb ldr r3, [r7, #8]
|
|
8002f34: 1c5a adds r2, r3, #1
|
|
8002f36: 60ba str r2, [r7, #8]
|
|
8002f38: b2ca uxtb r2, r1
|
|
8002f3a: 701a strb r2, [r3, #0]
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002f3c: 697b ldr r3, [r7, #20]
|
|
8002f3e: 3301 adds r3, #1
|
|
8002f40: 617b str r3, [r7, #20]
|
|
8002f42: 697a ldr r2, [r7, #20]
|
|
8002f44: 687b ldr r3, [r7, #4]
|
|
8002f46: 429a cmp r2, r3
|
|
8002f48: dbf0 blt.n 8002f2c <_read+0x12>
|
|
}
|
|
|
|
return len;
|
|
8002f4a: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002f4c: 4618 mov r0, r3
|
|
8002f4e: 3718 adds r7, #24
|
|
8002f50: 46bd mov sp, r7
|
|
8002f52: bd80 pop {r7, pc}
|
|
|
|
08002f54 <_close>:
|
|
}
|
|
return len;
|
|
}
|
|
|
|
int _close(int file)
|
|
{
|
|
8002f54: b480 push {r7}
|
|
8002f56: b083 sub sp, #12
|
|
8002f58: af00 add r7, sp, #0
|
|
8002f5a: 6078 str r0, [r7, #4]
|
|
return -1;
|
|
8002f5c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
|
|
}
|
|
8002f60: 4618 mov r0, r3
|
|
8002f62: 370c adds r7, #12
|
|
8002f64: 46bd mov sp, r7
|
|
8002f66: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002f6a: 4770 bx lr
|
|
|
|
08002f6c <_fstat>:
|
|
|
|
|
|
int _fstat(int file, struct stat *st)
|
|
{
|
|
8002f6c: b480 push {r7}
|
|
8002f6e: b083 sub sp, #12
|
|
8002f70: af00 add r7, sp, #0
|
|
8002f72: 6078 str r0, [r7, #4]
|
|
8002f74: 6039 str r1, [r7, #0]
|
|
st->st_mode = S_IFCHR;
|
|
8002f76: 683b ldr r3, [r7, #0]
|
|
8002f78: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
8002f7c: 605a str r2, [r3, #4]
|
|
return 0;
|
|
8002f7e: 2300 movs r3, #0
|
|
}
|
|
8002f80: 4618 mov r0, r3
|
|
8002f82: 370c adds r7, #12
|
|
8002f84: 46bd mov sp, r7
|
|
8002f86: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002f8a: 4770 bx lr
|
|
|
|
08002f8c <_isatty>:
|
|
|
|
int _isatty(int file)
|
|
{
|
|
8002f8c: b480 push {r7}
|
|
8002f8e: b083 sub sp, #12
|
|
8002f90: af00 add r7, sp, #0
|
|
8002f92: 6078 str r0, [r7, #4]
|
|
return 1;
|
|
8002f94: 2301 movs r3, #1
|
|
}
|
|
8002f96: 4618 mov r0, r3
|
|
8002f98: 370c adds r7, #12
|
|
8002f9a: 46bd mov sp, r7
|
|
8002f9c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002fa0: 4770 bx lr
|
|
|
|
08002fa2 <_lseek>:
|
|
|
|
int _lseek(int file, int ptr, int dir)
|
|
{
|
|
8002fa2: b480 push {r7}
|
|
8002fa4: b085 sub sp, #20
|
|
8002fa6: af00 add r7, sp, #0
|
|
8002fa8: 60f8 str r0, [r7, #12]
|
|
8002faa: 60b9 str r1, [r7, #8]
|
|
8002fac: 607a str r2, [r7, #4]
|
|
return 0;
|
|
8002fae: 2300 movs r3, #0
|
|
}
|
|
8002fb0: 4618 mov r0, r3
|
|
8002fb2: 3714 adds r7, #20
|
|
8002fb4: 46bd mov sp, r7
|
|
8002fb6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002fba: 4770 bx lr
|
|
|
|
08002fbc <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
8002fbc: b580 push {r7, lr}
|
|
8002fbe: b086 sub sp, #24
|
|
8002fc0: af00 add r7, sp, #0
|
|
8002fc2: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8002fc4: f248 0200 movw r2, #32768 ; 0x8000
|
|
8002fc8: f2c2 0201 movt r2, #8193 ; 0x2001
|
|
8002fcc: f240 4300 movw r3, #1024 ; 0x400
|
|
8002fd0: f2c0 0300 movt r3, #0
|
|
8002fd4: 1ad3 subs r3, r2, r3
|
|
8002fd6: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
8002fd8: 697b ldr r3, [r7, #20]
|
|
8002fda: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
8002fdc: f240 536c movw r3, #1388 ; 0x56c
|
|
8002fe0: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002fe4: 681b ldr r3, [r3, #0]
|
|
8002fe6: 2b00 cmp r3, #0
|
|
8002fe8: d108 bne.n 8002ffc <_sbrk+0x40>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
8002fea: f240 536c movw r3, #1388 ; 0x56c
|
|
8002fee: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8002ff2: f640 2290 movw r2, #2704 ; 0xa90
|
|
8002ff6: f2c2 0200 movt r2, #8192 ; 0x2000
|
|
8002ffa: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
8002ffc: f240 536c movw r3, #1388 ; 0x56c
|
|
8003000: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8003004: 681a ldr r2, [r3, #0]
|
|
8003006: 687b ldr r3, [r7, #4]
|
|
8003008: 4413 add r3, r2
|
|
800300a: 693a ldr r2, [r7, #16]
|
|
800300c: 429a cmp r2, r3
|
|
800300e: d207 bcs.n 8003020 <_sbrk+0x64>
|
|
{
|
|
errno = ENOMEM;
|
|
8003010: f007 ff7a bl 800af08 <__errno>
|
|
8003014: 4603 mov r3, r0
|
|
8003016: 220c movs r2, #12
|
|
8003018: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
800301a: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
|
|
800301e: e012 b.n 8003046 <_sbrk+0x8a>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
8003020: f240 536c movw r3, #1388 ; 0x56c
|
|
8003024: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8003028: 681b ldr r3, [r3, #0]
|
|
800302a: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
800302c: f240 536c movw r3, #1388 ; 0x56c
|
|
8003030: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8003034: 681a ldr r2, [r3, #0]
|
|
8003036: 687b ldr r3, [r7, #4]
|
|
8003038: 441a add r2, r3
|
|
800303a: f240 536c movw r3, #1388 ; 0x56c
|
|
800303e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8003042: 601a str r2, [r3, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
8003044: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8003046: 4618 mov r0, r3
|
|
8003048: 3718 adds r7, #24
|
|
800304a: 46bd mov sp, r7
|
|
800304c: bd80 pop {r7, pc}
|
|
|
|
0800304e <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
800304e: b480 push {r7}
|
|
8003050: af00 add r7, sp, #0
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
#endif
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
|
8003052: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8003056: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
800305a: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88
|
|
800305e: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8003062: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8003066: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000
|
|
800306a: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
#endif
|
|
|
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
|
/* Set MSION bit */
|
|
RCC->CR |= RCC_CR_MSION;
|
|
800306e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8003072: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8003076: 681a ldr r2, [r3, #0]
|
|
8003078: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800307c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8003080: f042 0201 orr.w r2, r2, #1
|
|
8003084: 601a str r2, [r3, #0]
|
|
|
|
/* Reset CFGR register */
|
|
RCC->CFGR = 0x00000000U;
|
|
8003086: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800308a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800308e: 2200 movs r2, #0
|
|
8003090: 609a str r2, [r3, #8]
|
|
|
|
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
|
RCC->CR &= 0xEAF6FFFFU;
|
|
8003092: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8003096: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800309a: 681b ldr r3, [r3, #0]
|
|
800309c: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
80030a0: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
80030a4: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000
|
|
80030a8: f423 2310 bic.w r3, r3, #589824 ; 0x90000
|
|
80030ac: 6013 str r3, [r2, #0]
|
|
|
|
/* Reset PLLCFGR register */
|
|
RCC->PLLCFGR = 0x00001000U;
|
|
80030ae: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80030b2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80030b6: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
80030ba: 60da str r2, [r3, #12]
|
|
|
|
/* Reset HSEBYP bit */
|
|
RCC->CR &= 0xFFFBFFFFU;
|
|
80030bc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80030c0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80030c4: 681a ldr r2, [r3, #0]
|
|
80030c6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80030ca: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80030ce: f422 2280 bic.w r2, r2, #262144 ; 0x40000
|
|
80030d2: 601a str r2, [r3, #0]
|
|
|
|
/* Disable all interrupts */
|
|
RCC->CIER = 0x00000000U;
|
|
80030d4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80030d8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80030dc: 2200 movs r2, #0
|
|
80030de: 619a str r2, [r3, #24]
|
|
}
|
|
80030e0: bf00 nop
|
|
80030e2: 46bd mov sp, r7
|
|
80030e4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80030e8: 4770 bx lr
|
|
|
|
080030ea <at_Com>:
|
|
#include <string.h>
|
|
#include "stdio.h"
|
|
|
|
|
|
HAL_StatusTypeDef at_Com(UART_HandleTypeDef *huart,uint8_t *p_ack,uint8_t *p_rcv, int timeout_ms,uint8_t size)
|
|
{
|
|
80030ea: b590 push {r4, r7, lr}
|
|
80030ec: b0c7 sub sp, #284 ; 0x11c
|
|
80030ee: af00 add r7, sp, #0
|
|
80030f0: f107 040c add.w r4, r7, #12
|
|
80030f4: 6020 str r0, [r4, #0]
|
|
80030f6: f107 0008 add.w r0, r7, #8
|
|
80030fa: 6001 str r1, [r0, #0]
|
|
80030fc: 1d39 adds r1, r7, #4
|
|
80030fe: 600a str r2, [r1, #0]
|
|
8003100: 463a mov r2, r7
|
|
8003102: 6013 str r3, [r2, #0]
|
|
|
|
HAL_StatusTypeDef rslt=0;
|
|
8003104: 2300 movs r3, #0
|
|
8003106: f887 3117 strb.w r3, [r7, #279] ; 0x117
|
|
uint8_t tmp[256]={0};
|
|
800310a: f107 0314 add.w r3, r7, #20
|
|
800310e: 2200 movs r2, #0
|
|
8003110: 601a str r2, [r3, #0]
|
|
8003112: 3304 adds r3, #4
|
|
8003114: 22fc movs r2, #252 ; 0xfc
|
|
8003116: 2100 movs r1, #0
|
|
8003118: 4618 mov r0, r3
|
|
800311a: f007 ff2d bl 800af78 <memset>
|
|
uint8_t i=0;
|
|
800311e: 2300 movs r3, #0
|
|
8003120: f887 3116 strb.w r3, [r7, #278] ; 0x116
|
|
|
|
if(HAL_UART_Transmit(huart,p_ack,size,timeout_ms))
|
|
8003124: f897 3128 ldrb.w r3, [r7, #296] ; 0x128
|
|
8003128: b29a uxth r2, r3
|
|
800312a: 463b mov r3, r7
|
|
800312c: 681b ldr r3, [r3, #0]
|
|
800312e: f107 0108 add.w r1, r7, #8
|
|
8003132: f107 000c add.w r0, r7, #12
|
|
8003136: 6809 ldr r1, [r1, #0]
|
|
8003138: 6800 ldr r0, [r0, #0]
|
|
800313a: f006 fee3 bl 8009f04 <HAL_UART_Transmit>
|
|
800313e: 4603 mov r3, r0
|
|
8003140: 2b00 cmp r3, #0
|
|
8003142: d007 beq.n 8003154 <at_Com+0x6a>
|
|
{
|
|
rslt= huart->ErrorCode;
|
|
8003144: f107 030c add.w r3, r7, #12
|
|
8003148: 681b ldr r3, [r3, #0]
|
|
800314a: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800314e: f887 3117 strb.w r3, [r7, #279] ; 0x117
|
|
8003152: e034 b.n 80031be <at_Com+0xd4>
|
|
}
|
|
else
|
|
{
|
|
do
|
|
{
|
|
rslt=HAL_UART_Receive(huart,& tmp[i], 1, timeout_ms);
|
|
8003154: f897 3116 ldrb.w r3, [r7, #278] ; 0x116
|
|
8003158: f107 0214 add.w r2, r7, #20
|
|
800315c: 18d1 adds r1, r2, r3
|
|
800315e: 463b mov r3, r7
|
|
8003160: 681b ldr r3, [r3, #0]
|
|
8003162: f107 000c add.w r0, r7, #12
|
|
8003166: 2201 movs r2, #1
|
|
8003168: 6800 ldr r0, [r0, #0]
|
|
800316a: f006 ff5f bl 800a02c <HAL_UART_Receive>
|
|
800316e: 4603 mov r3, r0
|
|
8003170: f887 3117 strb.w r3, [r7, #279] ; 0x117
|
|
if(i>=256)
|
|
{
|
|
printf("uart reception buffer flooded and going to be flushed\r\n");
|
|
break;
|
|
}
|
|
i++;
|
|
8003174: f897 3116 ldrb.w r3, [r7, #278] ; 0x116
|
|
8003178: 3301 adds r3, #1
|
|
800317a: f887 3116 strb.w r3, [r7, #278] ; 0x116
|
|
if(rslt)
|
|
800317e: f897 3117 ldrb.w r3, [r7, #279] ; 0x117
|
|
8003182: 2b00 cmp r3, #0
|
|
8003184: d007 beq.n 8003196 <at_Com+0xac>
|
|
{
|
|
rslt=huart->ErrorCode;
|
|
8003186: f107 030c add.w r3, r7, #12
|
|
800318a: 681b ldr r3, [r3, #0]
|
|
800318c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
8003190: f887 3117 strb.w r3, [r7, #279] ; 0x117
|
|
break;
|
|
8003194: e006 b.n 80031a4 <at_Com+0xba>
|
|
}
|
|
}while(tmp[i]!='\n');
|
|
8003196: f897 3116 ldrb.w r3, [r7, #278] ; 0x116
|
|
800319a: f107 0214 add.w r2, r7, #20
|
|
800319e: 5cd3 ldrb r3, [r2, r3]
|
|
80031a0: 2b0a cmp r3, #10
|
|
80031a2: d1d7 bne.n 8003154 <at_Com+0x6a>
|
|
if(!rslt)
|
|
80031a4: f897 3117 ldrb.w r3, [r7, #279] ; 0x117
|
|
80031a8: 2b00 cmp r3, #0
|
|
80031aa: d108 bne.n 80031be <at_Com+0xd4>
|
|
printf("%s",tmp);
|
|
80031ac: f107 0314 add.w r3, r7, #20
|
|
80031b0: 4619 mov r1, r3
|
|
80031b2: f24e 3020 movw r0, #58144 ; 0xe320
|
|
80031b6: f6c0 0000 movt r0, #2048 ; 0x800
|
|
80031ba: f008 fb4f bl 800b85c <iprintf>
|
|
}
|
|
memcpy(p_rcv,tmp,strlen((char*)tmp));
|
|
80031be: f107 0314 add.w r3, r7, #20
|
|
80031c2: 4618 mov r0, r3
|
|
80031c4: f7fd f804 bl 80001d0 <strlen>
|
|
80031c8: 4602 mov r2, r0
|
|
80031ca: f107 0114 add.w r1, r7, #20
|
|
80031ce: 1d3b adds r3, r7, #4
|
|
80031d0: 6818 ldr r0, [r3, #0]
|
|
80031d2: f007 fec3 bl 800af5c <memcpy>
|
|
memset(tmp,0,i);
|
|
80031d6: f897 2116 ldrb.w r2, [r7, #278] ; 0x116
|
|
80031da: f107 0314 add.w r3, r7, #20
|
|
80031de: 2100 movs r1, #0
|
|
80031e0: 4618 mov r0, r3
|
|
80031e2: f007 fec9 bl 800af78 <memset>
|
|
return rslt;
|
|
80031e6: f897 3117 ldrb.w r3, [r7, #279] ; 0x117
|
|
}
|
|
80031ea: 4618 mov r0, r3
|
|
80031ec: f507 778e add.w r7, r7, #284 ; 0x11c
|
|
80031f0: 46bd mov sp, r7
|
|
80031f2: bd90 pop {r4, r7, pc}
|
|
|
|
080031f4 <at_send>:
|
|
|
|
HAL_StatusTypeDef at_send(UART_HandleTypeDef *huart,uint8_t *p_ack, int timeout_ms,uint8_t size)
|
|
{
|
|
80031f4: b580 push {r7, lr}
|
|
80031f6: b088 sub sp, #32
|
|
80031f8: af02 add r7, sp, #8
|
|
80031fa: 60f8 str r0, [r7, #12]
|
|
80031fc: 60b9 str r1, [r7, #8]
|
|
80031fe: 607a str r2, [r7, #4]
|
|
8003200: 70fb strb r3, [r7, #3]
|
|
uint8_t rslt=0;
|
|
8003202: 2300 movs r3, #0
|
|
8003204: 75fb strb r3, [r7, #23]
|
|
rslt=at_Com(huart,p_ack,0, timeout_ms, size);
|
|
8003206: 78fb ldrb r3, [r7, #3]
|
|
8003208: 9300 str r3, [sp, #0]
|
|
800320a: 687b ldr r3, [r7, #4]
|
|
800320c: 2200 movs r2, #0
|
|
800320e: 68b9 ldr r1, [r7, #8]
|
|
8003210: 68f8 ldr r0, [r7, #12]
|
|
8003212: f7ff ff6a bl 80030ea <at_Com>
|
|
8003216: 4603 mov r3, r0
|
|
8003218: 75fb strb r3, [r7, #23]
|
|
|
|
return rslt;
|
|
800321a: 7dfb ldrb r3, [r7, #23]
|
|
|
|
}
|
|
800321c: 4618 mov r0, r3
|
|
800321e: 3718 adds r7, #24
|
|
8003220: 46bd mov sp, r7
|
|
8003222: bd80 pop {r7, pc}
|
|
|
|
08003224 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8003224: f8df d034 ldr.w sp, [pc, #52] ; 800325c <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8003228: f7ff ff11 bl 800304e <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
movs r1, #0
|
|
800322c: 2100 movs r1, #0
|
|
b LoopCopyDataInit
|
|
800322e: e003 b.n 8003238 <LoopCopyDataInit>
|
|
|
|
08003230 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r3, =_sidata
|
|
8003230: 4b0b ldr r3, [pc, #44] ; (8003260 <LoopForever+0x6>)
|
|
ldr r3, [r3, r1]
|
|
8003232: 585b ldr r3, [r3, r1]
|
|
str r3, [r0, r1]
|
|
8003234: 5043 str r3, [r0, r1]
|
|
adds r1, r1, #4
|
|
8003236: 3104 adds r1, #4
|
|
|
|
08003238 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
ldr r0, =_sdata
|
|
8003238: 480a ldr r0, [pc, #40] ; (8003264 <LoopForever+0xa>)
|
|
ldr r3, =_edata
|
|
800323a: 4b0b ldr r3, [pc, #44] ; (8003268 <LoopForever+0xe>)
|
|
adds r2, r0, r1
|
|
800323c: 1842 adds r2, r0, r1
|
|
cmp r2, r3
|
|
800323e: 429a cmp r2, r3
|
|
bcc CopyDataInit
|
|
8003240: d3f6 bcc.n 8003230 <CopyDataInit>
|
|
ldr r2, =_sbss
|
|
8003242: 4a0a ldr r2, [pc, #40] ; (800326c <LoopForever+0x12>)
|
|
b LoopFillZerobss
|
|
8003244: e002 b.n 800324c <LoopFillZerobss>
|
|
|
|
08003246 <FillZerobss>:
|
|
/* Zero fill the bss segment. */
|
|
FillZerobss:
|
|
movs r3, #0
|
|
8003246: 2300 movs r3, #0
|
|
str r3, [r2], #4
|
|
8003248: f842 3b04 str.w r3, [r2], #4
|
|
|
|
0800324c <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
ldr r3, = _ebss
|
|
800324c: 4b08 ldr r3, [pc, #32] ; (8003270 <LoopForever+0x16>)
|
|
cmp r2, r3
|
|
800324e: 429a cmp r2, r3
|
|
bcc FillZerobss
|
|
8003250: d3f9 bcc.n 8003246 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8003252: f007 fe5f bl 800af14 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
8003256: f7fe fdc0 bl 8001dda <main>
|
|
|
|
0800325a <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
800325a: e7fe b.n 800325a <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
800325c: 20018000 .word 0x20018000
|
|
ldr r3, =_sidata
|
|
8003260: 0800e7e8 .word 0x0800e7e8
|
|
ldr r0, =_sdata
|
|
8003264: 20000000 .word 0x20000000
|
|
ldr r3, =_edata
|
|
8003268: 2000044c .word 0x2000044c
|
|
ldr r2, =_sbss
|
|
800326c: 2000044c .word 0x2000044c
|
|
ldr r3, = _ebss
|
|
8003270: 20000a8c .word 0x20000a8c
|
|
|
|
08003274 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8003274: e7fe b.n 8003274 <ADC1_2_IRQHandler>
|
|
|
|
08003276 <bme680_init>:
|
|
/*!
|
|
*@brief This API is the entry point.
|
|
*It reads the chip-id and calibration data from the sensor.
|
|
*/
|
|
int8_t bme680_init(struct bme680_dev *dev)
|
|
{
|
|
8003276: b580 push {r7, lr}
|
|
8003278: b084 sub sp, #16
|
|
800327a: af00 add r7, sp, #0
|
|
800327c: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
800327e: 6878 ldr r0, [r7, #4]
|
|
8003280: f001 fa4a bl 8004718 <null_ptr_check>
|
|
8003284: 4603 mov r3, r0
|
|
8003286: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
8003288: f997 300f ldrsb.w r3, [r7, #15]
|
|
800328c: 2b00 cmp r3, #0
|
|
800328e: d120 bne.n 80032d2 <bme680_init+0x5c>
|
|
/* Soft reset to restore it to default values*/
|
|
rslt = bme680_soft_reset(dev);
|
|
8003290: 6878 ldr r0, [r7, #4]
|
|
8003292: f000 f8f1 bl 8003478 <bme680_soft_reset>
|
|
8003296: 4603 mov r3, r0
|
|
8003298: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
800329a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800329e: 2b00 cmp r3, #0
|
|
80032a0: d117 bne.n 80032d2 <bme680_init+0x5c>
|
|
rslt = bme680_get_regs(BME680_CHIP_ID_ADDR, &dev->chip_id, 1, dev);
|
|
80032a2: 6879 ldr r1, [r7, #4]
|
|
80032a4: 687b ldr r3, [r7, #4]
|
|
80032a6: 2201 movs r2, #1
|
|
80032a8: 20d0 movs r0, #208 ; 0xd0
|
|
80032aa: f000 f818 bl 80032de <bme680_get_regs>
|
|
80032ae: 4603 mov r3, r0
|
|
80032b0: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
80032b2: f997 300f ldrsb.w r3, [r7, #15]
|
|
80032b6: 2b00 cmp r3, #0
|
|
80032b8: d10b bne.n 80032d2 <bme680_init+0x5c>
|
|
if (dev->chip_id == BME680_CHIP_ID) {
|
|
80032ba: 687b ldr r3, [r7, #4]
|
|
80032bc: 781b ldrb r3, [r3, #0]
|
|
80032be: 2b61 cmp r3, #97 ; 0x61
|
|
80032c0: d105 bne.n 80032ce <bme680_init+0x58>
|
|
/* Get the Calibration data */
|
|
rslt = get_calib_data(dev);
|
|
80032c2: 6878 ldr r0, [r7, #4]
|
|
80032c4: f000 fbe0 bl 8003a88 <get_calib_data>
|
|
80032c8: 4603 mov r3, r0
|
|
80032ca: 73fb strb r3, [r7, #15]
|
|
80032cc: e001 b.n 80032d2 <bme680_init+0x5c>
|
|
} else {
|
|
rslt = BME680_E_DEV_NOT_FOUND;
|
|
80032ce: 23fd movs r3, #253 ; 0xfd
|
|
80032d0: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
80032d2: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
80032d6: 4618 mov r0, r3
|
|
80032d8: 3710 adds r7, #16
|
|
80032da: 46bd mov sp, r7
|
|
80032dc: bd80 pop {r7, pc}
|
|
|
|
080032de <bme680_get_regs>:
|
|
|
|
/*!
|
|
* @brief This API reads the data from the given register address of the sensor.
|
|
*/
|
|
int8_t bme680_get_regs(uint8_t reg_addr, uint8_t *reg_data, uint16_t len, struct bme680_dev *dev)
|
|
{
|
|
80032de: b590 push {r4, r7, lr}
|
|
80032e0: b087 sub sp, #28
|
|
80032e2: af00 add r7, sp, #0
|
|
80032e4: 60b9 str r1, [r7, #8]
|
|
80032e6: 607b str r3, [r7, #4]
|
|
80032e8: 4603 mov r3, r0
|
|
80032ea: 73fb strb r3, [r7, #15]
|
|
80032ec: 4613 mov r3, r2
|
|
80032ee: 81bb strh r3, [r7, #12]
|
|
int8_t rslt;
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
80032f0: 6878 ldr r0, [r7, #4]
|
|
80032f2: f001 fa11 bl 8004718 <null_ptr_check>
|
|
80032f6: 4603 mov r3, r0
|
|
80032f8: 75fb strb r3, [r7, #23]
|
|
if (rslt == BME680_OK) {
|
|
80032fa: f997 3017 ldrsb.w r3, [r7, #23]
|
|
80032fe: 2b00 cmp r3, #0
|
|
8003300: d126 bne.n 8003350 <bme680_get_regs+0x72>
|
|
if (dev->intf == BME680_SPI_INTF) {
|
|
8003302: 687b ldr r3, [r7, #4]
|
|
8003304: 789b ldrb r3, [r3, #2]
|
|
8003306: 2b00 cmp r3, #0
|
|
8003308: d10e bne.n 8003328 <bme680_get_regs+0x4a>
|
|
/* Set the memory page */
|
|
rslt = set_mem_page(reg_addr, dev);
|
|
800330a: 7bfb ldrb r3, [r7, #15]
|
|
800330c: 6879 ldr r1, [r7, #4]
|
|
800330e: 4618 mov r0, r3
|
|
8003310: f001 f933 bl 800457a <set_mem_page>
|
|
8003314: 4603 mov r3, r0
|
|
8003316: 75fb strb r3, [r7, #23]
|
|
if (rslt == BME680_OK)
|
|
8003318: f997 3017 ldrsb.w r3, [r7, #23]
|
|
800331c: 2b00 cmp r3, #0
|
|
800331e: d103 bne.n 8003328 <bme680_get_regs+0x4a>
|
|
reg_addr = reg_addr | BME680_SPI_RD_MSK;
|
|
8003320: 7bfb ldrb r3, [r7, #15]
|
|
8003322: f063 037f orn r3, r3, #127 ; 0x7f
|
|
8003326: 73fb strb r3, [r7, #15]
|
|
}
|
|
dev->com_rslt = dev->read(dev->dev_id, reg_addr, reg_data, len);
|
|
8003328: 687b ldr r3, [r7, #4]
|
|
800332a: 6c9c ldr r4, [r3, #72] ; 0x48
|
|
800332c: 687b ldr r3, [r7, #4]
|
|
800332e: 7858 ldrb r0, [r3, #1]
|
|
8003330: 89bb ldrh r3, [r7, #12]
|
|
8003332: 7bf9 ldrb r1, [r7, #15]
|
|
8003334: 68ba ldr r2, [r7, #8]
|
|
8003336: 47a0 blx r4
|
|
8003338: 4603 mov r3, r0
|
|
800333a: 461a mov r2, r3
|
|
800333c: 687b ldr r3, [r7, #4]
|
|
800333e: f883 2054 strb.w r2, [r3, #84] ; 0x54
|
|
if (dev->com_rslt != 0)
|
|
8003342: 687b ldr r3, [r7, #4]
|
|
8003344: f993 3054 ldrsb.w r3, [r3, #84] ; 0x54
|
|
8003348: 2b00 cmp r3, #0
|
|
800334a: d001 beq.n 8003350 <bme680_get_regs+0x72>
|
|
rslt = BME680_E_COM_FAIL;
|
|
800334c: 23fe movs r3, #254 ; 0xfe
|
|
800334e: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return rslt;
|
|
8003350: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
8003354: 4618 mov r0, r3
|
|
8003356: 371c adds r7, #28
|
|
8003358: 46bd mov sp, r7
|
|
800335a: bd90 pop {r4, r7, pc}
|
|
|
|
0800335c <bme680_set_regs>:
|
|
/*!
|
|
* @brief This API writes the given data to the register address
|
|
* of the sensor.
|
|
*/
|
|
int8_t bme680_set_regs(const uint8_t *reg_addr, const uint8_t *reg_data, uint8_t len, struct bme680_dev *dev)
|
|
{
|
|
800335c: b5b0 push {r4, r5, r7, lr}
|
|
800335e: b090 sub sp, #64 ; 0x40
|
|
8003360: af00 add r7, sp, #0
|
|
8003362: 60f8 str r0, [r7, #12]
|
|
8003364: 60b9 str r1, [r7, #8]
|
|
8003366: 603b str r3, [r7, #0]
|
|
8003368: 4613 mov r3, r2
|
|
800336a: 71fb strb r3, [r7, #7]
|
|
int8_t rslt;
|
|
/* Length of the temporary buffer is 2*(length of register)*/
|
|
uint8_t tmp_buff[BME680_TMP_BUFFER_LENGTH] = { 0 };
|
|
800336c: 2300 movs r3, #0
|
|
800336e: 617b str r3, [r7, #20]
|
|
8003370: f107 0318 add.w r3, r7, #24
|
|
8003374: 2224 movs r2, #36 ; 0x24
|
|
8003376: 2100 movs r1, #0
|
|
8003378: 4618 mov r0, r3
|
|
800337a: f007 fdfd bl 800af78 <memset>
|
|
uint16_t index;
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
800337e: 6838 ldr r0, [r7, #0]
|
|
8003380: f001 f9ca bl 8004718 <null_ptr_check>
|
|
8003384: 4603 mov r3, r0
|
|
8003386: f887 303f strb.w r3, [r7, #63] ; 0x3f
|
|
if (rslt == BME680_OK) {
|
|
800338a: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f
|
|
800338e: 2b00 cmp r3, #0
|
|
8003390: d16c bne.n 800346c <bme680_set_regs+0x110>
|
|
if ((len > 0) && (len < BME680_TMP_BUFFER_LENGTH / 2)) {
|
|
8003392: 79fb ldrb r3, [r7, #7]
|
|
8003394: 2b00 cmp r3, #0
|
|
8003396: d064 beq.n 8003462 <bme680_set_regs+0x106>
|
|
8003398: 79fb ldrb r3, [r7, #7]
|
|
800339a: 2b13 cmp r3, #19
|
|
800339c: d861 bhi.n 8003462 <bme680_set_regs+0x106>
|
|
/* Interleave the 2 arrays */
|
|
for (index = 0; index < len; index++) {
|
|
800339e: 2300 movs r3, #0
|
|
80033a0: 87bb strh r3, [r7, #60] ; 0x3c
|
|
80033a2: e037 b.n 8003414 <bme680_set_regs+0xb8>
|
|
if (dev->intf == BME680_SPI_INTF) {
|
|
80033a4: 683b ldr r3, [r7, #0]
|
|
80033a6: 789b ldrb r3, [r3, #2]
|
|
80033a8: 2b00 cmp r3, #0
|
|
80033aa: d119 bne.n 80033e0 <bme680_set_regs+0x84>
|
|
/* Set the memory page */
|
|
rslt = set_mem_page(reg_addr[index], dev);
|
|
80033ac: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
80033ae: 68fa ldr r2, [r7, #12]
|
|
80033b0: 4413 add r3, r2
|
|
80033b2: 781b ldrb r3, [r3, #0]
|
|
80033b4: 6839 ldr r1, [r7, #0]
|
|
80033b6: 4618 mov r0, r3
|
|
80033b8: f001 f8df bl 800457a <set_mem_page>
|
|
80033bc: 4603 mov r3, r0
|
|
80033be: f887 303f strb.w r3, [r7, #63] ; 0x3f
|
|
tmp_buff[(2 * index)] = reg_addr[index] & BME680_SPI_WR_MSK;
|
|
80033c2: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
80033c4: 68fa ldr r2, [r7, #12]
|
|
80033c6: 4413 add r3, r2
|
|
80033c8: 781a ldrb r2, [r3, #0]
|
|
80033ca: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
80033cc: 005b lsls r3, r3, #1
|
|
80033ce: f002 027f and.w r2, r2, #127 ; 0x7f
|
|
80033d2: b2d2 uxtb r2, r2
|
|
80033d4: f107 0140 add.w r1, r7, #64 ; 0x40
|
|
80033d8: 440b add r3, r1
|
|
80033da: f803 2c2c strb.w r2, [r3, #-44]
|
|
80033de: e00a b.n 80033f6 <bme680_set_regs+0x9a>
|
|
} else {
|
|
tmp_buff[(2 * index)] = reg_addr[index];
|
|
80033e0: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
80033e2: 68fa ldr r2, [r7, #12]
|
|
80033e4: 441a add r2, r3
|
|
80033e6: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
80033e8: 005b lsls r3, r3, #1
|
|
80033ea: 7812 ldrb r2, [r2, #0]
|
|
80033ec: f107 0140 add.w r1, r7, #64 ; 0x40
|
|
80033f0: 440b add r3, r1
|
|
80033f2: f803 2c2c strb.w r2, [r3, #-44]
|
|
}
|
|
tmp_buff[(2 * index) + 1] = reg_data[index];
|
|
80033f6: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
80033f8: 68ba ldr r2, [r7, #8]
|
|
80033fa: 441a add r2, r3
|
|
80033fc: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
80033fe: 005b lsls r3, r3, #1
|
|
8003400: 3301 adds r3, #1
|
|
8003402: 7812 ldrb r2, [r2, #0]
|
|
8003404: f107 0140 add.w r1, r7, #64 ; 0x40
|
|
8003408: 440b add r3, r1
|
|
800340a: f803 2c2c strb.w r2, [r3, #-44]
|
|
for (index = 0; index < len; index++) {
|
|
800340e: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
8003410: 3301 adds r3, #1
|
|
8003412: 87bb strh r3, [r7, #60] ; 0x3c
|
|
8003414: 79fb ldrb r3, [r7, #7]
|
|
8003416: b29b uxth r3, r3
|
|
8003418: 8fba ldrh r2, [r7, #60] ; 0x3c
|
|
800341a: 429a cmp r2, r3
|
|
800341c: d3c2 bcc.n 80033a4 <bme680_set_regs+0x48>
|
|
}
|
|
/* Write the interleaved array */
|
|
if (rslt == BME680_OK) {
|
|
800341e: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f
|
|
8003422: 2b00 cmp r3, #0
|
|
8003424: d121 bne.n 800346a <bme680_set_regs+0x10e>
|
|
dev->com_rslt = dev->write(dev->dev_id, tmp_buff[0], &tmp_buff[1], (2 * len) - 1);
|
|
8003426: 683b ldr r3, [r7, #0]
|
|
8003428: 6cdc ldr r4, [r3, #76] ; 0x4c
|
|
800342a: 683b ldr r3, [r7, #0]
|
|
800342c: 7858 ldrb r0, [r3, #1]
|
|
800342e: 7d39 ldrb r1, [r7, #20]
|
|
8003430: 79fb ldrb r3, [r7, #7]
|
|
8003432: b29b uxth r3, r3
|
|
8003434: 005b lsls r3, r3, #1
|
|
8003436: b29b uxth r3, r3
|
|
8003438: 3b01 subs r3, #1
|
|
800343a: b29d uxth r5, r3
|
|
800343c: f107 0314 add.w r3, r7, #20
|
|
8003440: 1c5a adds r2, r3, #1
|
|
8003442: 462b mov r3, r5
|
|
8003444: 47a0 blx r4
|
|
8003446: 4603 mov r3, r0
|
|
8003448: 461a mov r2, r3
|
|
800344a: 683b ldr r3, [r7, #0]
|
|
800344c: f883 2054 strb.w r2, [r3, #84] ; 0x54
|
|
if (dev->com_rslt != 0)
|
|
8003450: 683b ldr r3, [r7, #0]
|
|
8003452: f993 3054 ldrsb.w r3, [r3, #84] ; 0x54
|
|
8003456: 2b00 cmp r3, #0
|
|
8003458: d007 beq.n 800346a <bme680_set_regs+0x10e>
|
|
rslt = BME680_E_COM_FAIL;
|
|
800345a: 23fe movs r3, #254 ; 0xfe
|
|
800345c: f887 303f strb.w r3, [r7, #63] ; 0x3f
|
|
if (rslt == BME680_OK) {
|
|
8003460: e003 b.n 800346a <bme680_set_regs+0x10e>
|
|
}
|
|
} else {
|
|
rslt = BME680_E_INVALID_LENGTH;
|
|
8003462: 23fc movs r3, #252 ; 0xfc
|
|
8003464: f887 303f strb.w r3, [r7, #63] ; 0x3f
|
|
8003468: e000 b.n 800346c <bme680_set_regs+0x110>
|
|
if (rslt == BME680_OK) {
|
|
800346a: bf00 nop
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
800346c: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f
|
|
}
|
|
8003470: 4618 mov r0, r3
|
|
8003472: 3740 adds r7, #64 ; 0x40
|
|
8003474: 46bd mov sp, r7
|
|
8003476: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
08003478 <bme680_soft_reset>:
|
|
|
|
/*!
|
|
* @brief This API performs the soft reset of the sensor.
|
|
*/
|
|
int8_t bme680_soft_reset(struct bme680_dev *dev)
|
|
{
|
|
8003478: b580 push {r7, lr}
|
|
800347a: b084 sub sp, #16
|
|
800347c: af00 add r7, sp, #0
|
|
800347e: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
uint8_t reg_addr = BME680_SOFT_RESET_ADDR;
|
|
8003480: 23e0 movs r3, #224 ; 0xe0
|
|
8003482: 73bb strb r3, [r7, #14]
|
|
/* 0xb6 is the soft reset command */
|
|
uint8_t soft_rst_cmd = BME680_SOFT_RESET_CMD;
|
|
8003484: 23b6 movs r3, #182 ; 0xb6
|
|
8003486: 737b strb r3, [r7, #13]
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
8003488: 6878 ldr r0, [r7, #4]
|
|
800348a: f001 f945 bl 8004718 <null_ptr_check>
|
|
800348e: 4603 mov r3, r0
|
|
8003490: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
8003492: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003496: 2b00 cmp r3, #0
|
|
8003498: d127 bne.n 80034ea <bme680_soft_reset+0x72>
|
|
if (dev->intf == BME680_SPI_INTF)
|
|
800349a: 687b ldr r3, [r7, #4]
|
|
800349c: 789b ldrb r3, [r3, #2]
|
|
800349e: 2b00 cmp r3, #0
|
|
80034a0: d104 bne.n 80034ac <bme680_soft_reset+0x34>
|
|
rslt = get_mem_page(dev);
|
|
80034a2: 6878 ldr r0, [r7, #4]
|
|
80034a4: f001 f8ce bl 8004644 <get_mem_page>
|
|
80034a8: 4603 mov r3, r0
|
|
80034aa: 73fb strb r3, [r7, #15]
|
|
|
|
/* Reset the device */
|
|
if (rslt == BME680_OK) {
|
|
80034ac: f997 300f ldrsb.w r3, [r7, #15]
|
|
80034b0: 2b00 cmp r3, #0
|
|
80034b2: d11a bne.n 80034ea <bme680_soft_reset+0x72>
|
|
rslt = bme680_set_regs(®_addr, &soft_rst_cmd, 1, dev);
|
|
80034b4: f107 010d add.w r1, r7, #13
|
|
80034b8: f107 000e add.w r0, r7, #14
|
|
80034bc: 687b ldr r3, [r7, #4]
|
|
80034be: 2201 movs r2, #1
|
|
80034c0: f7ff ff4c bl 800335c <bme680_set_regs>
|
|
80034c4: 4603 mov r3, r0
|
|
80034c6: 73fb strb r3, [r7, #15]
|
|
/* Wait for 5ms */
|
|
dev->delay_ms(BME680_RESET_PERIOD);
|
|
80034c8: 687b ldr r3, [r7, #4]
|
|
80034ca: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
80034cc: 200a movs r0, #10
|
|
80034ce: 4798 blx r3
|
|
|
|
if (rslt == BME680_OK) {
|
|
80034d0: f997 300f ldrsb.w r3, [r7, #15]
|
|
80034d4: 2b00 cmp r3, #0
|
|
80034d6: d108 bne.n 80034ea <bme680_soft_reset+0x72>
|
|
/* After reset get the memory page */
|
|
if (dev->intf == BME680_SPI_INTF)
|
|
80034d8: 687b ldr r3, [r7, #4]
|
|
80034da: 789b ldrb r3, [r3, #2]
|
|
80034dc: 2b00 cmp r3, #0
|
|
80034de: d104 bne.n 80034ea <bme680_soft_reset+0x72>
|
|
rslt = get_mem_page(dev);
|
|
80034e0: 6878 ldr r0, [r7, #4]
|
|
80034e2: f001 f8af bl 8004644 <get_mem_page>
|
|
80034e6: 4603 mov r3, r0
|
|
80034e8: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
80034ea: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
80034ee: 4618 mov r0, r3
|
|
80034f0: 3710 adds r7, #16
|
|
80034f2: 46bd mov sp, r7
|
|
80034f4: bd80 pop {r7, pc}
|
|
|
|
080034f6 <bme680_set_sensor_settings>:
|
|
/*!
|
|
* @brief This API is used to set the oversampling, filter and T,P,H, gas selection
|
|
* settings in the sensor.
|
|
*/
|
|
int8_t bme680_set_sensor_settings(uint16_t desired_settings, struct bme680_dev *dev)
|
|
{
|
|
80034f6: b580 push {r7, lr}
|
|
80034f8: b088 sub sp, #32
|
|
80034fa: af00 add r7, sp, #0
|
|
80034fc: 4603 mov r3, r0
|
|
80034fe: 6039 str r1, [r7, #0]
|
|
8003500: 80fb strh r3, [r7, #6]
|
|
int8_t rslt;
|
|
uint8_t reg_addr;
|
|
uint8_t data = 0;
|
|
8003502: 2300 movs r3, #0
|
|
8003504: 76fb strb r3, [r7, #27]
|
|
uint8_t count = 0;
|
|
8003506: 2300 movs r3, #0
|
|
8003508: 77bb strb r3, [r7, #30]
|
|
uint8_t reg_array[BME680_REG_BUFFER_LENGTH] = { 0 };
|
|
800350a: 2300 movs r3, #0
|
|
800350c: 617b str r3, [r7, #20]
|
|
800350e: 2300 movs r3, #0
|
|
8003510: 833b strh r3, [r7, #24]
|
|
uint8_t data_array[BME680_REG_BUFFER_LENGTH] = { 0 };
|
|
8003512: 2300 movs r3, #0
|
|
8003514: 60fb str r3, [r7, #12]
|
|
8003516: 2300 movs r3, #0
|
|
8003518: 823b strh r3, [r7, #16]
|
|
uint8_t intended_power_mode = dev->power_mode; /* Save intended power mode */
|
|
800351a: 683b ldr r3, [r7, #0]
|
|
800351c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
8003520: 777b strb r3, [r7, #29]
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
8003522: 6838 ldr r0, [r7, #0]
|
|
8003524: f001 f8f8 bl 8004718 <null_ptr_check>
|
|
8003528: 4603 mov r3, r0
|
|
800352a: 77fb strb r3, [r7, #31]
|
|
if (rslt == BME680_OK) {
|
|
800352c: f997 301f ldrsb.w r3, [r7, #31]
|
|
8003530: 2b00 cmp r3, #0
|
|
8003532: f040 81ac bne.w 800388e <bme680_set_sensor_settings+0x398>
|
|
if (desired_settings & BME680_GAS_MEAS_SEL)
|
|
8003536: 88fb ldrh r3, [r7, #6]
|
|
8003538: f003 0308 and.w r3, r3, #8
|
|
800353c: 2b00 cmp r3, #0
|
|
800353e: d004 beq.n 800354a <bme680_set_sensor_settings+0x54>
|
|
rslt = set_gas_config(dev);
|
|
8003540: 6838 ldr r0, [r7, #0]
|
|
8003542: f000 fbcd bl 8003ce0 <set_gas_config>
|
|
8003546: 4603 mov r3, r0
|
|
8003548: 77fb strb r3, [r7, #31]
|
|
|
|
dev->power_mode = BME680_SLEEP_MODE;
|
|
800354a: 683b ldr r3, [r7, #0]
|
|
800354c: 2200 movs r2, #0
|
|
800354e: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
if (rslt == BME680_OK)
|
|
8003552: f997 301f ldrsb.w r3, [r7, #31]
|
|
8003556: 2b00 cmp r3, #0
|
|
8003558: d104 bne.n 8003564 <bme680_set_sensor_settings+0x6e>
|
|
rslt = bme680_set_sensor_mode(dev);
|
|
800355a: 6838 ldr r0, [r7, #0]
|
|
800355c: f000 f99d bl 800389a <bme680_set_sensor_mode>
|
|
8003560: 4603 mov r3, r0
|
|
8003562: 77fb strb r3, [r7, #31]
|
|
|
|
/* Selecting the filter */
|
|
if (desired_settings & BME680_FILTER_SEL) {
|
|
8003564: 88fb ldrh r3, [r7, #6]
|
|
8003566: f003 0310 and.w r3, r3, #16
|
|
800356a: 2b00 cmp r3, #0
|
|
800356c: d03f beq.n 80035ee <bme680_set_sensor_settings+0xf8>
|
|
rslt = boundary_check(&dev->tph_sett.filter, BME680_FILTER_SIZE_0, BME680_FILTER_SIZE_127, dev);
|
|
800356e: 683b ldr r3, [r7, #0]
|
|
8003570: f103 003b add.w r0, r3, #59 ; 0x3b
|
|
8003574: 683b ldr r3, [r7, #0]
|
|
8003576: 2207 movs r2, #7
|
|
8003578: 2100 movs r1, #0
|
|
800357a: f001 f892 bl 80046a2 <boundary_check>
|
|
800357e: 4603 mov r3, r0
|
|
8003580: 77fb strb r3, [r7, #31]
|
|
reg_addr = BME680_CONF_ODR_FILT_ADDR;
|
|
8003582: 2375 movs r3, #117 ; 0x75
|
|
8003584: 773b strb r3, [r7, #28]
|
|
|
|
if (rslt == BME680_OK)
|
|
8003586: f997 301f ldrsb.w r3, [r7, #31]
|
|
800358a: 2b00 cmp r3, #0
|
|
800358c: d108 bne.n 80035a0 <bme680_set_sensor_settings+0xaa>
|
|
rslt = bme680_get_regs(reg_addr, &data, 1, dev);
|
|
800358e: f107 011b add.w r1, r7, #27
|
|
8003592: 7f38 ldrb r0, [r7, #28]
|
|
8003594: 683b ldr r3, [r7, #0]
|
|
8003596: 2201 movs r2, #1
|
|
8003598: f7ff fea1 bl 80032de <bme680_get_regs>
|
|
800359c: 4603 mov r3, r0
|
|
800359e: 77fb strb r3, [r7, #31]
|
|
|
|
if (desired_settings & BME680_FILTER_SEL)
|
|
80035a0: 88fb ldrh r3, [r7, #6]
|
|
80035a2: f003 0310 and.w r3, r3, #16
|
|
80035a6: 2b00 cmp r3, #0
|
|
80035a8: d010 beq.n 80035cc <bme680_set_sensor_settings+0xd6>
|
|
data = BME680_SET_BITS(data, BME680_FILTER, dev->tph_sett.filter);
|
|
80035aa: 7efb ldrb r3, [r7, #27]
|
|
80035ac: b25b sxtb r3, r3
|
|
80035ae: f023 031c bic.w r3, r3, #28
|
|
80035b2: b25a sxtb r2, r3
|
|
80035b4: 683b ldr r3, [r7, #0]
|
|
80035b6: f893 303b ldrb.w r3, [r3, #59] ; 0x3b
|
|
80035ba: 009b lsls r3, r3, #2
|
|
80035bc: b25b sxtb r3, r3
|
|
80035be: f003 031c and.w r3, r3, #28
|
|
80035c2: b25b sxtb r3, r3
|
|
80035c4: 4313 orrs r3, r2
|
|
80035c6: b25b sxtb r3, r3
|
|
80035c8: b2db uxtb r3, r3
|
|
80035ca: 76fb strb r3, [r7, #27]
|
|
|
|
reg_array[count] = reg_addr; /* Append configuration */
|
|
80035cc: 7fbb ldrb r3, [r7, #30]
|
|
80035ce: f107 0220 add.w r2, r7, #32
|
|
80035d2: 4413 add r3, r2
|
|
80035d4: 7f3a ldrb r2, [r7, #28]
|
|
80035d6: f803 2c0c strb.w r2, [r3, #-12]
|
|
data_array[count] = data;
|
|
80035da: 7fbb ldrb r3, [r7, #30]
|
|
80035dc: 7efa ldrb r2, [r7, #27]
|
|
80035de: f107 0120 add.w r1, r7, #32
|
|
80035e2: 440b add r3, r1
|
|
80035e4: f803 2c14 strb.w r2, [r3, #-20]
|
|
count++;
|
|
80035e8: 7fbb ldrb r3, [r7, #30]
|
|
80035ea: 3301 adds r3, #1
|
|
80035ec: 77bb strb r3, [r7, #30]
|
|
}
|
|
|
|
/* Selecting heater control for the sensor */
|
|
if (desired_settings & BME680_HCNTRL_SEL) {
|
|
80035ee: 88fb ldrh r3, [r7, #6]
|
|
80035f0: f003 0320 and.w r3, r3, #32
|
|
80035f4: 2b00 cmp r3, #0
|
|
80035f6: d039 beq.n 800366c <bme680_set_sensor_settings+0x176>
|
|
rslt = boundary_check(&dev->gas_sett.heatr_ctrl, BME680_ENABLE_HEATER,
|
|
80035f8: 683b ldr r3, [r7, #0]
|
|
80035fa: f103 003d add.w r0, r3, #61 ; 0x3d
|
|
80035fe: 683b ldr r3, [r7, #0]
|
|
8003600: 2208 movs r2, #8
|
|
8003602: 2100 movs r1, #0
|
|
8003604: f001 f84d bl 80046a2 <boundary_check>
|
|
8003608: 4603 mov r3, r0
|
|
800360a: 77fb strb r3, [r7, #31]
|
|
BME680_DISABLE_HEATER, dev);
|
|
reg_addr = BME680_CONF_HEAT_CTRL_ADDR;
|
|
800360c: 2370 movs r3, #112 ; 0x70
|
|
800360e: 773b strb r3, [r7, #28]
|
|
|
|
if (rslt == BME680_OK)
|
|
8003610: f997 301f ldrsb.w r3, [r7, #31]
|
|
8003614: 2b00 cmp r3, #0
|
|
8003616: d108 bne.n 800362a <bme680_set_sensor_settings+0x134>
|
|
rslt = bme680_get_regs(reg_addr, &data, 1, dev);
|
|
8003618: f107 011b add.w r1, r7, #27
|
|
800361c: 7f38 ldrb r0, [r7, #28]
|
|
800361e: 683b ldr r3, [r7, #0]
|
|
8003620: 2201 movs r2, #1
|
|
8003622: f7ff fe5c bl 80032de <bme680_get_regs>
|
|
8003626: 4603 mov r3, r0
|
|
8003628: 77fb strb r3, [r7, #31]
|
|
data = BME680_SET_BITS_POS_0(data, BME680_HCTRL, dev->gas_sett.heatr_ctrl);
|
|
800362a: 7efb ldrb r3, [r7, #27]
|
|
800362c: b25b sxtb r3, r3
|
|
800362e: f023 0308 bic.w r3, r3, #8
|
|
8003632: b25a sxtb r2, r3
|
|
8003634: 683b ldr r3, [r7, #0]
|
|
8003636: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
800363a: b25b sxtb r3, r3
|
|
800363c: f003 0308 and.w r3, r3, #8
|
|
8003640: b25b sxtb r3, r3
|
|
8003642: 4313 orrs r3, r2
|
|
8003644: b25b sxtb r3, r3
|
|
8003646: b2db uxtb r3, r3
|
|
8003648: 76fb strb r3, [r7, #27]
|
|
|
|
reg_array[count] = reg_addr; /* Append configuration */
|
|
800364a: 7fbb ldrb r3, [r7, #30]
|
|
800364c: f107 0220 add.w r2, r7, #32
|
|
8003650: 4413 add r3, r2
|
|
8003652: 7f3a ldrb r2, [r7, #28]
|
|
8003654: f803 2c0c strb.w r2, [r3, #-12]
|
|
data_array[count] = data;
|
|
8003658: 7fbb ldrb r3, [r7, #30]
|
|
800365a: 7efa ldrb r2, [r7, #27]
|
|
800365c: f107 0120 add.w r1, r7, #32
|
|
8003660: 440b add r3, r1
|
|
8003662: f803 2c14 strb.w r2, [r3, #-20]
|
|
count++;
|
|
8003666: 7fbb ldrb r3, [r7, #30]
|
|
8003668: 3301 adds r3, #1
|
|
800366a: 77bb strb r3, [r7, #30]
|
|
}
|
|
|
|
/* Selecting heater T,P oversampling for the sensor */
|
|
if (desired_settings & (BME680_OST_SEL | BME680_OSP_SEL)) {
|
|
800366c: 88fb ldrh r3, [r7, #6]
|
|
800366e: f003 0303 and.w r3, r3, #3
|
|
8003672: 2b00 cmp r3, #0
|
|
8003674: d052 beq.n 800371c <bme680_set_sensor_settings+0x226>
|
|
rslt = boundary_check(&dev->tph_sett.os_temp, BME680_OS_NONE, BME680_OS_16X, dev);
|
|
8003676: 683b ldr r3, [r7, #0]
|
|
8003678: f103 0039 add.w r0, r3, #57 ; 0x39
|
|
800367c: 683b ldr r3, [r7, #0]
|
|
800367e: 2205 movs r2, #5
|
|
8003680: 2100 movs r1, #0
|
|
8003682: f001 f80e bl 80046a2 <boundary_check>
|
|
8003686: 4603 mov r3, r0
|
|
8003688: 77fb strb r3, [r7, #31]
|
|
reg_addr = BME680_CONF_T_P_MODE_ADDR;
|
|
800368a: 2374 movs r3, #116 ; 0x74
|
|
800368c: 773b strb r3, [r7, #28]
|
|
|
|
if (rslt == BME680_OK)
|
|
800368e: f997 301f ldrsb.w r3, [r7, #31]
|
|
8003692: 2b00 cmp r3, #0
|
|
8003694: d108 bne.n 80036a8 <bme680_set_sensor_settings+0x1b2>
|
|
rslt = bme680_get_regs(reg_addr, &data, 1, dev);
|
|
8003696: f107 011b add.w r1, r7, #27
|
|
800369a: 7f38 ldrb r0, [r7, #28]
|
|
800369c: 683b ldr r3, [r7, #0]
|
|
800369e: 2201 movs r2, #1
|
|
80036a0: f7ff fe1d bl 80032de <bme680_get_regs>
|
|
80036a4: 4603 mov r3, r0
|
|
80036a6: 77fb strb r3, [r7, #31]
|
|
|
|
if (desired_settings & BME680_OST_SEL)
|
|
80036a8: 88fb ldrh r3, [r7, #6]
|
|
80036aa: f003 0301 and.w r3, r3, #1
|
|
80036ae: 2b00 cmp r3, #0
|
|
80036b0: d00d beq.n 80036ce <bme680_set_sensor_settings+0x1d8>
|
|
data = BME680_SET_BITS(data, BME680_OST, dev->tph_sett.os_temp);
|
|
80036b2: 7efb ldrb r3, [r7, #27]
|
|
80036b4: b25b sxtb r3, r3
|
|
80036b6: f003 031f and.w r3, r3, #31
|
|
80036ba: b25a sxtb r2, r3
|
|
80036bc: 683b ldr r3, [r7, #0]
|
|
80036be: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
|
|
80036c2: 015b lsls r3, r3, #5
|
|
80036c4: b25b sxtb r3, r3
|
|
80036c6: 4313 orrs r3, r2
|
|
80036c8: b25b sxtb r3, r3
|
|
80036ca: b2db uxtb r3, r3
|
|
80036cc: 76fb strb r3, [r7, #27]
|
|
|
|
if (desired_settings & BME680_OSP_SEL)
|
|
80036ce: 88fb ldrh r3, [r7, #6]
|
|
80036d0: f003 0302 and.w r3, r3, #2
|
|
80036d4: 2b00 cmp r3, #0
|
|
80036d6: d010 beq.n 80036fa <bme680_set_sensor_settings+0x204>
|
|
data = BME680_SET_BITS(data, BME680_OSP, dev->tph_sett.os_pres);
|
|
80036d8: 7efb ldrb r3, [r7, #27]
|
|
80036da: b25b sxtb r3, r3
|
|
80036dc: f023 031c bic.w r3, r3, #28
|
|
80036e0: b25a sxtb r2, r3
|
|
80036e2: 683b ldr r3, [r7, #0]
|
|
80036e4: f893 303a ldrb.w r3, [r3, #58] ; 0x3a
|
|
80036e8: 009b lsls r3, r3, #2
|
|
80036ea: b25b sxtb r3, r3
|
|
80036ec: f003 031c and.w r3, r3, #28
|
|
80036f0: b25b sxtb r3, r3
|
|
80036f2: 4313 orrs r3, r2
|
|
80036f4: b25b sxtb r3, r3
|
|
80036f6: b2db uxtb r3, r3
|
|
80036f8: 76fb strb r3, [r7, #27]
|
|
|
|
reg_array[count] = reg_addr;
|
|
80036fa: 7fbb ldrb r3, [r7, #30]
|
|
80036fc: f107 0220 add.w r2, r7, #32
|
|
8003700: 4413 add r3, r2
|
|
8003702: 7f3a ldrb r2, [r7, #28]
|
|
8003704: f803 2c0c strb.w r2, [r3, #-12]
|
|
data_array[count] = data;
|
|
8003708: 7fbb ldrb r3, [r7, #30]
|
|
800370a: 7efa ldrb r2, [r7, #27]
|
|
800370c: f107 0120 add.w r1, r7, #32
|
|
8003710: 440b add r3, r1
|
|
8003712: f803 2c14 strb.w r2, [r3, #-20]
|
|
count++;
|
|
8003716: 7fbb ldrb r3, [r7, #30]
|
|
8003718: 3301 adds r3, #1
|
|
800371a: 77bb strb r3, [r7, #30]
|
|
}
|
|
|
|
/* Selecting humidity oversampling for the sensor */
|
|
if (desired_settings & BME680_OSH_SEL) {
|
|
800371c: 88fb ldrh r3, [r7, #6]
|
|
800371e: f003 0304 and.w r3, r3, #4
|
|
8003722: 2b00 cmp r3, #0
|
|
8003724: d039 beq.n 800379a <bme680_set_sensor_settings+0x2a4>
|
|
rslt = boundary_check(&dev->tph_sett.os_hum, BME680_OS_NONE, BME680_OS_16X, dev);
|
|
8003726: 683b ldr r3, [r7, #0]
|
|
8003728: f103 0038 add.w r0, r3, #56 ; 0x38
|
|
800372c: 683b ldr r3, [r7, #0]
|
|
800372e: 2205 movs r2, #5
|
|
8003730: 2100 movs r1, #0
|
|
8003732: f000 ffb6 bl 80046a2 <boundary_check>
|
|
8003736: 4603 mov r3, r0
|
|
8003738: 77fb strb r3, [r7, #31]
|
|
reg_addr = BME680_CONF_OS_H_ADDR;
|
|
800373a: 2372 movs r3, #114 ; 0x72
|
|
800373c: 773b strb r3, [r7, #28]
|
|
|
|
if (rslt == BME680_OK)
|
|
800373e: f997 301f ldrsb.w r3, [r7, #31]
|
|
8003742: 2b00 cmp r3, #0
|
|
8003744: d108 bne.n 8003758 <bme680_set_sensor_settings+0x262>
|
|
rslt = bme680_get_regs(reg_addr, &data, 1, dev);
|
|
8003746: f107 011b add.w r1, r7, #27
|
|
800374a: 7f38 ldrb r0, [r7, #28]
|
|
800374c: 683b ldr r3, [r7, #0]
|
|
800374e: 2201 movs r2, #1
|
|
8003750: f7ff fdc5 bl 80032de <bme680_get_regs>
|
|
8003754: 4603 mov r3, r0
|
|
8003756: 77fb strb r3, [r7, #31]
|
|
data = BME680_SET_BITS_POS_0(data, BME680_OSH, dev->tph_sett.os_hum);
|
|
8003758: 7efb ldrb r3, [r7, #27]
|
|
800375a: b25b sxtb r3, r3
|
|
800375c: f023 0307 bic.w r3, r3, #7
|
|
8003760: b25a sxtb r2, r3
|
|
8003762: 683b ldr r3, [r7, #0]
|
|
8003764: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
|
|
8003768: b25b sxtb r3, r3
|
|
800376a: f003 0307 and.w r3, r3, #7
|
|
800376e: b25b sxtb r3, r3
|
|
8003770: 4313 orrs r3, r2
|
|
8003772: b25b sxtb r3, r3
|
|
8003774: b2db uxtb r3, r3
|
|
8003776: 76fb strb r3, [r7, #27]
|
|
|
|
reg_array[count] = reg_addr; /* Append configuration */
|
|
8003778: 7fbb ldrb r3, [r7, #30]
|
|
800377a: f107 0220 add.w r2, r7, #32
|
|
800377e: 4413 add r3, r2
|
|
8003780: 7f3a ldrb r2, [r7, #28]
|
|
8003782: f803 2c0c strb.w r2, [r3, #-12]
|
|
data_array[count] = data;
|
|
8003786: 7fbb ldrb r3, [r7, #30]
|
|
8003788: 7efa ldrb r2, [r7, #27]
|
|
800378a: f107 0120 add.w r1, r7, #32
|
|
800378e: 440b add r3, r1
|
|
8003790: f803 2c14 strb.w r2, [r3, #-20]
|
|
count++;
|
|
8003794: 7fbb ldrb r3, [r7, #30]
|
|
8003796: 3301 adds r3, #1
|
|
8003798: 77bb strb r3, [r7, #30]
|
|
}
|
|
|
|
/* Selecting the runGas and NB conversion settings for the sensor */
|
|
if (desired_settings & (BME680_RUN_GAS_SEL | BME680_NBCONV_SEL)) {
|
|
800379a: 88fb ldrh r3, [r7, #6]
|
|
800379c: f003 03c0 and.w r3, r3, #192 ; 0xc0
|
|
80037a0: 2b00 cmp r3, #0
|
|
80037a2: d062 beq.n 800386a <bme680_set_sensor_settings+0x374>
|
|
rslt = boundary_check(&dev->gas_sett.run_gas, BME680_RUN_GAS_DISABLE,
|
|
80037a4: 683b ldr r3, [r7, #0]
|
|
80037a6: f103 003e add.w r0, r3, #62 ; 0x3e
|
|
80037aa: 683b ldr r3, [r7, #0]
|
|
80037ac: 2201 movs r2, #1
|
|
80037ae: 2100 movs r1, #0
|
|
80037b0: f000 ff77 bl 80046a2 <boundary_check>
|
|
80037b4: 4603 mov r3, r0
|
|
80037b6: 77fb strb r3, [r7, #31]
|
|
BME680_RUN_GAS_ENABLE, dev);
|
|
if (rslt == BME680_OK) {
|
|
80037b8: f997 301f ldrsb.w r3, [r7, #31]
|
|
80037bc: 2b00 cmp r3, #0
|
|
80037be: d109 bne.n 80037d4 <bme680_set_sensor_settings+0x2de>
|
|
/* Validate boundary conditions */
|
|
rslt = boundary_check(&dev->gas_sett.nb_conv, BME680_NBCONV_MIN,
|
|
80037c0: 683b ldr r3, [r7, #0]
|
|
80037c2: f103 003c add.w r0, r3, #60 ; 0x3c
|
|
80037c6: 683b ldr r3, [r7, #0]
|
|
80037c8: 220a movs r2, #10
|
|
80037ca: 2100 movs r1, #0
|
|
80037cc: f000 ff69 bl 80046a2 <boundary_check>
|
|
80037d0: 4603 mov r3, r0
|
|
80037d2: 77fb strb r3, [r7, #31]
|
|
BME680_NBCONV_MAX, dev);
|
|
}
|
|
|
|
reg_addr = BME680_CONF_ODR_RUN_GAS_NBC_ADDR;
|
|
80037d4: 2371 movs r3, #113 ; 0x71
|
|
80037d6: 773b strb r3, [r7, #28]
|
|
|
|
if (rslt == BME680_OK)
|
|
80037d8: f997 301f ldrsb.w r3, [r7, #31]
|
|
80037dc: 2b00 cmp r3, #0
|
|
80037de: d108 bne.n 80037f2 <bme680_set_sensor_settings+0x2fc>
|
|
rslt = bme680_get_regs(reg_addr, &data, 1, dev);
|
|
80037e0: f107 011b add.w r1, r7, #27
|
|
80037e4: 7f38 ldrb r0, [r7, #28]
|
|
80037e6: 683b ldr r3, [r7, #0]
|
|
80037e8: 2201 movs r2, #1
|
|
80037ea: f7ff fd78 bl 80032de <bme680_get_regs>
|
|
80037ee: 4603 mov r3, r0
|
|
80037f0: 77fb strb r3, [r7, #31]
|
|
|
|
if (desired_settings & BME680_RUN_GAS_SEL)
|
|
80037f2: 88fb ldrh r3, [r7, #6]
|
|
80037f4: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
80037f8: 2b00 cmp r3, #0
|
|
80037fa: d010 beq.n 800381e <bme680_set_sensor_settings+0x328>
|
|
data = BME680_SET_BITS(data, BME680_RUN_GAS, dev->gas_sett.run_gas);
|
|
80037fc: 7efb ldrb r3, [r7, #27]
|
|
80037fe: b25b sxtb r3, r3
|
|
8003800: f023 0310 bic.w r3, r3, #16
|
|
8003804: b25a sxtb r2, r3
|
|
8003806: 683b ldr r3, [r7, #0]
|
|
8003808: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
|
|
800380c: 011b lsls r3, r3, #4
|
|
800380e: b25b sxtb r3, r3
|
|
8003810: f003 0310 and.w r3, r3, #16
|
|
8003814: b25b sxtb r3, r3
|
|
8003816: 4313 orrs r3, r2
|
|
8003818: b25b sxtb r3, r3
|
|
800381a: b2db uxtb r3, r3
|
|
800381c: 76fb strb r3, [r7, #27]
|
|
|
|
if (desired_settings & BME680_NBCONV_SEL)
|
|
800381e: 88fb ldrh r3, [r7, #6]
|
|
8003820: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
8003824: 2b00 cmp r3, #0
|
|
8003826: d00f beq.n 8003848 <bme680_set_sensor_settings+0x352>
|
|
data = BME680_SET_BITS_POS_0(data, BME680_NBCONV, dev->gas_sett.nb_conv);
|
|
8003828: 7efb ldrb r3, [r7, #27]
|
|
800382a: b25b sxtb r3, r3
|
|
800382c: f023 030f bic.w r3, r3, #15
|
|
8003830: b25a sxtb r2, r3
|
|
8003832: 683b ldr r3, [r7, #0]
|
|
8003834: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
8003838: b25b sxtb r3, r3
|
|
800383a: f003 030f and.w r3, r3, #15
|
|
800383e: b25b sxtb r3, r3
|
|
8003840: 4313 orrs r3, r2
|
|
8003842: b25b sxtb r3, r3
|
|
8003844: b2db uxtb r3, r3
|
|
8003846: 76fb strb r3, [r7, #27]
|
|
|
|
reg_array[count] = reg_addr; /* Append configuration */
|
|
8003848: 7fbb ldrb r3, [r7, #30]
|
|
800384a: f107 0220 add.w r2, r7, #32
|
|
800384e: 4413 add r3, r2
|
|
8003850: 7f3a ldrb r2, [r7, #28]
|
|
8003852: f803 2c0c strb.w r2, [r3, #-12]
|
|
data_array[count] = data;
|
|
8003856: 7fbb ldrb r3, [r7, #30]
|
|
8003858: 7efa ldrb r2, [r7, #27]
|
|
800385a: f107 0120 add.w r1, r7, #32
|
|
800385e: 440b add r3, r1
|
|
8003860: f803 2c14 strb.w r2, [r3, #-20]
|
|
count++;
|
|
8003864: 7fbb ldrb r3, [r7, #30]
|
|
8003866: 3301 adds r3, #1
|
|
8003868: 77bb strb r3, [r7, #30]
|
|
}
|
|
|
|
if (rslt == BME680_OK)
|
|
800386a: f997 301f ldrsb.w r3, [r7, #31]
|
|
800386e: 2b00 cmp r3, #0
|
|
8003870: d109 bne.n 8003886 <bme680_set_sensor_settings+0x390>
|
|
rslt = bme680_set_regs(reg_array, data_array, count, dev);
|
|
8003872: 7fba ldrb r2, [r7, #30]
|
|
8003874: f107 010c add.w r1, r7, #12
|
|
8003878: f107 0014 add.w r0, r7, #20
|
|
800387c: 683b ldr r3, [r7, #0]
|
|
800387e: f7ff fd6d bl 800335c <bme680_set_regs>
|
|
8003882: 4603 mov r3, r0
|
|
8003884: 77fb strb r3, [r7, #31]
|
|
|
|
/* Restore previous intended power mode */
|
|
dev->power_mode = intended_power_mode;
|
|
8003886: 683b ldr r3, [r7, #0]
|
|
8003888: 7f7a ldrb r2, [r7, #29]
|
|
800388a: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
}
|
|
|
|
return rslt;
|
|
800388e: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
8003892: 4618 mov r0, r3
|
|
8003894: 3720 adds r7, #32
|
|
8003896: 46bd mov sp, r7
|
|
8003898: bd80 pop {r7, pc}
|
|
|
|
0800389a <bme680_set_sensor_mode>:
|
|
|
|
/*!
|
|
* @brief This API is used to set the power mode of the sensor.
|
|
*/
|
|
int8_t bme680_set_sensor_mode(struct bme680_dev *dev)
|
|
{
|
|
800389a: b580 push {r7, lr}
|
|
800389c: b084 sub sp, #16
|
|
800389e: af00 add r7, sp, #0
|
|
80038a0: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
uint8_t tmp_pow_mode;
|
|
uint8_t pow_mode = 0;
|
|
80038a2: 2300 movs r3, #0
|
|
80038a4: 73bb strb r3, [r7, #14]
|
|
uint8_t reg_addr = BME680_CONF_T_P_MODE_ADDR;
|
|
80038a6: 2374 movs r3, #116 ; 0x74
|
|
80038a8: 733b strb r3, [r7, #12]
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
80038aa: 6878 ldr r0, [r7, #4]
|
|
80038ac: f000 ff34 bl 8004718 <null_ptr_check>
|
|
80038b0: 4603 mov r3, r0
|
|
80038b2: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
80038b4: f997 300f ldrsb.w r3, [r7, #15]
|
|
80038b8: 2b00 cmp r3, #0
|
|
80038ba: d14c bne.n 8003956 <bme680_set_sensor_mode+0xbc>
|
|
/* Call repeatedly until in sleep */
|
|
do {
|
|
rslt = bme680_get_regs(BME680_CONF_T_P_MODE_ADDR, &tmp_pow_mode, 1, dev);
|
|
80038bc: f107 010d add.w r1, r7, #13
|
|
80038c0: 687b ldr r3, [r7, #4]
|
|
80038c2: 2201 movs r2, #1
|
|
80038c4: 2074 movs r0, #116 ; 0x74
|
|
80038c6: f7ff fd0a bl 80032de <bme680_get_regs>
|
|
80038ca: 4603 mov r3, r0
|
|
80038cc: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
80038ce: f997 300f ldrsb.w r3, [r7, #15]
|
|
80038d2: 2b00 cmp r3, #0
|
|
80038d4: d119 bne.n 800390a <bme680_set_sensor_mode+0x70>
|
|
/* Put to sleep before changing mode */
|
|
pow_mode = (tmp_pow_mode & BME680_MODE_MSK);
|
|
80038d6: 7b7b ldrb r3, [r7, #13]
|
|
80038d8: f003 0303 and.w r3, r3, #3
|
|
80038dc: 73bb strb r3, [r7, #14]
|
|
|
|
if (pow_mode != BME680_SLEEP_MODE) {
|
|
80038de: 7bbb ldrb r3, [r7, #14]
|
|
80038e0: 2b00 cmp r3, #0
|
|
80038e2: d012 beq.n 800390a <bme680_set_sensor_mode+0x70>
|
|
tmp_pow_mode = tmp_pow_mode & (~BME680_MODE_MSK); /* Set to sleep */
|
|
80038e4: 7b7b ldrb r3, [r7, #13]
|
|
80038e6: f023 0303 bic.w r3, r3, #3
|
|
80038ea: b2db uxtb r3, r3
|
|
80038ec: 737b strb r3, [r7, #13]
|
|
rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev);
|
|
80038ee: f107 010d add.w r1, r7, #13
|
|
80038f2: f107 000c add.w r0, r7, #12
|
|
80038f6: 687b ldr r3, [r7, #4]
|
|
80038f8: 2201 movs r2, #1
|
|
80038fa: f7ff fd2f bl 800335c <bme680_set_regs>
|
|
80038fe: 4603 mov r3, r0
|
|
8003900: 73fb strb r3, [r7, #15]
|
|
dev->delay_ms(BME680_POLL_PERIOD_MS);
|
|
8003902: 687b ldr r3, [r7, #4]
|
|
8003904: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
8003906: 200a movs r0, #10
|
|
8003908: 4798 blx r3
|
|
}
|
|
}
|
|
} while (pow_mode != BME680_SLEEP_MODE);
|
|
800390a: 7bbb ldrb r3, [r7, #14]
|
|
800390c: 2b00 cmp r3, #0
|
|
800390e: d1d5 bne.n 80038bc <bme680_set_sensor_mode+0x22>
|
|
|
|
/* Already in sleep */
|
|
if (dev->power_mode != BME680_SLEEP_MODE) {
|
|
8003910: 687b ldr r3, [r7, #4]
|
|
8003912: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
8003916: 2b00 cmp r3, #0
|
|
8003918: d01d beq.n 8003956 <bme680_set_sensor_mode+0xbc>
|
|
tmp_pow_mode = (tmp_pow_mode & ~BME680_MODE_MSK) | (dev->power_mode & BME680_MODE_MSK);
|
|
800391a: 7b7b ldrb r3, [r7, #13]
|
|
800391c: b25b sxtb r3, r3
|
|
800391e: f023 0303 bic.w r3, r3, #3
|
|
8003922: b25a sxtb r2, r3
|
|
8003924: 687b ldr r3, [r7, #4]
|
|
8003926: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800392a: b25b sxtb r3, r3
|
|
800392c: f003 0303 and.w r3, r3, #3
|
|
8003930: b25b sxtb r3, r3
|
|
8003932: 4313 orrs r3, r2
|
|
8003934: b25b sxtb r3, r3
|
|
8003936: b2db uxtb r3, r3
|
|
8003938: 737b strb r3, [r7, #13]
|
|
if (rslt == BME680_OK)
|
|
800393a: f997 300f ldrsb.w r3, [r7, #15]
|
|
800393e: 2b00 cmp r3, #0
|
|
8003940: d109 bne.n 8003956 <bme680_set_sensor_mode+0xbc>
|
|
rslt = bme680_set_regs(®_addr, &tmp_pow_mode, 1, dev);
|
|
8003942: f107 010d add.w r1, r7, #13
|
|
8003946: f107 000c add.w r0, r7, #12
|
|
800394a: 687b ldr r3, [r7, #4]
|
|
800394c: 2201 movs r2, #1
|
|
800394e: f7ff fd05 bl 800335c <bme680_set_regs>
|
|
8003952: 4603 mov r3, r0
|
|
8003954: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
8003956: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
800395a: 4618 mov r0, r3
|
|
800395c: 3710 adds r7, #16
|
|
800395e: 46bd mov sp, r7
|
|
8003960: bd80 pop {r7, pc}
|
|
|
|
08003962 <bme680_get_profile_dur>:
|
|
|
|
/*!
|
|
* @brief This API is used to get the profile duration of the sensor.
|
|
*/
|
|
void bme680_get_profile_dur(uint16_t *duration, const struct bme680_dev *dev)
|
|
{
|
|
8003962: b480 push {r7}
|
|
8003964: b087 sub sp, #28
|
|
8003966: af00 add r7, sp, #0
|
|
8003968: 6078 str r0, [r7, #4]
|
|
800396a: 6039 str r1, [r7, #0]
|
|
uint32_t tph_dur; /* Calculate in us */
|
|
uint32_t meas_cycles;
|
|
uint8_t os_to_meas_cycles[6] = {0, 1, 2, 4, 8, 16};
|
|
800396c: f24e 3224 movw r2, #58148 ; 0xe324
|
|
8003970: f6c0 0200 movt r2, #2048 ; 0x800
|
|
8003974: f107 0308 add.w r3, r7, #8
|
|
8003978: e892 0003 ldmia.w r2, {r0, r1}
|
|
800397c: 6018 str r0, [r3, #0]
|
|
800397e: 3304 adds r3, #4
|
|
8003980: 8019 strh r1, [r3, #0]
|
|
|
|
meas_cycles = os_to_meas_cycles[dev->tph_sett.os_temp];
|
|
8003982: 683b ldr r3, [r7, #0]
|
|
8003984: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
|
|
8003988: f107 0218 add.w r2, r7, #24
|
|
800398c: 4413 add r3, r2
|
|
800398e: f813 3c10 ldrb.w r3, [r3, #-16]
|
|
8003992: 617b str r3, [r7, #20]
|
|
meas_cycles += os_to_meas_cycles[dev->tph_sett.os_pres];
|
|
8003994: 683b ldr r3, [r7, #0]
|
|
8003996: f893 303a ldrb.w r3, [r3, #58] ; 0x3a
|
|
800399a: f107 0218 add.w r2, r7, #24
|
|
800399e: 4413 add r3, r2
|
|
80039a0: f813 3c10 ldrb.w r3, [r3, #-16]
|
|
80039a4: 461a mov r2, r3
|
|
80039a6: 697b ldr r3, [r7, #20]
|
|
80039a8: 4413 add r3, r2
|
|
80039aa: 617b str r3, [r7, #20]
|
|
meas_cycles += os_to_meas_cycles[dev->tph_sett.os_hum];
|
|
80039ac: 683b ldr r3, [r7, #0]
|
|
80039ae: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
|
|
80039b2: f107 0218 add.w r2, r7, #24
|
|
80039b6: 4413 add r3, r2
|
|
80039b8: f813 3c10 ldrb.w r3, [r3, #-16]
|
|
80039bc: 461a mov r2, r3
|
|
80039be: 697b ldr r3, [r7, #20]
|
|
80039c0: 4413 add r3, r2
|
|
80039c2: 617b str r3, [r7, #20]
|
|
|
|
/* TPH measurement duration */
|
|
tph_dur = meas_cycles * UINT32_C(1963);
|
|
80039c4: 697b ldr r3, [r7, #20]
|
|
80039c6: f240 72ab movw r2, #1963 ; 0x7ab
|
|
80039ca: fb02 f303 mul.w r3, r2, r3
|
|
80039ce: 613b str r3, [r7, #16]
|
|
tph_dur += UINT32_C(477 * 4); /* TPH switching duration */
|
|
80039d0: 693b ldr r3, [r7, #16]
|
|
80039d2: f203 7374 addw r3, r3, #1908 ; 0x774
|
|
80039d6: 613b str r3, [r7, #16]
|
|
tph_dur += UINT32_C(477 * 5); /* Gas measurement duration */
|
|
80039d8: 693b ldr r3, [r7, #16]
|
|
80039da: f603 1351 addw r3, r3, #2385 ; 0x951
|
|
80039de: 613b str r3, [r7, #16]
|
|
tph_dur += UINT32_C(500); /* Get it to the closest whole number.*/
|
|
80039e0: 693b ldr r3, [r7, #16]
|
|
80039e2: f503 73fa add.w r3, r3, #500 ; 0x1f4
|
|
80039e6: 613b str r3, [r7, #16]
|
|
tph_dur /= UINT32_C(1000); /* Convert to ms */
|
|
80039e8: 693a ldr r2, [r7, #16]
|
|
80039ea: f644 53d3 movw r3, #19923 ; 0x4dd3
|
|
80039ee: f2c1 0362 movt r3, #4194 ; 0x1062
|
|
80039f2: fba3 2302 umull r2, r3, r3, r2
|
|
80039f6: 099b lsrs r3, r3, #6
|
|
80039f8: 613b str r3, [r7, #16]
|
|
|
|
tph_dur += UINT32_C(1); /* Wake up duration of 1ms */
|
|
80039fa: 693b ldr r3, [r7, #16]
|
|
80039fc: 3301 adds r3, #1
|
|
80039fe: 613b str r3, [r7, #16]
|
|
|
|
*duration = (uint16_t) tph_dur;
|
|
8003a00: 693b ldr r3, [r7, #16]
|
|
8003a02: b29a uxth r2, r3
|
|
8003a04: 687b ldr r3, [r7, #4]
|
|
8003a06: 801a strh r2, [r3, #0]
|
|
|
|
/* Get the gas duration only when the run gas is enabled */
|
|
if (dev->gas_sett.run_gas) {
|
|
8003a08: 683b ldr r3, [r7, #0]
|
|
8003a0a: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
|
|
8003a0e: 2b00 cmp r3, #0
|
|
8003a10: d008 beq.n 8003a24 <bme680_get_profile_dur+0xc2>
|
|
/* The remaining time should be used for heating */
|
|
*duration += dev->gas_sett.heatr_dur;
|
|
8003a12: 687b ldr r3, [r7, #4]
|
|
8003a14: 881a ldrh r2, [r3, #0]
|
|
8003a16: 683b ldr r3, [r7, #0]
|
|
8003a18: f8b3 3042 ldrh.w r3, [r3, #66] ; 0x42
|
|
8003a1c: 4413 add r3, r2
|
|
8003a1e: b29a uxth r2, r3
|
|
8003a20: 687b ldr r3, [r7, #4]
|
|
8003a22: 801a strh r2, [r3, #0]
|
|
}
|
|
}
|
|
8003a24: bf00 nop
|
|
8003a26: 371c adds r7, #28
|
|
8003a28: 46bd mov sp, r7
|
|
8003a2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003a2e: 4770 bx lr
|
|
|
|
08003a30 <bme680_get_sensor_data>:
|
|
* @brief This API reads the pressure, temperature and humidity and gas data
|
|
* from the sensor, compensates the data and store it in the bme680_data
|
|
* structure instance passed by the user.
|
|
*/
|
|
int8_t bme680_get_sensor_data(struct bme680_field_data *data, struct bme680_dev *dev)
|
|
{
|
|
8003a30: b580 push {r7, lr}
|
|
8003a32: b084 sub sp, #16
|
|
8003a34: af00 add r7, sp, #0
|
|
8003a36: 6078 str r0, [r7, #4]
|
|
8003a38: 6039 str r1, [r7, #0]
|
|
int8_t rslt;
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
8003a3a: 6838 ldr r0, [r7, #0]
|
|
8003a3c: f000 fe6c bl 8004718 <null_ptr_check>
|
|
8003a40: 4603 mov r3, r0
|
|
8003a42: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
8003a44: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003a48: 2b00 cmp r3, #0
|
|
8003a4a: d117 bne.n 8003a7c <bme680_get_sensor_data+0x4c>
|
|
/* Reading the sensor data in forced mode only */
|
|
rslt = read_field_data(data, dev);
|
|
8003a4c: 6839 ldr r1, [r7, #0]
|
|
8003a4e: 6878 ldr r0, [r7, #4]
|
|
8003a50: f000 fcd9 bl 8004406 <read_field_data>
|
|
8003a54: 4603 mov r3, r0
|
|
8003a56: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
8003a58: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003a5c: 2b00 cmp r3, #0
|
|
8003a5e: d10d bne.n 8003a7c <bme680_get_sensor_data+0x4c>
|
|
if (data->status & BME680_NEW_DATA_MSK)
|
|
8003a60: 687b ldr r3, [r7, #4]
|
|
8003a62: 781b ldrb r3, [r3, #0]
|
|
8003a64: b25b sxtb r3, r3
|
|
8003a66: 2b00 cmp r3, #0
|
|
8003a68: da04 bge.n 8003a74 <bme680_get_sensor_data+0x44>
|
|
dev->new_fields = 1;
|
|
8003a6a: 683b ldr r3, [r7, #0]
|
|
8003a6c: 2201 movs r2, #1
|
|
8003a6e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
8003a72: e003 b.n 8003a7c <bme680_get_sensor_data+0x4c>
|
|
else
|
|
dev->new_fields = 0;
|
|
8003a74: 683b ldr r3, [r7, #0]
|
|
8003a76: 2200 movs r2, #0
|
|
8003a78: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
8003a7c: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8003a80: 4618 mov r0, r3
|
|
8003a82: 3710 adds r7, #16
|
|
8003a84: 46bd mov sp, r7
|
|
8003a86: bd80 pop {r7, pc}
|
|
|
|
08003a88 <get_calib_data>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to read the calibrated data from the sensor.
|
|
*/
|
|
static int8_t get_calib_data(struct bme680_dev *dev)
|
|
{
|
|
8003a88: b580 push {r7, lr}
|
|
8003a8a: b08e sub sp, #56 ; 0x38
|
|
8003a8c: af00 add r7, sp, #0
|
|
8003a8e: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
uint8_t coeff_array[BME680_COEFF_SIZE] = { 0 };
|
|
8003a90: 2300 movs r3, #0
|
|
8003a92: 60fb str r3, [r7, #12]
|
|
8003a94: f107 0310 add.w r3, r7, #16
|
|
8003a98: 2225 movs r2, #37 ; 0x25
|
|
8003a9a: 2100 movs r1, #0
|
|
8003a9c: 4618 mov r0, r3
|
|
8003a9e: f007 fa6b bl 800af78 <memset>
|
|
uint8_t temp_var = 0; /* Temporary variable */
|
|
8003aa2: 2300 movs r3, #0
|
|
8003aa4: 72fb strb r3, [r7, #11]
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
8003aa6: 6878 ldr r0, [r7, #4]
|
|
8003aa8: f000 fe36 bl 8004718 <null_ptr_check>
|
|
8003aac: 4603 mov r3, r0
|
|
8003aae: f887 3037 strb.w r3, [r7, #55] ; 0x37
|
|
if (rslt == BME680_OK) {
|
|
8003ab2: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37
|
|
8003ab6: 2b00 cmp r3, #0
|
|
8003ab8: f040 810c bne.w 8003cd4 <get_calib_data+0x24c>
|
|
rslt = bme680_get_regs(BME680_COEFF_ADDR1, coeff_array, BME680_COEFF_ADDR1_LEN, dev);
|
|
8003abc: f107 010c add.w r1, r7, #12
|
|
8003ac0: 687b ldr r3, [r7, #4]
|
|
8003ac2: 2219 movs r2, #25
|
|
8003ac4: 2089 movs r0, #137 ; 0x89
|
|
8003ac6: f7ff fc0a bl 80032de <bme680_get_regs>
|
|
8003aca: 4603 mov r3, r0
|
|
8003acc: f887 3037 strb.w r3, [r7, #55] ; 0x37
|
|
/* Append the second half in the same array */
|
|
if (rslt == BME680_OK)
|
|
8003ad0: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37
|
|
8003ad4: 2b00 cmp r3, #0
|
|
8003ad6: d10b bne.n 8003af0 <get_calib_data+0x68>
|
|
rslt = bme680_get_regs(BME680_COEFF_ADDR2, &coeff_array[BME680_COEFF_ADDR1_LEN]
|
|
8003ad8: f107 030c add.w r3, r7, #12
|
|
8003adc: f103 0119 add.w r1, r3, #25
|
|
8003ae0: 687b ldr r3, [r7, #4]
|
|
8003ae2: 2210 movs r2, #16
|
|
8003ae4: 20e1 movs r0, #225 ; 0xe1
|
|
8003ae6: f7ff fbfa bl 80032de <bme680_get_regs>
|
|
8003aea: 4603 mov r3, r0
|
|
8003aec: f887 3037 strb.w r3, [r7, #55] ; 0x37
|
|
, BME680_COEFF_ADDR2_LEN, dev);
|
|
|
|
/* Temperature related coefficients */
|
|
dev->calib.par_t1 = (uint16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_T1_MSB_REG],
|
|
8003af0: f897 302e ldrb.w r3, [r7, #46] ; 0x2e
|
|
8003af4: 021b lsls r3, r3, #8
|
|
8003af6: b21a sxth r2, r3
|
|
8003af8: f897 302d ldrb.w r3, [r7, #45] ; 0x2d
|
|
8003afc: b21b sxth r3, r3
|
|
8003afe: 4313 orrs r3, r2
|
|
8003b00: b21b sxth r3, r3
|
|
8003b02: b29a uxth r2, r3
|
|
8003b04: 687b ldr r3, [r7, #4]
|
|
8003b06: 82da strh r2, [r3, #22]
|
|
coeff_array[BME680_T1_LSB_REG]));
|
|
dev->calib.par_t2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_T2_MSB_REG],
|
|
8003b08: 7bbb ldrb r3, [r7, #14]
|
|
8003b0a: 021b lsls r3, r3, #8
|
|
8003b0c: b21a sxth r2, r3
|
|
8003b0e: 7b7b ldrb r3, [r7, #13]
|
|
8003b10: b21b sxth r3, r3
|
|
8003b12: 4313 orrs r3, r2
|
|
8003b14: b21a sxth r2, r3
|
|
8003b16: 687b ldr r3, [r7, #4]
|
|
8003b18: 831a strh r2, [r3, #24]
|
|
coeff_array[BME680_T2_LSB_REG]));
|
|
dev->calib.par_t3 = (int8_t) (coeff_array[BME680_T3_REG]);
|
|
8003b1a: 7bfb ldrb r3, [r7, #15]
|
|
8003b1c: b25a sxtb r2, r3
|
|
8003b1e: 687b ldr r3, [r7, #4]
|
|
8003b20: 769a strb r2, [r3, #26]
|
|
|
|
/* Pressure related coefficients */
|
|
dev->calib.par_p1 = (uint16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P1_MSB_REG],
|
|
8003b22: 7cbb ldrb r3, [r7, #18]
|
|
8003b24: 021b lsls r3, r3, #8
|
|
8003b26: b21a sxth r2, r3
|
|
8003b28: 7c7b ldrb r3, [r7, #17]
|
|
8003b2a: b21b sxth r3, r3
|
|
8003b2c: 4313 orrs r3, r2
|
|
8003b2e: b21b sxth r3, r3
|
|
8003b30: b29a uxth r2, r3
|
|
8003b32: 687b ldr r3, [r7, #4]
|
|
8003b34: 839a strh r2, [r3, #28]
|
|
coeff_array[BME680_P1_LSB_REG]));
|
|
dev->calib.par_p2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P2_MSB_REG],
|
|
8003b36: 7d3b ldrb r3, [r7, #20]
|
|
8003b38: 021b lsls r3, r3, #8
|
|
8003b3a: b21a sxth r2, r3
|
|
8003b3c: 7cfb ldrb r3, [r7, #19]
|
|
8003b3e: b21b sxth r3, r3
|
|
8003b40: 4313 orrs r3, r2
|
|
8003b42: b21a sxth r2, r3
|
|
8003b44: 687b ldr r3, [r7, #4]
|
|
8003b46: 83da strh r2, [r3, #30]
|
|
coeff_array[BME680_P2_LSB_REG]));
|
|
dev->calib.par_p3 = (int8_t) coeff_array[BME680_P3_REG];
|
|
8003b48: 7d7b ldrb r3, [r7, #21]
|
|
8003b4a: b25a sxtb r2, r3
|
|
8003b4c: 687b ldr r3, [r7, #4]
|
|
8003b4e: f883 2020 strb.w r2, [r3, #32]
|
|
dev->calib.par_p4 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P4_MSB_REG],
|
|
8003b52: 7e3b ldrb r3, [r7, #24]
|
|
8003b54: 021b lsls r3, r3, #8
|
|
8003b56: b21a sxth r2, r3
|
|
8003b58: 7dfb ldrb r3, [r7, #23]
|
|
8003b5a: b21b sxth r3, r3
|
|
8003b5c: 4313 orrs r3, r2
|
|
8003b5e: b21a sxth r2, r3
|
|
8003b60: 687b ldr r3, [r7, #4]
|
|
8003b62: 845a strh r2, [r3, #34] ; 0x22
|
|
coeff_array[BME680_P4_LSB_REG]));
|
|
dev->calib.par_p5 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P5_MSB_REG],
|
|
8003b64: 7ebb ldrb r3, [r7, #26]
|
|
8003b66: 021b lsls r3, r3, #8
|
|
8003b68: b21a sxth r2, r3
|
|
8003b6a: 7e7b ldrb r3, [r7, #25]
|
|
8003b6c: b21b sxth r3, r3
|
|
8003b6e: 4313 orrs r3, r2
|
|
8003b70: b21a sxth r2, r3
|
|
8003b72: 687b ldr r3, [r7, #4]
|
|
8003b74: 849a strh r2, [r3, #36] ; 0x24
|
|
coeff_array[BME680_P5_LSB_REG]));
|
|
dev->calib.par_p6 = (int8_t) (coeff_array[BME680_P6_REG]);
|
|
8003b76: 7f3b ldrb r3, [r7, #28]
|
|
8003b78: b25a sxtb r2, r3
|
|
8003b7a: 687b ldr r3, [r7, #4]
|
|
8003b7c: f883 2026 strb.w r2, [r3, #38] ; 0x26
|
|
dev->calib.par_p7 = (int8_t) (coeff_array[BME680_P7_REG]);
|
|
8003b80: 7efb ldrb r3, [r7, #27]
|
|
8003b82: b25a sxtb r2, r3
|
|
8003b84: 687b ldr r3, [r7, #4]
|
|
8003b86: f883 2027 strb.w r2, [r3, #39] ; 0x27
|
|
dev->calib.par_p8 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P8_MSB_REG],
|
|
8003b8a: f897 3020 ldrb.w r3, [r7, #32]
|
|
8003b8e: 021b lsls r3, r3, #8
|
|
8003b90: b21a sxth r2, r3
|
|
8003b92: 7ffb ldrb r3, [r7, #31]
|
|
8003b94: b21b sxth r3, r3
|
|
8003b96: 4313 orrs r3, r2
|
|
8003b98: b21a sxth r2, r3
|
|
8003b9a: 687b ldr r3, [r7, #4]
|
|
8003b9c: 851a strh r2, [r3, #40] ; 0x28
|
|
coeff_array[BME680_P8_LSB_REG]));
|
|
dev->calib.par_p9 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_P9_MSB_REG],
|
|
8003b9e: f897 3022 ldrb.w r3, [r7, #34] ; 0x22
|
|
8003ba2: 021b lsls r3, r3, #8
|
|
8003ba4: b21a sxth r2, r3
|
|
8003ba6: f897 3021 ldrb.w r3, [r7, #33] ; 0x21
|
|
8003baa: b21b sxth r3, r3
|
|
8003bac: 4313 orrs r3, r2
|
|
8003bae: b21a sxth r2, r3
|
|
8003bb0: 687b ldr r3, [r7, #4]
|
|
8003bb2: 855a strh r2, [r3, #42] ; 0x2a
|
|
coeff_array[BME680_P9_LSB_REG]));
|
|
dev->calib.par_p10 = (uint8_t) (coeff_array[BME680_P10_REG]);
|
|
8003bb4: f897 2023 ldrb.w r2, [r7, #35] ; 0x23
|
|
8003bb8: 687b ldr r3, [r7, #4]
|
|
8003bba: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
|
|
/* Humidity related coefficients */
|
|
dev->calib.par_h1 = (uint16_t) (((uint16_t) coeff_array[BME680_H1_MSB_REG] << BME680_HUM_REG_SHIFT_VAL)
|
|
8003bbe: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8003bc2: 011b lsls r3, r3, #4
|
|
| (coeff_array[BME680_H1_LSB_REG] & BME680_BIT_H1_DATA_MSK));
|
|
8003bc4: b21a sxth r2, r3
|
|
8003bc6: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8003bca: b21b sxth r3, r3
|
|
8003bcc: f003 030f and.w r3, r3, #15
|
|
8003bd0: b21b sxth r3, r3
|
|
8003bd2: 4313 orrs r3, r2
|
|
8003bd4: b21b sxth r3, r3
|
|
dev->calib.par_h1 = (uint16_t) (((uint16_t) coeff_array[BME680_H1_MSB_REG] << BME680_HUM_REG_SHIFT_VAL)
|
|
8003bd6: b29a uxth r2, r3
|
|
8003bd8: 687b ldr r3, [r7, #4]
|
|
8003bda: 811a strh r2, [r3, #8]
|
|
dev->calib.par_h2 = (uint16_t) (((uint16_t) coeff_array[BME680_H2_MSB_REG] << BME680_HUM_REG_SHIFT_VAL)
|
|
8003bdc: f897 3025 ldrb.w r3, [r7, #37] ; 0x25
|
|
8003be0: 011b lsls r3, r3, #4
|
|
| ((coeff_array[BME680_H2_LSB_REG]) >> BME680_HUM_REG_SHIFT_VAL));
|
|
8003be2: b21a sxth r2, r3
|
|
8003be4: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8003be8: 091b lsrs r3, r3, #4
|
|
8003bea: b2db uxtb r3, r3
|
|
8003bec: b21b sxth r3, r3
|
|
8003bee: 4313 orrs r3, r2
|
|
8003bf0: b21b sxth r3, r3
|
|
dev->calib.par_h2 = (uint16_t) (((uint16_t) coeff_array[BME680_H2_MSB_REG] << BME680_HUM_REG_SHIFT_VAL)
|
|
8003bf2: b29a uxth r2, r3
|
|
8003bf4: 687b ldr r3, [r7, #4]
|
|
8003bf6: 815a strh r2, [r3, #10]
|
|
dev->calib.par_h3 = (int8_t) coeff_array[BME680_H3_REG];
|
|
8003bf8: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
|
|
8003bfc: b25a sxtb r2, r3
|
|
8003bfe: 687b ldr r3, [r7, #4]
|
|
8003c00: 731a strb r2, [r3, #12]
|
|
dev->calib.par_h4 = (int8_t) coeff_array[BME680_H4_REG];
|
|
8003c02: f897 3029 ldrb.w r3, [r7, #41] ; 0x29
|
|
8003c06: b25a sxtb r2, r3
|
|
8003c08: 687b ldr r3, [r7, #4]
|
|
8003c0a: 735a strb r2, [r3, #13]
|
|
dev->calib.par_h5 = (int8_t) coeff_array[BME680_H5_REG];
|
|
8003c0c: f897 302a ldrb.w r3, [r7, #42] ; 0x2a
|
|
8003c10: b25a sxtb r2, r3
|
|
8003c12: 687b ldr r3, [r7, #4]
|
|
8003c14: 739a strb r2, [r3, #14]
|
|
dev->calib.par_h6 = (uint8_t) coeff_array[BME680_H6_REG];
|
|
8003c16: f897 202b ldrb.w r2, [r7, #43] ; 0x2b
|
|
8003c1a: 687b ldr r3, [r7, #4]
|
|
8003c1c: 73da strb r2, [r3, #15]
|
|
dev->calib.par_h7 = (int8_t) coeff_array[BME680_H7_REG];
|
|
8003c1e: f897 302c ldrb.w r3, [r7, #44] ; 0x2c
|
|
8003c22: b25a sxtb r2, r3
|
|
8003c24: 687b ldr r3, [r7, #4]
|
|
8003c26: 741a strb r2, [r3, #16]
|
|
|
|
/* Gas heater related coefficients */
|
|
dev->calib.par_gh1 = (int8_t) coeff_array[BME680_GH1_REG];
|
|
8003c28: f897 3031 ldrb.w r3, [r7, #49] ; 0x31
|
|
8003c2c: b25a sxtb r2, r3
|
|
8003c2e: 687b ldr r3, [r7, #4]
|
|
8003c30: 745a strb r2, [r3, #17]
|
|
dev->calib.par_gh2 = (int16_t) (BME680_CONCAT_BYTES(coeff_array[BME680_GH2_MSB_REG],
|
|
8003c32: f897 3030 ldrb.w r3, [r7, #48] ; 0x30
|
|
8003c36: 021b lsls r3, r3, #8
|
|
8003c38: b21a sxth r2, r3
|
|
8003c3a: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
|
|
8003c3e: b21b sxth r3, r3
|
|
8003c40: 4313 orrs r3, r2
|
|
8003c42: b21a sxth r2, r3
|
|
8003c44: 687b ldr r3, [r7, #4]
|
|
8003c46: 825a strh r2, [r3, #18]
|
|
coeff_array[BME680_GH2_LSB_REG]));
|
|
dev->calib.par_gh3 = (int8_t) coeff_array[BME680_GH3_REG];
|
|
8003c48: f897 3032 ldrb.w r3, [r7, #50] ; 0x32
|
|
8003c4c: b25a sxtb r2, r3
|
|
8003c4e: 687b ldr r3, [r7, #4]
|
|
8003c50: 751a strb r2, [r3, #20]
|
|
|
|
/* Other coefficients */
|
|
if (rslt == BME680_OK) {
|
|
8003c52: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37
|
|
8003c56: 2b00 cmp r3, #0
|
|
8003c58: d135 bne.n 8003cc6 <get_calib_data+0x23e>
|
|
rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_RANGE_ADDR, &temp_var, 1, dev);
|
|
8003c5a: f107 010b add.w r1, r7, #11
|
|
8003c5e: 687b ldr r3, [r7, #4]
|
|
8003c60: 2201 movs r2, #1
|
|
8003c62: 2002 movs r0, #2
|
|
8003c64: f7ff fb3b bl 80032de <bme680_get_regs>
|
|
8003c68: 4603 mov r3, r0
|
|
8003c6a: f887 3037 strb.w r3, [r7, #55] ; 0x37
|
|
|
|
dev->calib.res_heat_range = ((temp_var & BME680_RHRANGE_MSK) / 16);
|
|
8003c6e: 7afb ldrb r3, [r7, #11]
|
|
8003c70: f003 0330 and.w r3, r3, #48 ; 0x30
|
|
8003c74: 2b00 cmp r3, #0
|
|
8003c76: da00 bge.n 8003c7a <get_calib_data+0x1f2>
|
|
8003c78: 330f adds r3, #15
|
|
8003c7a: 111b asrs r3, r3, #4
|
|
8003c7c: b2da uxtb r2, r3
|
|
8003c7e: 687b ldr r3, [r7, #4]
|
|
8003c80: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
if (rslt == BME680_OK) {
|
|
8003c84: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37
|
|
8003c88: 2b00 cmp r3, #0
|
|
8003c8a: d11c bne.n 8003cc6 <get_calib_data+0x23e>
|
|
rslt = bme680_get_regs(BME680_ADDR_RES_HEAT_VAL_ADDR, &temp_var, 1, dev);
|
|
8003c8c: f107 010b add.w r1, r7, #11
|
|
8003c90: 687b ldr r3, [r7, #4]
|
|
8003c92: 2201 movs r2, #1
|
|
8003c94: 2000 movs r0, #0
|
|
8003c96: f7ff fb22 bl 80032de <bme680_get_regs>
|
|
8003c9a: 4603 mov r3, r0
|
|
8003c9c: f887 3037 strb.w r3, [r7, #55] ; 0x37
|
|
|
|
dev->calib.res_heat_val = (int8_t) temp_var;
|
|
8003ca0: 7afb ldrb r3, [r7, #11]
|
|
8003ca2: b25a sxtb r2, r3
|
|
8003ca4: 687b ldr r3, [r7, #4]
|
|
8003ca6: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
if (rslt == BME680_OK)
|
|
8003caa: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37
|
|
8003cae: 2b00 cmp r3, #0
|
|
8003cb0: d109 bne.n 8003cc6 <get_calib_data+0x23e>
|
|
rslt = bme680_get_regs(BME680_ADDR_RANGE_SW_ERR_ADDR, &temp_var, 1, dev);
|
|
8003cb2: f107 010b add.w r1, r7, #11
|
|
8003cb6: 687b ldr r3, [r7, #4]
|
|
8003cb8: 2201 movs r2, #1
|
|
8003cba: 2004 movs r0, #4
|
|
8003cbc: f7ff fb0f bl 80032de <bme680_get_regs>
|
|
8003cc0: 4603 mov r3, r0
|
|
8003cc2: f887 3037 strb.w r3, [r7, #55] ; 0x37
|
|
}
|
|
}
|
|
dev->calib.range_sw_err = ((int8_t) temp_var & (int8_t) BME680_RSERROR_MSK) / 16;
|
|
8003cc6: 7afb ldrb r3, [r7, #11]
|
|
8003cc8: b25b sxtb r3, r3
|
|
8003cca: 111b asrs r3, r3, #4
|
|
8003ccc: b25a sxtb r2, r3
|
|
8003cce: 687b ldr r3, [r7, #4]
|
|
8003cd0: f883 2036 strb.w r2, [r3, #54] ; 0x36
|
|
}
|
|
|
|
return rslt;
|
|
8003cd4: f997 3037 ldrsb.w r3, [r7, #55] ; 0x37
|
|
}
|
|
8003cd8: 4618 mov r0, r3
|
|
8003cda: 3738 adds r7, #56 ; 0x38
|
|
8003cdc: 46bd mov sp, r7
|
|
8003cde: bd80 pop {r7, pc}
|
|
|
|
08003ce0 <set_gas_config>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to set the gas configuration of the sensor.
|
|
*/
|
|
static int8_t set_gas_config(struct bme680_dev *dev)
|
|
{
|
|
8003ce0: b580 push {r7, lr}
|
|
8003ce2: b084 sub sp, #16
|
|
8003ce4: af00 add r7, sp, #0
|
|
8003ce6: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
8003ce8: 6878 ldr r0, [r7, #4]
|
|
8003cea: f000 fd15 bl 8004718 <null_ptr_check>
|
|
8003cee: 4603 mov r3, r0
|
|
8003cf0: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
8003cf2: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003cf6: 2b00 cmp r3, #0
|
|
8003cf8: d132 bne.n 8003d60 <set_gas_config+0x80>
|
|
|
|
uint8_t reg_addr[2] = {0};
|
|
8003cfa: 2300 movs r3, #0
|
|
8003cfc: 81bb strh r3, [r7, #12]
|
|
uint8_t reg_data[2] = {0};
|
|
8003cfe: 2300 movs r3, #0
|
|
8003d00: 813b strh r3, [r7, #8]
|
|
|
|
if (dev->power_mode == BME680_FORCED_MODE) {
|
|
8003d02: 687b ldr r3, [r7, #4]
|
|
8003d04: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
8003d08: 2b01 cmp r3, #1
|
|
8003d0a: d119 bne.n 8003d40 <set_gas_config+0x60>
|
|
reg_addr[0] = BME680_RES_HEAT0_ADDR;
|
|
8003d0c: 235a movs r3, #90 ; 0x5a
|
|
8003d0e: 733b strb r3, [r7, #12]
|
|
reg_data[0] = calc_heater_res(dev->gas_sett.heatr_temp, dev);
|
|
8003d10: 687b ldr r3, [r7, #4]
|
|
8003d12: f8b3 3040 ldrh.w r3, [r3, #64] ; 0x40
|
|
8003d16: 6879 ldr r1, [r7, #4]
|
|
8003d18: 4618 mov r0, r3
|
|
8003d1a: f000 facd bl 80042b8 <calc_heater_res>
|
|
8003d1e: 4603 mov r3, r0
|
|
8003d20: 723b strb r3, [r7, #8]
|
|
reg_addr[1] = BME680_GAS_WAIT0_ADDR;
|
|
8003d22: 2364 movs r3, #100 ; 0x64
|
|
8003d24: 737b strb r3, [r7, #13]
|
|
reg_data[1] = calc_heater_dur(dev->gas_sett.heatr_dur);
|
|
8003d26: 687b ldr r3, [r7, #4]
|
|
8003d28: f8b3 3042 ldrh.w r3, [r3, #66] ; 0x42
|
|
8003d2c: 4618 mov r0, r3
|
|
8003d2e: f000 fb45 bl 80043bc <calc_heater_dur>
|
|
8003d32: 4603 mov r3, r0
|
|
8003d34: 727b strb r3, [r7, #9]
|
|
dev->gas_sett.nb_conv = 0;
|
|
8003d36: 687b ldr r3, [r7, #4]
|
|
8003d38: 2200 movs r2, #0
|
|
8003d3a: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
8003d3e: e001 b.n 8003d44 <set_gas_config+0x64>
|
|
} else {
|
|
rslt = BME680_W_DEFINE_PWR_MODE;
|
|
8003d40: 2301 movs r3, #1
|
|
8003d42: 73fb strb r3, [r7, #15]
|
|
}
|
|
if (rslt == BME680_OK)
|
|
8003d44: f997 300f ldrsb.w r3, [r7, #15]
|
|
8003d48: 2b00 cmp r3, #0
|
|
8003d4a: d109 bne.n 8003d60 <set_gas_config+0x80>
|
|
rslt = bme680_set_regs(reg_addr, reg_data, 2, dev);
|
|
8003d4c: f107 0108 add.w r1, r7, #8
|
|
8003d50: f107 000c add.w r0, r7, #12
|
|
8003d54: 687b ldr r3, [r7, #4]
|
|
8003d56: 2202 movs r2, #2
|
|
8003d58: f7ff fb00 bl 800335c <bme680_set_regs>
|
|
8003d5c: 4603 mov r3, r0
|
|
8003d5e: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return rslt;
|
|
8003d60: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8003d64: 4618 mov r0, r3
|
|
8003d66: 3710 adds r7, #16
|
|
8003d68: 46bd mov sp, r7
|
|
8003d6a: bd80 pop {r7, pc}
|
|
|
|
08003d6c <calc_temperature>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to calculate the temperature value.
|
|
*/
|
|
static int16_t calc_temperature(uint32_t temp_adc, struct bme680_dev *dev)
|
|
{
|
|
8003d6c: b4b0 push {r4, r5, r7}
|
|
8003d6e: b08b sub sp, #44 ; 0x2c
|
|
8003d70: af00 add r7, sp, #0
|
|
8003d72: 6078 str r0, [r7, #4]
|
|
8003d74: 6039 str r1, [r7, #0]
|
|
int64_t var1;
|
|
int64_t var2;
|
|
int64_t var3;
|
|
int16_t calc_temp;
|
|
|
|
var1 = ((int32_t) temp_adc >> 3) - ((int32_t) dev->calib.par_t1 << 1);
|
|
8003d76: 687b ldr r3, [r7, #4]
|
|
8003d78: 10da asrs r2, r3, #3
|
|
8003d7a: 683b ldr r3, [r7, #0]
|
|
8003d7c: 8adb ldrh r3, [r3, #22]
|
|
8003d7e: 005b lsls r3, r3, #1
|
|
8003d80: 1ad3 subs r3, r2, r3
|
|
8003d82: 461a mov r2, r3
|
|
8003d84: ea4f 73e2 mov.w r3, r2, asr #31
|
|
8003d88: e9c7 2308 strd r2, r3, [r7, #32]
|
|
var2 = (var1 * (int32_t) dev->calib.par_t2) >> 11;
|
|
8003d8c: 683b ldr r3, [r7, #0]
|
|
8003d8e: f9b3 3018 ldrsh.w r3, [r3, #24]
|
|
8003d92: b21a sxth r2, r3
|
|
8003d94: ea4f 73e2 mov.w r3, r2, asr #31
|
|
8003d98: 6a39 ldr r1, [r7, #32]
|
|
8003d9a: fb03 f001 mul.w r0, r3, r1
|
|
8003d9e: 6a79 ldr r1, [r7, #36] ; 0x24
|
|
8003da0: fb02 f101 mul.w r1, r2, r1
|
|
8003da4: 1844 adds r4, r0, r1
|
|
8003da6: 6a39 ldr r1, [r7, #32]
|
|
8003da8: fba1 0102 umull r0, r1, r1, r2
|
|
8003dac: 1863 adds r3, r4, r1
|
|
8003dae: 4619 mov r1, r3
|
|
8003db0: f04f 0200 mov.w r2, #0
|
|
8003db4: f04f 0300 mov.w r3, #0
|
|
8003db8: 0ac2 lsrs r2, r0, #11
|
|
8003dba: ea42 5241 orr.w r2, r2, r1, lsl #21
|
|
8003dbe: 12cb asrs r3, r1, #11
|
|
8003dc0: e9c7 2306 strd r2, r3, [r7, #24]
|
|
var3 = ((var1 >> 1) * (var1 >> 1)) >> 12;
|
|
8003dc4: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
8003dc8: f04f 0000 mov.w r0, #0
|
|
8003dcc: f04f 0100 mov.w r1, #0
|
|
8003dd0: 0850 lsrs r0, r2, #1
|
|
8003dd2: ea40 70c3 orr.w r0, r0, r3, lsl #31
|
|
8003dd6: 1059 asrs r1, r3, #1
|
|
8003dd8: e9d7 4508 ldrd r4, r5, [r7, #32]
|
|
8003ddc: f04f 0200 mov.w r2, #0
|
|
8003de0: f04f 0300 mov.w r3, #0
|
|
8003de4: 0862 lsrs r2, r4, #1
|
|
8003de6: ea42 72c5 orr.w r2, r2, r5, lsl #31
|
|
8003dea: 106b asrs r3, r5, #1
|
|
8003dec: fb02 f501 mul.w r5, r2, r1
|
|
8003df0: fb00 f403 mul.w r4, r0, r3
|
|
8003df4: 442c add r4, r5
|
|
8003df6: fba0 0102 umull r0, r1, r0, r2
|
|
8003dfa: 1863 adds r3, r4, r1
|
|
8003dfc: 4619 mov r1, r3
|
|
8003dfe: f04f 0200 mov.w r2, #0
|
|
8003e02: f04f 0300 mov.w r3, #0
|
|
8003e06: 0b02 lsrs r2, r0, #12
|
|
8003e08: ea42 5201 orr.w r2, r2, r1, lsl #20
|
|
8003e0c: 130b asrs r3, r1, #12
|
|
8003e0e: e9c7 2304 strd r2, r3, [r7, #16]
|
|
var3 = ((var3) * ((int32_t) dev->calib.par_t3 << 4)) >> 14;
|
|
8003e12: 683b ldr r3, [r7, #0]
|
|
8003e14: f993 301a ldrsb.w r3, [r3, #26]
|
|
8003e18: 011b lsls r3, r3, #4
|
|
8003e1a: 461a mov r2, r3
|
|
8003e1c: ea4f 73e2 mov.w r3, r2, asr #31
|
|
8003e20: 6939 ldr r1, [r7, #16]
|
|
8003e22: fb03 f001 mul.w r0, r3, r1
|
|
8003e26: 6979 ldr r1, [r7, #20]
|
|
8003e28: fb02 f101 mul.w r1, r2, r1
|
|
8003e2c: 1844 adds r4, r0, r1
|
|
8003e2e: 6939 ldr r1, [r7, #16]
|
|
8003e30: fba1 0102 umull r0, r1, r1, r2
|
|
8003e34: 1863 adds r3, r4, r1
|
|
8003e36: 4619 mov r1, r3
|
|
8003e38: f04f 0200 mov.w r2, #0
|
|
8003e3c: f04f 0300 mov.w r3, #0
|
|
8003e40: 0b82 lsrs r2, r0, #14
|
|
8003e42: ea42 4281 orr.w r2, r2, r1, lsl #18
|
|
8003e46: 138b asrs r3, r1, #14
|
|
8003e48: e9c7 2304 strd r2, r3, [r7, #16]
|
|
dev->calib.t_fine = (int32_t) (var2 + var3);
|
|
8003e4c: 69ba ldr r2, [r7, #24]
|
|
8003e4e: 693b ldr r3, [r7, #16]
|
|
8003e50: 4413 add r3, r2
|
|
8003e52: 461a mov r2, r3
|
|
8003e54: 683b ldr r3, [r7, #0]
|
|
8003e56: 631a str r2, [r3, #48] ; 0x30
|
|
calc_temp = (int16_t) (((dev->calib.t_fine * 5) + 128) >> 8);
|
|
8003e58: 683b ldr r3, [r7, #0]
|
|
8003e5a: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
8003e5c: 4613 mov r3, r2
|
|
8003e5e: 009b lsls r3, r3, #2
|
|
8003e60: 4413 add r3, r2
|
|
8003e62: 3380 adds r3, #128 ; 0x80
|
|
8003e64: 121b asrs r3, r3, #8
|
|
8003e66: 81fb strh r3, [r7, #14]
|
|
|
|
return calc_temp;
|
|
8003e68: f9b7 300e ldrsh.w r3, [r7, #14]
|
|
}
|
|
8003e6c: 4618 mov r0, r3
|
|
8003e6e: 372c adds r7, #44 ; 0x2c
|
|
8003e70: 46bd mov sp, r7
|
|
8003e72: bcb0 pop {r4, r5, r7}
|
|
8003e74: 4770 bx lr
|
|
|
|
08003e76 <calc_pressure>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to calculate the pressure value.
|
|
*/
|
|
static uint32_t calc_pressure(uint32_t pres_adc, const struct bme680_dev *dev)
|
|
{
|
|
8003e76: b480 push {r7}
|
|
8003e78: b087 sub sp, #28
|
|
8003e7a: af00 add r7, sp, #0
|
|
8003e7c: 6078 str r0, [r7, #4]
|
|
8003e7e: 6039 str r1, [r7, #0]
|
|
int32_t var1;
|
|
int32_t var2;
|
|
int32_t var3;
|
|
int32_t pressure_comp;
|
|
|
|
var1 = (((int32_t)dev->calib.t_fine) >> 1) - 64000;
|
|
8003e80: 683b ldr r3, [r7, #0]
|
|
8003e82: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e84: 105b asrs r3, r3, #1
|
|
8003e86: f5a3 437a sub.w r3, r3, #64000 ; 0xfa00
|
|
8003e8a: 613b str r3, [r7, #16]
|
|
var2 = ((((var1 >> 2) * (var1 >> 2)) >> 11) *
|
|
8003e8c: 693b ldr r3, [r7, #16]
|
|
8003e8e: 109b asrs r3, r3, #2
|
|
8003e90: 693a ldr r2, [r7, #16]
|
|
8003e92: 1092 asrs r2, r2, #2
|
|
8003e94: fb02 f303 mul.w r3, r2, r3
|
|
8003e98: 12db asrs r3, r3, #11
|
|
(int32_t)dev->calib.par_p6) >> 2;
|
|
8003e9a: 683a ldr r2, [r7, #0]
|
|
8003e9c: f992 2026 ldrsb.w r2, [r2, #38] ; 0x26
|
|
var2 = ((((var1 >> 2) * (var1 >> 2)) >> 11) *
|
|
8003ea0: fb02 f303 mul.w r3, r2, r3
|
|
8003ea4: 109b asrs r3, r3, #2
|
|
8003ea6: 60fb str r3, [r7, #12]
|
|
var2 = var2 + ((var1 * (int32_t)dev->calib.par_p5) << 1);
|
|
8003ea8: 683b ldr r3, [r7, #0]
|
|
8003eaa: f9b3 3024 ldrsh.w r3, [r3, #36] ; 0x24
|
|
8003eae: 461a mov r2, r3
|
|
8003eb0: 693b ldr r3, [r7, #16]
|
|
8003eb2: fb03 f302 mul.w r3, r3, r2
|
|
8003eb6: 005b lsls r3, r3, #1
|
|
8003eb8: 68fa ldr r2, [r7, #12]
|
|
8003eba: 4413 add r3, r2
|
|
8003ebc: 60fb str r3, [r7, #12]
|
|
var2 = (var2 >> 2) + ((int32_t)dev->calib.par_p4 << 16);
|
|
8003ebe: 68fb ldr r3, [r7, #12]
|
|
8003ec0: 109a asrs r2, r3, #2
|
|
8003ec2: 683b ldr r3, [r7, #0]
|
|
8003ec4: f9b3 3022 ldrsh.w r3, [r3, #34] ; 0x22
|
|
8003ec8: 041b lsls r3, r3, #16
|
|
8003eca: 4413 add r3, r2
|
|
8003ecc: 60fb str r3, [r7, #12]
|
|
var1 = (((((var1 >> 2) * (var1 >> 2)) >> 13) *
|
|
8003ece: 693b ldr r3, [r7, #16]
|
|
8003ed0: 109b asrs r3, r3, #2
|
|
8003ed2: 693a ldr r2, [r7, #16]
|
|
8003ed4: 1092 asrs r2, r2, #2
|
|
8003ed6: fb02 f303 mul.w r3, r2, r3
|
|
8003eda: 135b asrs r3, r3, #13
|
|
((int32_t)dev->calib.par_p3 << 5)) >> 3) +
|
|
8003edc: 683a ldr r2, [r7, #0]
|
|
8003ede: f992 2020 ldrsb.w r2, [r2, #32]
|
|
8003ee2: 0152 lsls r2, r2, #5
|
|
var1 = (((((var1 >> 2) * (var1 >> 2)) >> 13) *
|
|
8003ee4: fb02 f303 mul.w r3, r2, r3
|
|
((int32_t)dev->calib.par_p3 << 5)) >> 3) +
|
|
8003ee8: 10da asrs r2, r3, #3
|
|
(((int32_t)dev->calib.par_p2 * var1) >> 1);
|
|
8003eea: 683b ldr r3, [r7, #0]
|
|
8003eec: f9b3 301e ldrsh.w r3, [r3, #30]
|
|
8003ef0: 4619 mov r1, r3
|
|
8003ef2: 693b ldr r3, [r7, #16]
|
|
8003ef4: fb03 f301 mul.w r3, r3, r1
|
|
8003ef8: 105b asrs r3, r3, #1
|
|
var1 = (((((var1 >> 2) * (var1 >> 2)) >> 13) *
|
|
8003efa: 4413 add r3, r2
|
|
8003efc: 613b str r3, [r7, #16]
|
|
var1 = var1 >> 18;
|
|
8003efe: 693b ldr r3, [r7, #16]
|
|
8003f00: 149b asrs r3, r3, #18
|
|
8003f02: 613b str r3, [r7, #16]
|
|
var1 = ((32768 + var1) * (int32_t)dev->calib.par_p1) >> 15;
|
|
8003f04: 693b ldr r3, [r7, #16]
|
|
8003f06: f503 4300 add.w r3, r3, #32768 ; 0x8000
|
|
8003f0a: 683a ldr r2, [r7, #0]
|
|
8003f0c: 8b92 ldrh r2, [r2, #28]
|
|
8003f0e: fb02 f303 mul.w r3, r2, r3
|
|
8003f12: 13db asrs r3, r3, #15
|
|
8003f14: 613b str r3, [r7, #16]
|
|
pressure_comp = 1048576 - pres_adc;
|
|
8003f16: 687b ldr r3, [r7, #4]
|
|
8003f18: f5c3 1380 rsb r3, r3, #1048576 ; 0x100000
|
|
8003f1c: 617b str r3, [r7, #20]
|
|
pressure_comp = (int32_t)((pressure_comp - (var2 >> 12)) * ((uint32_t)3125));
|
|
8003f1e: 68fb ldr r3, [r7, #12]
|
|
8003f20: 131b asrs r3, r3, #12
|
|
8003f22: 697a ldr r2, [r7, #20]
|
|
8003f24: 1ad3 subs r3, r2, r3
|
|
8003f26: 461a mov r2, r3
|
|
8003f28: f640 4335 movw r3, #3125 ; 0xc35
|
|
8003f2c: fb03 f302 mul.w r3, r3, r2
|
|
8003f30: 617b str r3, [r7, #20]
|
|
if (pressure_comp >= BME680_MAX_OVERFLOW_VAL)
|
|
8003f32: 697b ldr r3, [r7, #20]
|
|
8003f34: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8003f38: db06 blt.n 8003f48 <calc_pressure+0xd2>
|
|
pressure_comp = ((pressure_comp / var1) << 1);
|
|
8003f3a: 697a ldr r2, [r7, #20]
|
|
8003f3c: 693b ldr r3, [r7, #16]
|
|
8003f3e: fb92 f3f3 sdiv r3, r2, r3
|
|
8003f42: 005b lsls r3, r3, #1
|
|
8003f44: 617b str r3, [r7, #20]
|
|
8003f46: e005 b.n 8003f54 <calc_pressure+0xde>
|
|
else
|
|
pressure_comp = ((pressure_comp << 1) / var1);
|
|
8003f48: 697b ldr r3, [r7, #20]
|
|
8003f4a: 005a lsls r2, r3, #1
|
|
8003f4c: 693b ldr r3, [r7, #16]
|
|
8003f4e: fb92 f3f3 sdiv r3, r2, r3
|
|
8003f52: 617b str r3, [r7, #20]
|
|
var1 = ((int32_t)dev->calib.par_p9 * (int32_t)(((pressure_comp >> 3) *
|
|
8003f54: 683b ldr r3, [r7, #0]
|
|
8003f56: f9b3 302a ldrsh.w r3, [r3, #42] ; 0x2a
|
|
8003f5a: 4619 mov r1, r3
|
|
8003f5c: 697b ldr r3, [r7, #20]
|
|
8003f5e: 10db asrs r3, r3, #3
|
|
(pressure_comp >> 3)) >> 13)) >> 12;
|
|
8003f60: 697a ldr r2, [r7, #20]
|
|
8003f62: 10d2 asrs r2, r2, #3
|
|
var1 = ((int32_t)dev->calib.par_p9 * (int32_t)(((pressure_comp >> 3) *
|
|
8003f64: fb02 f303 mul.w r3, r2, r3
|
|
(pressure_comp >> 3)) >> 13)) >> 12;
|
|
8003f68: 135b asrs r3, r3, #13
|
|
var1 = ((int32_t)dev->calib.par_p9 * (int32_t)(((pressure_comp >> 3) *
|
|
8003f6a: fb03 f301 mul.w r3, r3, r1
|
|
8003f6e: 131b asrs r3, r3, #12
|
|
8003f70: 613b str r3, [r7, #16]
|
|
var2 = ((int32_t)(pressure_comp >> 2) *
|
|
8003f72: 697b ldr r3, [r7, #20]
|
|
8003f74: 109b asrs r3, r3, #2
|
|
(int32_t)dev->calib.par_p8) >> 13;
|
|
8003f76: 683a ldr r2, [r7, #0]
|
|
8003f78: f9b2 2028 ldrsh.w r2, [r2, #40] ; 0x28
|
|
var2 = ((int32_t)(pressure_comp >> 2) *
|
|
8003f7c: fb02 f303 mul.w r3, r2, r3
|
|
8003f80: 135b asrs r3, r3, #13
|
|
8003f82: 60fb str r3, [r7, #12]
|
|
var3 = ((int32_t)(pressure_comp >> 8) * (int32_t)(pressure_comp >> 8) *
|
|
8003f84: 697b ldr r3, [r7, #20]
|
|
8003f86: 121b asrs r3, r3, #8
|
|
8003f88: 697a ldr r2, [r7, #20]
|
|
8003f8a: 1212 asrs r2, r2, #8
|
|
8003f8c: fb02 f303 mul.w r3, r2, r3
|
|
(int32_t)(pressure_comp >> 8) *
|
|
8003f90: 697a ldr r2, [r7, #20]
|
|
8003f92: 1212 asrs r2, r2, #8
|
|
var3 = ((int32_t)(pressure_comp >> 8) * (int32_t)(pressure_comp >> 8) *
|
|
8003f94: fb02 f303 mul.w r3, r2, r3
|
|
(int32_t)dev->calib.par_p10) >> 17;
|
|
8003f98: 683a ldr r2, [r7, #0]
|
|
8003f9a: f892 202c ldrb.w r2, [r2, #44] ; 0x2c
|
|
(int32_t)(pressure_comp >> 8) *
|
|
8003f9e: fb02 f303 mul.w r3, r2, r3
|
|
var3 = ((int32_t)(pressure_comp >> 8) * (int32_t)(pressure_comp >> 8) *
|
|
8003fa2: 145b asrs r3, r3, #17
|
|
8003fa4: 60bb str r3, [r7, #8]
|
|
|
|
pressure_comp = (int32_t)(pressure_comp) + ((var1 + var2 + var3 +
|
|
8003fa6: 693a ldr r2, [r7, #16]
|
|
8003fa8: 68fb ldr r3, [r7, #12]
|
|
8003faa: 441a add r2, r3
|
|
8003fac: 68bb ldr r3, [r7, #8]
|
|
8003fae: 441a add r2, r3
|
|
((int32_t)dev->calib.par_p7 << 7)) >> 4);
|
|
8003fb0: 683b ldr r3, [r7, #0]
|
|
8003fb2: f993 3027 ldrsb.w r3, [r3, #39] ; 0x27
|
|
8003fb6: 01db lsls r3, r3, #7
|
|
pressure_comp = (int32_t)(pressure_comp) + ((var1 + var2 + var3 +
|
|
8003fb8: 4413 add r3, r2
|
|
((int32_t)dev->calib.par_p7 << 7)) >> 4);
|
|
8003fba: 111b asrs r3, r3, #4
|
|
pressure_comp = (int32_t)(pressure_comp) + ((var1 + var2 + var3 +
|
|
8003fbc: 697a ldr r2, [r7, #20]
|
|
8003fbe: 4413 add r3, r2
|
|
8003fc0: 617b str r3, [r7, #20]
|
|
|
|
return (uint32_t)pressure_comp;
|
|
8003fc2: 697b ldr r3, [r7, #20]
|
|
|
|
}
|
|
8003fc4: 4618 mov r0, r3
|
|
8003fc6: 371c adds r7, #28
|
|
8003fc8: 46bd mov sp, r7
|
|
8003fca: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003fce: 4770 bx lr
|
|
|
|
08003fd0 <calc_humidity>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to calculate the humidity value.
|
|
*/
|
|
static uint32_t calc_humidity(uint16_t hum_adc, const struct bme680_dev *dev)
|
|
{
|
|
8003fd0: b490 push {r4, r7}
|
|
8003fd2: b08a sub sp, #40 ; 0x28
|
|
8003fd4: af00 add r7, sp, #0
|
|
8003fd6: 4603 mov r3, r0
|
|
8003fd8: 6039 str r1, [r7, #0]
|
|
8003fda: 80fb strh r3, [r7, #6]
|
|
int32_t var5;
|
|
int32_t var6;
|
|
int32_t temp_scaled;
|
|
int32_t calc_hum;
|
|
|
|
temp_scaled = (((int32_t) dev->calib.t_fine * 5) + 128) >> 8;
|
|
8003fdc: 683b ldr r3, [r7, #0]
|
|
8003fde: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
8003fe0: 4613 mov r3, r2
|
|
8003fe2: 009b lsls r3, r3, #2
|
|
8003fe4: 4413 add r3, r2
|
|
8003fe6: 3380 adds r3, #128 ; 0x80
|
|
8003fe8: 121b asrs r3, r3, #8
|
|
8003fea: 623b str r3, [r7, #32]
|
|
var1 = (int32_t) (hum_adc - ((int32_t) ((int32_t) dev->calib.par_h1 * 16)))
|
|
8003fec: 88fa ldrh r2, [r7, #6]
|
|
8003fee: 683b ldr r3, [r7, #0]
|
|
8003ff0: 891b ldrh r3, [r3, #8]
|
|
8003ff2: 011b lsls r3, r3, #4
|
|
8003ff4: 1ad1 subs r1, r2, r3
|
|
- (((temp_scaled * (int32_t) dev->calib.par_h3) / ((int32_t) 100)) >> 1);
|
|
8003ff6: 683b ldr r3, [r7, #0]
|
|
8003ff8: f993 300c ldrsb.w r3, [r3, #12]
|
|
8003ffc: 461a mov r2, r3
|
|
8003ffe: 6a3b ldr r3, [r7, #32]
|
|
8004000: fb03 f202 mul.w r2, r3, r2
|
|
8004004: f248 531f movw r3, #34079 ; 0x851f
|
|
8004008: f2c5 13eb movt r3, #20971 ; 0x51eb
|
|
800400c: fb83 0302 smull r0, r3, r3, r2
|
|
8004010: 1158 asrs r0, r3, #5
|
|
8004012: 17d3 asrs r3, r2, #31
|
|
8004014: 1ac3 subs r3, r0, r3
|
|
8004016: 105b asrs r3, r3, #1
|
|
var1 = (int32_t) (hum_adc - ((int32_t) ((int32_t) dev->calib.par_h1 * 16)))
|
|
8004018: 1acb subs r3, r1, r3
|
|
800401a: 61fb str r3, [r7, #28]
|
|
var2 = ((int32_t) dev->calib.par_h2
|
|
800401c: 683b ldr r3, [r7, #0]
|
|
800401e: 895b ldrh r3, [r3, #10]
|
|
8004020: 461c mov r4, r3
|
|
* (((temp_scaled * (int32_t) dev->calib.par_h4) / ((int32_t) 100))
|
|
8004022: 683b ldr r3, [r7, #0]
|
|
8004024: f993 300d ldrsb.w r3, [r3, #13]
|
|
8004028: 461a mov r2, r3
|
|
800402a: 6a3b ldr r3, [r7, #32]
|
|
800402c: fb03 f202 mul.w r2, r3, r2
|
|
8004030: f248 531f movw r3, #34079 ; 0x851f
|
|
8004034: f2c5 13eb movt r3, #20971 ; 0x51eb
|
|
8004038: fb83 1302 smull r1, r3, r3, r2
|
|
800403c: 1159 asrs r1, r3, #5
|
|
800403e: 17d3 asrs r3, r2, #31
|
|
8004040: 1ac9 subs r1, r1, r3
|
|
+ (((temp_scaled * ((temp_scaled * (int32_t) dev->calib.par_h5) / ((int32_t) 100))) >> 6)
|
|
8004042: 683b ldr r3, [r7, #0]
|
|
8004044: f993 300e ldrsb.w r3, [r3, #14]
|
|
8004048: 461a mov r2, r3
|
|
800404a: 6a3b ldr r3, [r7, #32]
|
|
800404c: fb03 f202 mul.w r2, r3, r2
|
|
8004050: f248 531f movw r3, #34079 ; 0x851f
|
|
8004054: f2c5 13eb movt r3, #20971 ; 0x51eb
|
|
8004058: fb83 0302 smull r0, r3, r3, r2
|
|
800405c: 1158 asrs r0, r3, #5
|
|
800405e: 17d3 asrs r3, r2, #31
|
|
8004060: 1ac3 subs r3, r0, r3
|
|
8004062: 6a3a ldr r2, [r7, #32]
|
|
8004064: fb02 f303 mul.w r3, r2, r3
|
|
8004068: 119a asrs r2, r3, #6
|
|
/ ((int32_t) 100)) + (int32_t) (1 << 14))) >> 10;
|
|
800406a: f248 531f movw r3, #34079 ; 0x851f
|
|
800406e: f2c5 13eb movt r3, #20971 ; 0x51eb
|
|
8004072: fb83 0302 smull r0, r3, r3, r2
|
|
8004076: 1158 asrs r0, r3, #5
|
|
8004078: 17d3 asrs r3, r2, #31
|
|
800407a: 1ac3 subs r3, r0, r3
|
|
+ (((temp_scaled * ((temp_scaled * (int32_t) dev->calib.par_h5) / ((int32_t) 100))) >> 6)
|
|
800407c: 440b add r3, r1
|
|
/ ((int32_t) 100)) + (int32_t) (1 << 14))) >> 10;
|
|
800407e: f503 4380 add.w r3, r3, #16384 ; 0x4000
|
|
* (((temp_scaled * (int32_t) dev->calib.par_h4) / ((int32_t) 100))
|
|
8004082: fb03 f304 mul.w r3, r3, r4
|
|
var2 = ((int32_t) dev->calib.par_h2
|
|
8004086: 129b asrs r3, r3, #10
|
|
8004088: 61bb str r3, [r7, #24]
|
|
var3 = var1 * var2;
|
|
800408a: 69fb ldr r3, [r7, #28]
|
|
800408c: 69ba ldr r2, [r7, #24]
|
|
800408e: fb02 f303 mul.w r3, r2, r3
|
|
8004092: 617b str r3, [r7, #20]
|
|
var4 = (int32_t) dev->calib.par_h6 << 7;
|
|
8004094: 683b ldr r3, [r7, #0]
|
|
8004096: 7bdb ldrb r3, [r3, #15]
|
|
8004098: 01db lsls r3, r3, #7
|
|
800409a: 613b str r3, [r7, #16]
|
|
var4 = ((var4) + ((temp_scaled * (int32_t) dev->calib.par_h7) / ((int32_t) 100))) >> 4;
|
|
800409c: 683b ldr r3, [r7, #0]
|
|
800409e: f993 3010 ldrsb.w r3, [r3, #16]
|
|
80040a2: 461a mov r2, r3
|
|
80040a4: 6a3b ldr r3, [r7, #32]
|
|
80040a6: fb03 f202 mul.w r2, r3, r2
|
|
80040aa: f248 531f movw r3, #34079 ; 0x851f
|
|
80040ae: f2c5 13eb movt r3, #20971 ; 0x51eb
|
|
80040b2: fb83 1302 smull r1, r3, r3, r2
|
|
80040b6: 1159 asrs r1, r3, #5
|
|
80040b8: 17d3 asrs r3, r2, #31
|
|
80040ba: 1aca subs r2, r1, r3
|
|
80040bc: 693b ldr r3, [r7, #16]
|
|
80040be: 4413 add r3, r2
|
|
80040c0: 111b asrs r3, r3, #4
|
|
80040c2: 613b str r3, [r7, #16]
|
|
var5 = ((var3 >> 14) * (var3 >> 14)) >> 10;
|
|
80040c4: 697b ldr r3, [r7, #20]
|
|
80040c6: 139b asrs r3, r3, #14
|
|
80040c8: 697a ldr r2, [r7, #20]
|
|
80040ca: 1392 asrs r2, r2, #14
|
|
80040cc: fb02 f303 mul.w r3, r2, r3
|
|
80040d0: 129b asrs r3, r3, #10
|
|
80040d2: 60fb str r3, [r7, #12]
|
|
var6 = (var4 * var5) >> 1;
|
|
80040d4: 693b ldr r3, [r7, #16]
|
|
80040d6: 68fa ldr r2, [r7, #12]
|
|
80040d8: fb02 f303 mul.w r3, r2, r3
|
|
80040dc: 105b asrs r3, r3, #1
|
|
80040de: 60bb str r3, [r7, #8]
|
|
calc_hum = (((var3 + var6) >> 10) * ((int32_t) 1000)) >> 12;
|
|
80040e0: 697a ldr r2, [r7, #20]
|
|
80040e2: 68bb ldr r3, [r7, #8]
|
|
80040e4: 4413 add r3, r2
|
|
80040e6: 129b asrs r3, r3, #10
|
|
80040e8: f44f 727a mov.w r2, #1000 ; 0x3e8
|
|
80040ec: fb02 f303 mul.w r3, r2, r3
|
|
80040f0: 131b asrs r3, r3, #12
|
|
80040f2: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
if (calc_hum > 100000) /* Cap at 100%rH */
|
|
80040f4: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
80040f6: f248 63a0 movw r3, #34464 ; 0x86a0
|
|
80040fa: f2c0 0301 movt r3, #1
|
|
80040fe: 429a cmp r2, r3
|
|
8004100: dd05 ble.n 800410e <calc_humidity+0x13e>
|
|
calc_hum = 100000;
|
|
8004102: f248 63a0 movw r3, #34464 ; 0x86a0
|
|
8004106: f2c0 0301 movt r3, #1
|
|
800410a: 627b str r3, [r7, #36] ; 0x24
|
|
800410c: e004 b.n 8004118 <calc_humidity+0x148>
|
|
else if (calc_hum < 0)
|
|
800410e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8004110: 2b00 cmp r3, #0
|
|
8004112: da01 bge.n 8004118 <calc_humidity+0x148>
|
|
calc_hum = 0;
|
|
8004114: 2300 movs r3, #0
|
|
8004116: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
return (uint32_t) calc_hum;
|
|
8004118: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
}
|
|
800411a: 4618 mov r0, r3
|
|
800411c: 3728 adds r7, #40 ; 0x28
|
|
800411e: 46bd mov sp, r7
|
|
8004120: bc90 pop {r4, r7}
|
|
8004122: 4770 bx lr
|
|
|
|
08004124 <calc_gas_resistance>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to calculate the Gas Resistance value.
|
|
*/
|
|
static uint32_t calc_gas_resistance(uint16_t gas_res_adc, uint8_t gas_range, const struct bme680_dev *dev)
|
|
{
|
|
8004124: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8004128: b0b0 sub sp, #192 ; 0xc0
|
|
800412a: af00 add r7, sp, #0
|
|
800412c: 4603 mov r3, r0
|
|
800412e: 61ba str r2, [r7, #24]
|
|
8004130: 83fb strh r3, [r7, #30]
|
|
8004132: 460b mov r3, r1
|
|
8004134: 777b strb r3, [r7, #29]
|
|
int64_t var1;
|
|
uint64_t var2;
|
|
int64_t var3;
|
|
uint32_t calc_gas_res;
|
|
/**Look up table 1 for the possible gas range values */
|
|
uint32_t lookupTable1[16] = { UINT32_C(2147483647), UINT32_C(2147483647), UINT32_C(2147483647), UINT32_C(2147483647),
|
|
8004136: f24e 332c movw r3, #58156 ; 0xe32c
|
|
800413a: f6c0 0300 movt r3, #2048 ; 0x800
|
|
800413e: f107 0564 add.w r5, r7, #100 ; 0x64
|
|
8004142: 461c mov r4, r3
|
|
8004144: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
8004146: c50f stmia r5!, {r0, r1, r2, r3}
|
|
8004148: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
800414a: c50f stmia r5!, {r0, r1, r2, r3}
|
|
800414c: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
800414e: c50f stmia r5!, {r0, r1, r2, r3}
|
|
8004150: e894 000f ldmia.w r4, {r0, r1, r2, r3}
|
|
8004154: e885 000f stmia.w r5, {r0, r1, r2, r3}
|
|
UINT32_C(2147483647), UINT32_C(2126008810), UINT32_C(2147483647), UINT32_C(2130303777),
|
|
UINT32_C(2147483647), UINT32_C(2147483647), UINT32_C(2143188679), UINT32_C(2136746228),
|
|
UINT32_C(2147483647), UINT32_C(2126008810), UINT32_C(2147483647), UINT32_C(2147483647) };
|
|
/**Look up table 2 for the possible gas range values */
|
|
uint32_t lookupTable2[16] = { UINT32_C(4096000000), UINT32_C(2048000000), UINT32_C(1024000000), UINT32_C(512000000),
|
|
8004158: f24e 336c movw r3, #58220 ; 0xe36c
|
|
800415c: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8004160: f107 0524 add.w r5, r7, #36 ; 0x24
|
|
8004164: 461c mov r4, r3
|
|
8004166: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
8004168: c50f stmia r5!, {r0, r1, r2, r3}
|
|
800416a: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
800416c: c50f stmia r5!, {r0, r1, r2, r3}
|
|
800416e: cc0f ldmia r4!, {r0, r1, r2, r3}
|
|
8004170: c50f stmia r5!, {r0, r1, r2, r3}
|
|
8004172: e894 000f ldmia.w r4, {r0, r1, r2, r3}
|
|
8004176: e885 000f stmia.w r5, {r0, r1, r2, r3}
|
|
UINT32_C(255744255), UINT32_C(127110228), UINT32_C(64000000), UINT32_C(32258064), UINT32_C(16016016),
|
|
UINT32_C(8000000), UINT32_C(4000000), UINT32_C(2000000), UINT32_C(1000000), UINT32_C(500000),
|
|
UINT32_C(250000), UINT32_C(125000) };
|
|
|
|
var1 = (int64_t) ((1340 + (5 * (int64_t) dev->calib.range_sw_err)) *
|
|
800417a: 69bb ldr r3, [r7, #24]
|
|
800417c: f993 3036 ldrsb.w r3, [r3, #54] ; 0x36
|
|
8004180: b25c sxtb r4, r3
|
|
8004182: ea4f 75e4 mov.w r5, r4, asr #31
|
|
8004186: 4622 mov r2, r4
|
|
8004188: 462b mov r3, r5
|
|
800418a: f04f 0000 mov.w r0, #0
|
|
800418e: f04f 0100 mov.w r1, #0
|
|
8004192: 0099 lsls r1, r3, #2
|
|
8004194: ea41 7192 orr.w r1, r1, r2, lsr #30
|
|
8004198: 0090 lsls r0, r2, #2
|
|
800419a: 4602 mov r2, r0
|
|
800419c: 460b mov r3, r1
|
|
800419e: 1911 adds r1, r2, r4
|
|
80041a0: 6139 str r1, [r7, #16]
|
|
80041a2: 416b adcs r3, r5
|
|
80041a4: 617b str r3, [r7, #20]
|
|
80041a6: f240 523c movw r2, #1340 ; 0x53c
|
|
80041aa: f04f 0300 mov.w r3, #0
|
|
80041ae: e9d7 4504 ldrd r4, r5, [r7, #16]
|
|
80041b2: 4621 mov r1, r4
|
|
80041b4: eb11 0802 adds.w r8, r1, r2
|
|
80041b8: 4629 mov r1, r5
|
|
80041ba: eb41 0903 adc.w r9, r1, r3
|
|
((int64_t) lookupTable1[gas_range])) >> 16;
|
|
80041be: 7f7b ldrb r3, [r7, #29]
|
|
80041c0: 009b lsls r3, r3, #2
|
|
80041c2: f107 02c0 add.w r2, r7, #192 ; 0xc0
|
|
80041c6: 4413 add r3, r2
|
|
80041c8: f853 3c5c ldr.w r3, [r3, #-92]
|
|
80041cc: 461a mov r2, r3
|
|
80041ce: f04f 0300 mov.w r3, #0
|
|
var1 = (int64_t) ((1340 + (5 * (int64_t) dev->calib.range_sw_err)) *
|
|
80041d2: fb02 f009 mul.w r0, r2, r9
|
|
80041d6: fb08 f103 mul.w r1, r8, r3
|
|
80041da: 1844 adds r4, r0, r1
|
|
80041dc: fba8 0102 umull r0, r1, r8, r2
|
|
80041e0: 1863 adds r3, r4, r1
|
|
80041e2: 4619 mov r1, r3
|
|
80041e4: f04f 0200 mov.w r2, #0
|
|
80041e8: f04f 0300 mov.w r3, #0
|
|
80041ec: 0c02 lsrs r2, r0, #16
|
|
80041ee: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80041f2: 140b asrs r3, r1, #16
|
|
80041f4: e9c7 232e strd r2, r3, [r7, #184] ; 0xb8
|
|
var2 = (((int64_t) ((int64_t) gas_res_adc << 15) - (int64_t) (16777216)) + var1);
|
|
80041f8: 8bf8 ldrh r0, [r7, #30]
|
|
80041fa: f04f 0100 mov.w r1, #0
|
|
80041fe: f04f 0200 mov.w r2, #0
|
|
8004202: f04f 0300 mov.w r3, #0
|
|
8004206: 03cb lsls r3, r1, #15
|
|
8004208: ea43 4350 orr.w r3, r3, r0, lsr #17
|
|
800420c: 03c2 lsls r2, r0, #15
|
|
800420e: f112 4a7f adds.w sl, r2, #4278190080 ; 0xff000000
|
|
8004212: f143 3bff adc.w fp, r3, #4294967295 ; 0xffffffff
|
|
8004216: e9d7 232e ldrd r2, r3, [r7, #184] ; 0xb8
|
|
800421a: eb1a 0102 adds.w r1, sl, r2
|
|
800421e: 60b9 str r1, [r7, #8]
|
|
8004220: eb4b 0303 adc.w r3, fp, r3
|
|
8004224: 60fb str r3, [r7, #12]
|
|
8004226: e9d7 3402 ldrd r3, r4, [r7, #8]
|
|
800422a: e9c7 342c strd r3, r4, [r7, #176] ; 0xb0
|
|
var3 = (((int64_t) lookupTable2[gas_range] * (int64_t) var1) >> 9);
|
|
800422e: 7f7b ldrb r3, [r7, #29]
|
|
8004230: 009b lsls r3, r3, #2
|
|
8004232: f107 02c0 add.w r2, r7, #192 ; 0xc0
|
|
8004236: 4413 add r3, r2
|
|
8004238: f853 3c9c ldr.w r3, [r3, #-156]
|
|
800423c: 461a mov r2, r3
|
|
800423e: f04f 0300 mov.w r3, #0
|
|
8004242: f8d7 10b8 ldr.w r1, [r7, #184] ; 0xb8
|
|
8004246: fb03 f001 mul.w r0, r3, r1
|
|
800424a: f8d7 10bc ldr.w r1, [r7, #188] ; 0xbc
|
|
800424e: fb02 f101 mul.w r1, r2, r1
|
|
8004252: 1844 adds r4, r0, r1
|
|
8004254: f8d7 10b8 ldr.w r1, [r7, #184] ; 0xb8
|
|
8004258: fba1 0102 umull r0, r1, r1, r2
|
|
800425c: 1863 adds r3, r4, r1
|
|
800425e: 4619 mov r1, r3
|
|
8004260: f04f 0200 mov.w r2, #0
|
|
8004264: f04f 0300 mov.w r3, #0
|
|
8004268: 0a42 lsrs r2, r0, #9
|
|
800426a: ea42 52c1 orr.w r2, r2, r1, lsl #23
|
|
800426e: 124b asrs r3, r1, #9
|
|
8004270: e9c7 232a strd r2, r3, [r7, #168] ; 0xa8
|
|
calc_gas_res = (uint32_t) ((var3 + ((int64_t) var2 >> 1)) / (int64_t) var2);
|
|
8004274: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0
|
|
8004278: f04f 0200 mov.w r2, #0
|
|
800427c: f04f 0300 mov.w r3, #0
|
|
8004280: 0842 lsrs r2, r0, #1
|
|
8004282: ea42 72c1 orr.w r2, r2, r1, lsl #31
|
|
8004286: 104b asrs r3, r1, #1
|
|
8004288: e9d7 012a ldrd r0, r1, [r7, #168] ; 0xa8
|
|
800428c: 1814 adds r4, r2, r0
|
|
800428e: 603c str r4, [r7, #0]
|
|
8004290: 414b adcs r3, r1
|
|
8004292: 607b str r3, [r7, #4]
|
|
8004294: e9d7 232c ldrd r2, r3, [r7, #176] ; 0xb0
|
|
8004298: e9d7 0100 ldrd r0, r1, [r7]
|
|
800429c: f7fc fcd4 bl 8000c48 <__aeabi_ldivmod>
|
|
80042a0: 4602 mov r2, r0
|
|
80042a2: 460b mov r3, r1
|
|
80042a4: 4613 mov r3, r2
|
|
80042a6: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
|
|
return calc_gas_res;
|
|
80042aa: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
|
|
}
|
|
80042ae: 4618 mov r0, r3
|
|
80042b0: 37c0 adds r7, #192 ; 0xc0
|
|
80042b2: 46bd mov sp, r7
|
|
80042b4: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
|
|
080042b8 <calc_heater_res>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to calculate the Heat Resistance value.
|
|
*/
|
|
static uint8_t calc_heater_res(uint16_t temp, const struct bme680_dev *dev)
|
|
{
|
|
80042b8: b480 push {r7}
|
|
80042ba: b08b sub sp, #44 ; 0x2c
|
|
80042bc: af00 add r7, sp, #0
|
|
80042be: 4603 mov r3, r0
|
|
80042c0: 6039 str r1, [r7, #0]
|
|
80042c2: 80fb strh r3, [r7, #6]
|
|
int32_t var3;
|
|
int32_t var4;
|
|
int32_t var5;
|
|
int32_t heatr_res_x100;
|
|
|
|
if (temp > 400) /* Cap temperature */
|
|
80042c4: 88fb ldrh r3, [r7, #6]
|
|
80042c6: f5b3 7fc8 cmp.w r3, #400 ; 0x190
|
|
80042ca: d902 bls.n 80042d2 <calc_heater_res+0x1a>
|
|
temp = 400;
|
|
80042cc: f44f 73c8 mov.w r3, #400 ; 0x190
|
|
80042d0: 80fb strh r3, [r7, #6]
|
|
|
|
var1 = (((int32_t) dev->amb_temp * dev->calib.par_gh3) / 1000) * 256;
|
|
80042d2: 683b ldr r3, [r7, #0]
|
|
80042d4: f993 3004 ldrsb.w r3, [r3, #4]
|
|
80042d8: 461a mov r2, r3
|
|
80042da: 683b ldr r3, [r7, #0]
|
|
80042dc: f993 3014 ldrsb.w r3, [r3, #20]
|
|
80042e0: fb03 f202 mul.w r2, r3, r2
|
|
80042e4: f644 53d3 movw r3, #19923 ; 0x4dd3
|
|
80042e8: f2c1 0362 movt r3, #4194 ; 0x1062
|
|
80042ec: fb83 1302 smull r1, r3, r3, r2
|
|
80042f0: 1199 asrs r1, r3, #6
|
|
80042f2: 17d3 asrs r3, r2, #31
|
|
80042f4: 1acb subs r3, r1, r3
|
|
80042f6: 021b lsls r3, r3, #8
|
|
80042f8: 627b str r3, [r7, #36] ; 0x24
|
|
var2 = (dev->calib.par_gh1 + 784) * (((((dev->calib.par_gh2 + 154009) * temp * 5) / 100) + 3276800) / 10);
|
|
80042fa: 683b ldr r3, [r7, #0]
|
|
80042fc: f993 3011 ldrsb.w r3, [r3, #17]
|
|
8004300: f503 7144 add.w r1, r3, #784 ; 0x310
|
|
8004304: 683b ldr r3, [r7, #0]
|
|
8004306: f9b3 3012 ldrsh.w r3, [r3, #18]
|
|
800430a: f503 3316 add.w r3, r3, #153600 ; 0x25800
|
|
800430e: f203 1399 addw r3, r3, #409 ; 0x199
|
|
8004312: 88fa ldrh r2, [r7, #6]
|
|
8004314: fb02 f203 mul.w r2, r2, r3
|
|
8004318: f246 6367 movw r3, #26215 ; 0x6667
|
|
800431c: f2c6 6366 movt r3, #26214 ; 0x6666
|
|
8004320: fb83 0302 smull r0, r3, r3, r2
|
|
8004324: 10d8 asrs r0, r3, #3
|
|
8004326: 17d3 asrs r3, r2, #31
|
|
8004328: 1ac3 subs r3, r0, r3
|
|
800432a: f503 1248 add.w r2, r3, #3276800 ; 0x320000
|
|
800432e: f246 6367 movw r3, #26215 ; 0x6667
|
|
8004332: f2c6 6366 movt r3, #26214 ; 0x6666
|
|
8004336: fb83 0302 smull r0, r3, r3, r2
|
|
800433a: 1098 asrs r0, r3, #2
|
|
800433c: 17d3 asrs r3, r2, #31
|
|
800433e: 1ac3 subs r3, r0, r3
|
|
8004340: fb03 f301 mul.w r3, r3, r1
|
|
8004344: 623b str r3, [r7, #32]
|
|
var3 = var1 + (var2 / 2);
|
|
8004346: 6a3b ldr r3, [r7, #32]
|
|
8004348: 0fda lsrs r2, r3, #31
|
|
800434a: 4413 add r3, r2
|
|
800434c: 105b asrs r3, r3, #1
|
|
800434e: 461a mov r2, r3
|
|
8004350: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8004352: 4413 add r3, r2
|
|
8004354: 61fb str r3, [r7, #28]
|
|
var4 = (var3 / (dev->calib.res_heat_range + 4));
|
|
8004356: 683b ldr r3, [r7, #0]
|
|
8004358: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
800435c: 3304 adds r3, #4
|
|
800435e: 69fa ldr r2, [r7, #28]
|
|
8004360: fb92 f3f3 sdiv r3, r2, r3
|
|
8004364: 61bb str r3, [r7, #24]
|
|
var5 = (131 * dev->calib.res_heat_val) + 65536;
|
|
8004366: 683b ldr r3, [r7, #0]
|
|
8004368: f993 3035 ldrsb.w r3, [r3, #53] ; 0x35
|
|
800436c: 461a mov r2, r3
|
|
800436e: 4613 mov r3, r2
|
|
8004370: 019b lsls r3, r3, #6
|
|
8004372: 4413 add r3, r2
|
|
8004374: 005b lsls r3, r3, #1
|
|
8004376: 4413 add r3, r2
|
|
8004378: f503 3380 add.w r3, r3, #65536 ; 0x10000
|
|
800437c: 617b str r3, [r7, #20]
|
|
heatr_res_x100 = (int32_t) (((var4 / var5) - 250) * 34);
|
|
800437e: 69ba ldr r2, [r7, #24]
|
|
8004380: 697b ldr r3, [r7, #20]
|
|
8004382: fb92 f3f3 sdiv r3, r2, r3
|
|
8004386: f1a3 02fa sub.w r2, r3, #250 ; 0xfa
|
|
800438a: 4613 mov r3, r2
|
|
800438c: 011b lsls r3, r3, #4
|
|
800438e: 4413 add r3, r2
|
|
8004390: 005b lsls r3, r3, #1
|
|
8004392: 613b str r3, [r7, #16]
|
|
heatr_res = (uint8_t) ((heatr_res_x100 + 50) / 100);
|
|
8004394: 693b ldr r3, [r7, #16]
|
|
8004396: f103 0232 add.w r2, r3, #50 ; 0x32
|
|
800439a: f248 531f movw r3, #34079 ; 0x851f
|
|
800439e: f2c5 13eb movt r3, #20971 ; 0x51eb
|
|
80043a2: fb83 1302 smull r1, r3, r3, r2
|
|
80043a6: 1159 asrs r1, r3, #5
|
|
80043a8: 17d3 asrs r3, r2, #31
|
|
80043aa: 1acb subs r3, r1, r3
|
|
80043ac: 73fb strb r3, [r7, #15]
|
|
|
|
return heatr_res;
|
|
80043ae: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80043b0: 4618 mov r0, r3
|
|
80043b2: 372c adds r7, #44 ; 0x2c
|
|
80043b4: 46bd mov sp, r7
|
|
80043b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80043ba: 4770 bx lr
|
|
|
|
080043bc <calc_heater_dur>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to calculate the Heat duration value.
|
|
*/
|
|
static uint8_t calc_heater_dur(uint16_t dur)
|
|
{
|
|
80043bc: b480 push {r7}
|
|
80043be: b085 sub sp, #20
|
|
80043c0: af00 add r7, sp, #0
|
|
80043c2: 4603 mov r3, r0
|
|
80043c4: 80fb strh r3, [r7, #6]
|
|
uint8_t factor = 0;
|
|
80043c6: 2300 movs r3, #0
|
|
80043c8: 73fb strb r3, [r7, #15]
|
|
uint8_t durval;
|
|
|
|
if (dur >= 0xfc0) {
|
|
80043ca: 88fb ldrh r3, [r7, #6]
|
|
80043cc: f5b3 6f7c cmp.w r3, #4032 ; 0xfc0
|
|
80043d0: d308 bcc.n 80043e4 <calc_heater_dur+0x28>
|
|
durval = 0xff; /* Max duration*/
|
|
80043d2: 23ff movs r3, #255 ; 0xff
|
|
80043d4: 73bb strb r3, [r7, #14]
|
|
80043d6: e00f b.n 80043f8 <calc_heater_dur+0x3c>
|
|
} else {
|
|
while (dur > 0x3F) {
|
|
dur = dur / 4;
|
|
80043d8: 88fb ldrh r3, [r7, #6]
|
|
80043da: 089b lsrs r3, r3, #2
|
|
80043dc: 80fb strh r3, [r7, #6]
|
|
factor += 1;
|
|
80043de: 7bfb ldrb r3, [r7, #15]
|
|
80043e0: 3301 adds r3, #1
|
|
80043e2: 73fb strb r3, [r7, #15]
|
|
while (dur > 0x3F) {
|
|
80043e4: 88fb ldrh r3, [r7, #6]
|
|
80043e6: 2b3f cmp r3, #63 ; 0x3f
|
|
80043e8: d8f6 bhi.n 80043d8 <calc_heater_dur+0x1c>
|
|
}
|
|
durval = (uint8_t) (dur + (factor * 64));
|
|
80043ea: 88fb ldrh r3, [r7, #6]
|
|
80043ec: b2da uxtb r2, r3
|
|
80043ee: 7bfb ldrb r3, [r7, #15]
|
|
80043f0: 019b lsls r3, r3, #6
|
|
80043f2: b2db uxtb r3, r3
|
|
80043f4: 4413 add r3, r2
|
|
80043f6: 73bb strb r3, [r7, #14]
|
|
}
|
|
|
|
return durval;
|
|
80043f8: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
80043fa: 4618 mov r0, r3
|
|
80043fc: 3714 adds r7, #20
|
|
80043fe: 46bd mov sp, r7
|
|
8004400: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004404: 4770 bx lr
|
|
|
|
08004406 <read_field_data>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to calculate the field data of sensor.
|
|
*/
|
|
static int8_t read_field_data(struct bme680_field_data *data, struct bme680_dev *dev)
|
|
{
|
|
8004406: b580 push {r7, lr}
|
|
8004408: b08a sub sp, #40 ; 0x28
|
|
800440a: af00 add r7, sp, #0
|
|
800440c: 6078 str r0, [r7, #4]
|
|
800440e: 6039 str r1, [r7, #0]
|
|
int8_t rslt;
|
|
uint8_t buff[BME680_FIELD_LENGTH] = { 0 };
|
|
8004410: 2300 movs r3, #0
|
|
8004412: 60bb str r3, [r7, #8]
|
|
8004414: f107 030c add.w r3, r7, #12
|
|
8004418: 2200 movs r2, #0
|
|
800441a: 601a str r2, [r3, #0]
|
|
800441c: 605a str r2, [r3, #4]
|
|
800441e: f8c3 2007 str.w r2, [r3, #7]
|
|
uint8_t gas_range;
|
|
uint32_t adc_temp;
|
|
uint32_t adc_pres;
|
|
uint16_t adc_hum;
|
|
uint16_t adc_gas_res;
|
|
uint8_t tries = 10;
|
|
8004422: 230a movs r3, #10
|
|
8004424: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
8004428: 6838 ldr r0, [r7, #0]
|
|
800442a: f000 f975 bl 8004718 <null_ptr_check>
|
|
800442e: 4603 mov r3, r0
|
|
8004430: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
do {
|
|
if (rslt == BME680_OK) {
|
|
8004434: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
8004438: 2b00 cmp r3, #0
|
|
800443a: f040 8087 bne.w 800454c <read_field_data+0x146>
|
|
rslt = bme680_get_regs(((uint8_t) (BME680_FIELD0_ADDR)), buff, (uint16_t) BME680_FIELD_LENGTH,
|
|
800443e: f107 0108 add.w r1, r7, #8
|
|
8004442: 683b ldr r3, [r7, #0]
|
|
8004444: 220f movs r2, #15
|
|
8004446: 201d movs r0, #29
|
|
8004448: f7fe ff49 bl 80032de <bme680_get_regs>
|
|
800444c: 4603 mov r3, r0
|
|
800444e: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
dev);
|
|
|
|
data->status = buff[0] & BME680_NEW_DATA_MSK;
|
|
8004452: 7a3b ldrb r3, [r7, #8]
|
|
8004454: f023 037f bic.w r3, r3, #127 ; 0x7f
|
|
8004458: b2da uxtb r2, r3
|
|
800445a: 687b ldr r3, [r7, #4]
|
|
800445c: 701a strb r2, [r3, #0]
|
|
data->gas_index = buff[0] & BME680_GAS_INDEX_MSK;
|
|
800445e: 7a3b ldrb r3, [r7, #8]
|
|
8004460: f003 030f and.w r3, r3, #15
|
|
8004464: b2da uxtb r2, r3
|
|
8004466: 687b ldr r3, [r7, #4]
|
|
8004468: 705a strb r2, [r3, #1]
|
|
data->meas_index = buff[1];
|
|
800446a: 7a7a ldrb r2, [r7, #9]
|
|
800446c: 687b ldr r3, [r7, #4]
|
|
800446e: 709a strb r2, [r3, #2]
|
|
|
|
/* read the raw data from the sensor */
|
|
adc_pres = (uint32_t) (((uint32_t) buff[2] * 4096) | ((uint32_t) buff[3] * 16)
|
|
8004470: 7abb ldrb r3, [r7, #10]
|
|
8004472: 031a lsls r2, r3, #12
|
|
8004474: 7afb ldrb r3, [r7, #11]
|
|
8004476: 011b lsls r3, r3, #4
|
|
8004478: 4313 orrs r3, r2
|
|
| ((uint32_t) buff[4] / 16));
|
|
800447a: 7b3a ldrb r2, [r7, #12]
|
|
800447c: 0912 lsrs r2, r2, #4
|
|
800447e: b2d2 uxtb r2, r2
|
|
adc_pres = (uint32_t) (((uint32_t) buff[2] * 4096) | ((uint32_t) buff[3] * 16)
|
|
8004480: 4313 orrs r3, r2
|
|
8004482: 623b str r3, [r7, #32]
|
|
adc_temp = (uint32_t) (((uint32_t) buff[5] * 4096) | ((uint32_t) buff[6] * 16)
|
|
8004484: 7b7b ldrb r3, [r7, #13]
|
|
8004486: 031a lsls r2, r3, #12
|
|
8004488: 7bbb ldrb r3, [r7, #14]
|
|
800448a: 011b lsls r3, r3, #4
|
|
800448c: 4313 orrs r3, r2
|
|
| ((uint32_t) buff[7] / 16));
|
|
800448e: 7bfa ldrb r2, [r7, #15]
|
|
8004490: 0912 lsrs r2, r2, #4
|
|
8004492: b2d2 uxtb r2, r2
|
|
adc_temp = (uint32_t) (((uint32_t) buff[5] * 4096) | ((uint32_t) buff[6] * 16)
|
|
8004494: 4313 orrs r3, r2
|
|
8004496: 61fb str r3, [r7, #28]
|
|
adc_hum = (uint16_t) (((uint32_t) buff[8] * 256) | (uint32_t) buff[9]);
|
|
8004498: 7c3b ldrb r3, [r7, #16]
|
|
800449a: b29b uxth r3, r3
|
|
800449c: 021b lsls r3, r3, #8
|
|
800449e: b29a uxth r2, r3
|
|
80044a0: 7c7b ldrb r3, [r7, #17]
|
|
80044a2: b29b uxth r3, r3
|
|
80044a4: 4313 orrs r3, r2
|
|
80044a6: 837b strh r3, [r7, #26]
|
|
adc_gas_res = (uint16_t) ((uint32_t) buff[13] * 4 | (((uint32_t) buff[14]) / 64));
|
|
80044a8: 7d7b ldrb r3, [r7, #21]
|
|
80044aa: b29b uxth r3, r3
|
|
80044ac: 009b lsls r3, r3, #2
|
|
80044ae: b29a uxth r2, r3
|
|
80044b0: 7dbb ldrb r3, [r7, #22]
|
|
80044b2: 099b lsrs r3, r3, #6
|
|
80044b4: b2db uxtb r3, r3
|
|
80044b6: b29b uxth r3, r3
|
|
80044b8: 4313 orrs r3, r2
|
|
80044ba: 833b strh r3, [r7, #24]
|
|
gas_range = buff[14] & BME680_GAS_RANGE_MSK;
|
|
80044bc: 7dbb ldrb r3, [r7, #22]
|
|
80044be: f003 030f and.w r3, r3, #15
|
|
80044c2: 75fb strb r3, [r7, #23]
|
|
|
|
data->status |= buff[14] & BME680_GASM_VALID_MSK;
|
|
80044c4: 687b ldr r3, [r7, #4]
|
|
80044c6: 781b ldrb r3, [r3, #0]
|
|
80044c8: b25a sxtb r2, r3
|
|
80044ca: 7dbb ldrb r3, [r7, #22]
|
|
80044cc: b25b sxtb r3, r3
|
|
80044ce: f003 0320 and.w r3, r3, #32
|
|
80044d2: b25b sxtb r3, r3
|
|
80044d4: 4313 orrs r3, r2
|
|
80044d6: b25b sxtb r3, r3
|
|
80044d8: b2da uxtb r2, r3
|
|
80044da: 687b ldr r3, [r7, #4]
|
|
80044dc: 701a strb r2, [r3, #0]
|
|
data->status |= buff[14] & BME680_HEAT_STAB_MSK;
|
|
80044de: 687b ldr r3, [r7, #4]
|
|
80044e0: 781b ldrb r3, [r3, #0]
|
|
80044e2: b25a sxtb r2, r3
|
|
80044e4: 7dbb ldrb r3, [r7, #22]
|
|
80044e6: b25b sxtb r3, r3
|
|
80044e8: f003 0310 and.w r3, r3, #16
|
|
80044ec: b25b sxtb r3, r3
|
|
80044ee: 4313 orrs r3, r2
|
|
80044f0: b25b sxtb r3, r3
|
|
80044f2: b2da uxtb r2, r3
|
|
80044f4: 687b ldr r3, [r7, #4]
|
|
80044f6: 701a strb r2, [r3, #0]
|
|
|
|
if (data->status & BME680_NEW_DATA_MSK) {
|
|
80044f8: 687b ldr r3, [r7, #4]
|
|
80044fa: 781b ldrb r3, [r3, #0]
|
|
80044fc: b25b sxtb r3, r3
|
|
80044fe: 2b00 cmp r3, #0
|
|
8004500: da20 bge.n 8004544 <read_field_data+0x13e>
|
|
data->temperature = calc_temperature(adc_temp, dev);
|
|
8004502: 6839 ldr r1, [r7, #0]
|
|
8004504: 69f8 ldr r0, [r7, #28]
|
|
8004506: f7ff fc31 bl 8003d6c <calc_temperature>
|
|
800450a: 4603 mov r3, r0
|
|
800450c: 461a mov r2, r3
|
|
800450e: 687b ldr r3, [r7, #4]
|
|
8004510: 809a strh r2, [r3, #4]
|
|
data->pressure = calc_pressure(adc_pres, dev);
|
|
8004512: 6839 ldr r1, [r7, #0]
|
|
8004514: 6a38 ldr r0, [r7, #32]
|
|
8004516: f7ff fcae bl 8003e76 <calc_pressure>
|
|
800451a: 4602 mov r2, r0
|
|
800451c: 687b ldr r3, [r7, #4]
|
|
800451e: 609a str r2, [r3, #8]
|
|
data->humidity = calc_humidity(adc_hum, dev);
|
|
8004520: 8b7b ldrh r3, [r7, #26]
|
|
8004522: 6839 ldr r1, [r7, #0]
|
|
8004524: 4618 mov r0, r3
|
|
8004526: f7ff fd53 bl 8003fd0 <calc_humidity>
|
|
800452a: 4602 mov r2, r0
|
|
800452c: 687b ldr r3, [r7, #4]
|
|
800452e: 60da str r2, [r3, #12]
|
|
data->gas_resistance = calc_gas_resistance(adc_gas_res, gas_range, dev);
|
|
8004530: 7df9 ldrb r1, [r7, #23]
|
|
8004532: 8b3b ldrh r3, [r7, #24]
|
|
8004534: 683a ldr r2, [r7, #0]
|
|
8004536: 4618 mov r0, r3
|
|
8004538: f7ff fdf4 bl 8004124 <calc_gas_resistance>
|
|
800453c: 4602 mov r2, r0
|
|
800453e: 687b ldr r3, [r7, #4]
|
|
8004540: 611a str r2, [r3, #16]
|
|
break;
|
|
8004542: e00d b.n 8004560 <read_field_data+0x15a>
|
|
}
|
|
/* Delay to poll the data */
|
|
dev->delay_ms(BME680_POLL_PERIOD_MS);
|
|
8004544: 683b ldr r3, [r7, #0]
|
|
8004546: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
8004548: 200a movs r0, #10
|
|
800454a: 4798 blx r3
|
|
}
|
|
tries--;
|
|
800454c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8004550: 3b01 subs r3, #1
|
|
8004552: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
} while (tries);
|
|
8004556: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
800455a: 2b00 cmp r3, #0
|
|
800455c: f47f af6a bne.w 8004434 <read_field_data+0x2e>
|
|
|
|
if (!tries)
|
|
8004560: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8004564: 2b00 cmp r3, #0
|
|
8004566: d102 bne.n 800456e <read_field_data+0x168>
|
|
rslt = BME680_W_NO_NEW_DATA;
|
|
8004568: 2302 movs r3, #2
|
|
800456a: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
return rslt;
|
|
800456e: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
8004572: 4618 mov r0, r3
|
|
8004574: 3728 adds r7, #40 ; 0x28
|
|
8004576: 46bd mov sp, r7
|
|
8004578: bd80 pop {r7, pc}
|
|
|
|
0800457a <set_mem_page>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to set the memory page based on register address.
|
|
*/
|
|
static int8_t set_mem_page(uint8_t reg_addr, struct bme680_dev *dev)
|
|
{
|
|
800457a: b590 push {r4, r7, lr}
|
|
800457c: b085 sub sp, #20
|
|
800457e: af00 add r7, sp, #0
|
|
8004580: 4603 mov r3, r0
|
|
8004582: 6039 str r1, [r7, #0]
|
|
8004584: 71fb strb r3, [r7, #7]
|
|
int8_t rslt;
|
|
uint8_t reg;
|
|
uint8_t mem_page;
|
|
|
|
/* Check for null pointers in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
8004586: 6838 ldr r0, [r7, #0]
|
|
8004588: f000 f8c6 bl 8004718 <null_ptr_check>
|
|
800458c: 4603 mov r3, r0
|
|
800458e: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
8004590: f997 300f ldrsb.w r3, [r7, #15]
|
|
8004594: 2b00 cmp r3, #0
|
|
8004596: d14f bne.n 8004638 <set_mem_page+0xbe>
|
|
if (reg_addr > 0x7f)
|
|
8004598: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800459c: 2b00 cmp r3, #0
|
|
800459e: da02 bge.n 80045a6 <set_mem_page+0x2c>
|
|
mem_page = BME680_MEM_PAGE1;
|
|
80045a0: 2300 movs r3, #0
|
|
80045a2: 73bb strb r3, [r7, #14]
|
|
80045a4: e001 b.n 80045aa <set_mem_page+0x30>
|
|
else
|
|
mem_page = BME680_MEM_PAGE0;
|
|
80045a6: 2310 movs r3, #16
|
|
80045a8: 73bb strb r3, [r7, #14]
|
|
|
|
if (mem_page != dev->mem_page) {
|
|
80045aa: 683b ldr r3, [r7, #0]
|
|
80045ac: 78db ldrb r3, [r3, #3]
|
|
80045ae: 7bba ldrb r2, [r7, #14]
|
|
80045b0: 429a cmp r2, r3
|
|
80045b2: d041 beq.n 8004638 <set_mem_page+0xbe>
|
|
dev->mem_page = mem_page;
|
|
80045b4: 683b ldr r3, [r7, #0]
|
|
80045b6: 7bba ldrb r2, [r7, #14]
|
|
80045b8: 70da strb r2, [r3, #3]
|
|
|
|
dev->com_rslt = dev->read(dev->dev_id, BME680_MEM_PAGE_ADDR | BME680_SPI_RD_MSK, ®, 1);
|
|
80045ba: 683b ldr r3, [r7, #0]
|
|
80045bc: 6c9c ldr r4, [r3, #72] ; 0x48
|
|
80045be: 683b ldr r3, [r7, #0]
|
|
80045c0: 7858 ldrb r0, [r3, #1]
|
|
80045c2: f107 020d add.w r2, r7, #13
|
|
80045c6: 2301 movs r3, #1
|
|
80045c8: 21f3 movs r1, #243 ; 0xf3
|
|
80045ca: 47a0 blx r4
|
|
80045cc: 4603 mov r3, r0
|
|
80045ce: 461a mov r2, r3
|
|
80045d0: 683b ldr r3, [r7, #0]
|
|
80045d2: f883 2054 strb.w r2, [r3, #84] ; 0x54
|
|
if (dev->com_rslt != 0)
|
|
80045d6: 683b ldr r3, [r7, #0]
|
|
80045d8: f993 3054 ldrsb.w r3, [r3, #84] ; 0x54
|
|
80045dc: 2b00 cmp r3, #0
|
|
80045de: d001 beq.n 80045e4 <set_mem_page+0x6a>
|
|
rslt = BME680_E_COM_FAIL;
|
|
80045e0: 23fe movs r3, #254 ; 0xfe
|
|
80045e2: 73fb strb r3, [r7, #15]
|
|
|
|
if (rslt == BME680_OK) {
|
|
80045e4: f997 300f ldrsb.w r3, [r7, #15]
|
|
80045e8: 2b00 cmp r3, #0
|
|
80045ea: d125 bne.n 8004638 <set_mem_page+0xbe>
|
|
reg = reg & (~BME680_MEM_PAGE_MSK);
|
|
80045ec: 7b7b ldrb r3, [r7, #13]
|
|
80045ee: f023 0310 bic.w r3, r3, #16
|
|
80045f2: b2db uxtb r3, r3
|
|
80045f4: 737b strb r3, [r7, #13]
|
|
reg = reg | (dev->mem_page & BME680_MEM_PAGE_MSK);
|
|
80045f6: 683b ldr r3, [r7, #0]
|
|
80045f8: 78db ldrb r3, [r3, #3]
|
|
80045fa: b25b sxtb r3, r3
|
|
80045fc: f003 0310 and.w r3, r3, #16
|
|
8004600: b25a sxtb r2, r3
|
|
8004602: 7b7b ldrb r3, [r7, #13]
|
|
8004604: b25b sxtb r3, r3
|
|
8004606: 4313 orrs r3, r2
|
|
8004608: b25b sxtb r3, r3
|
|
800460a: b2db uxtb r3, r3
|
|
800460c: 737b strb r3, [r7, #13]
|
|
|
|
dev->com_rslt = dev->write(dev->dev_id, BME680_MEM_PAGE_ADDR & BME680_SPI_WR_MSK,
|
|
800460e: 683b ldr r3, [r7, #0]
|
|
8004610: 6cdc ldr r4, [r3, #76] ; 0x4c
|
|
8004612: 683b ldr r3, [r7, #0]
|
|
8004614: 7858 ldrb r0, [r3, #1]
|
|
8004616: f107 020d add.w r2, r7, #13
|
|
800461a: 2301 movs r3, #1
|
|
800461c: 2173 movs r1, #115 ; 0x73
|
|
800461e: 47a0 blx r4
|
|
8004620: 4603 mov r3, r0
|
|
8004622: 461a mov r2, r3
|
|
8004624: 683b ldr r3, [r7, #0]
|
|
8004626: f883 2054 strb.w r2, [r3, #84] ; 0x54
|
|
®, 1);
|
|
if (dev->com_rslt != 0)
|
|
800462a: 683b ldr r3, [r7, #0]
|
|
800462c: f993 3054 ldrsb.w r3, [r3, #84] ; 0x54
|
|
8004630: 2b00 cmp r3, #0
|
|
8004632: d001 beq.n 8004638 <set_mem_page+0xbe>
|
|
rslt = BME680_E_COM_FAIL;
|
|
8004634: 23fe movs r3, #254 ; 0xfe
|
|
8004636: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
}
|
|
|
|
return rslt;
|
|
8004638: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
800463c: 4618 mov r0, r3
|
|
800463e: 3714 adds r7, #20
|
|
8004640: 46bd mov sp, r7
|
|
8004642: bd90 pop {r4, r7, pc}
|
|
|
|
08004644 <get_mem_page>:
|
|
|
|
/*!
|
|
* @brief This internal API is used to get the memory page based on register address.
|
|
*/
|
|
static int8_t get_mem_page(struct bme680_dev *dev)
|
|
{
|
|
8004644: b590 push {r4, r7, lr}
|
|
8004646: b085 sub sp, #20
|
|
8004648: af00 add r7, sp, #0
|
|
800464a: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
uint8_t reg;
|
|
|
|
/* Check for null pointer in the device structure*/
|
|
rslt = null_ptr_check(dev);
|
|
800464c: 6878 ldr r0, [r7, #4]
|
|
800464e: f000 f863 bl 8004718 <null_ptr_check>
|
|
8004652: 4603 mov r3, r0
|
|
8004654: 73fb strb r3, [r7, #15]
|
|
if (rslt == BME680_OK) {
|
|
8004656: f997 300f ldrsb.w r3, [r7, #15]
|
|
800465a: 2b00 cmp r3, #0
|
|
800465c: d11b bne.n 8004696 <get_mem_page+0x52>
|
|
dev->com_rslt = dev->read(dev->dev_id, BME680_MEM_PAGE_ADDR | BME680_SPI_RD_MSK, ®, 1);
|
|
800465e: 687b ldr r3, [r7, #4]
|
|
8004660: 6c9c ldr r4, [r3, #72] ; 0x48
|
|
8004662: 687b ldr r3, [r7, #4]
|
|
8004664: 7858 ldrb r0, [r3, #1]
|
|
8004666: f107 020e add.w r2, r7, #14
|
|
800466a: 2301 movs r3, #1
|
|
800466c: 21f3 movs r1, #243 ; 0xf3
|
|
800466e: 47a0 blx r4
|
|
8004670: 4603 mov r3, r0
|
|
8004672: 461a mov r2, r3
|
|
8004674: 687b ldr r3, [r7, #4]
|
|
8004676: f883 2054 strb.w r2, [r3, #84] ; 0x54
|
|
if (dev->com_rslt != 0)
|
|
800467a: 687b ldr r3, [r7, #4]
|
|
800467c: f993 3054 ldrsb.w r3, [r3, #84] ; 0x54
|
|
8004680: 2b00 cmp r3, #0
|
|
8004682: d002 beq.n 800468a <get_mem_page+0x46>
|
|
rslt = BME680_E_COM_FAIL;
|
|
8004684: 23fe movs r3, #254 ; 0xfe
|
|
8004686: 73fb strb r3, [r7, #15]
|
|
8004688: e005 b.n 8004696 <get_mem_page+0x52>
|
|
else
|
|
dev->mem_page = reg & BME680_MEM_PAGE_MSK;
|
|
800468a: 7bbb ldrb r3, [r7, #14]
|
|
800468c: f003 0310 and.w r3, r3, #16
|
|
8004690: b2da uxtb r2, r3
|
|
8004692: 687b ldr r3, [r7, #4]
|
|
8004694: 70da strb r2, [r3, #3]
|
|
}
|
|
|
|
return rslt;
|
|
8004696: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
800469a: 4618 mov r0, r3
|
|
800469c: 3714 adds r7, #20
|
|
800469e: 46bd mov sp, r7
|
|
80046a0: bd90 pop {r4, r7, pc}
|
|
|
|
080046a2 <boundary_check>:
|
|
/*!
|
|
* @brief This internal API is used to validate the boundary
|
|
* conditions.
|
|
*/
|
|
static int8_t boundary_check(uint8_t *value, uint8_t min, uint8_t max, struct bme680_dev *dev)
|
|
{
|
|
80046a2: b480 push {r7}
|
|
80046a4: b087 sub sp, #28
|
|
80046a6: af00 add r7, sp, #0
|
|
80046a8: 60f8 str r0, [r7, #12]
|
|
80046aa: 607b str r3, [r7, #4]
|
|
80046ac: 460b mov r3, r1
|
|
80046ae: 72fb strb r3, [r7, #11]
|
|
80046b0: 4613 mov r3, r2
|
|
80046b2: 72bb strb r3, [r7, #10]
|
|
int8_t rslt = BME680_OK;
|
|
80046b4: 2300 movs r3, #0
|
|
80046b6: 75fb strb r3, [r7, #23]
|
|
|
|
if (value != NULL) {
|
|
80046b8: 68fb ldr r3, [r7, #12]
|
|
80046ba: 2b00 cmp r3, #0
|
|
80046bc: d022 beq.n 8004704 <boundary_check+0x62>
|
|
/* Check if value is below minimum value */
|
|
if (*value < min) {
|
|
80046be: 68fb ldr r3, [r7, #12]
|
|
80046c0: 781b ldrb r3, [r3, #0]
|
|
80046c2: 7afa ldrb r2, [r7, #11]
|
|
80046c4: 429a cmp r2, r3
|
|
80046c6: d90b bls.n 80046e0 <boundary_check+0x3e>
|
|
/* Auto correct the invalid value to minimum value */
|
|
*value = min;
|
|
80046c8: 68fb ldr r3, [r7, #12]
|
|
80046ca: 7afa ldrb r2, [r7, #11]
|
|
80046cc: 701a strb r2, [r3, #0]
|
|
dev->info_msg |= BME680_I_MIN_CORRECTION;
|
|
80046ce: 687b ldr r3, [r7, #4]
|
|
80046d0: f893 3046 ldrb.w r3, [r3, #70] ; 0x46
|
|
80046d4: f043 0301 orr.w r3, r3, #1
|
|
80046d8: b2da uxtb r2, r3
|
|
80046da: 687b ldr r3, [r7, #4]
|
|
80046dc: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
}
|
|
/* Check if value is above maximum value */
|
|
if (*value > max) {
|
|
80046e0: 68fb ldr r3, [r7, #12]
|
|
80046e2: 781b ldrb r3, [r3, #0]
|
|
80046e4: 7aba ldrb r2, [r7, #10]
|
|
80046e6: 429a cmp r2, r3
|
|
80046e8: d20e bcs.n 8004708 <boundary_check+0x66>
|
|
/* Auto correct the invalid value to maximum value */
|
|
*value = max;
|
|
80046ea: 68fb ldr r3, [r7, #12]
|
|
80046ec: 7aba ldrb r2, [r7, #10]
|
|
80046ee: 701a strb r2, [r3, #0]
|
|
dev->info_msg |= BME680_I_MAX_CORRECTION;
|
|
80046f0: 687b ldr r3, [r7, #4]
|
|
80046f2: f893 3046 ldrb.w r3, [r3, #70] ; 0x46
|
|
80046f6: f043 0302 orr.w r3, r3, #2
|
|
80046fa: b2da uxtb r2, r3
|
|
80046fc: 687b ldr r3, [r7, #4]
|
|
80046fe: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
8004702: e001 b.n 8004708 <boundary_check+0x66>
|
|
}
|
|
} else {
|
|
rslt = BME680_E_NULL_PTR;
|
|
8004704: 23ff movs r3, #255 ; 0xff
|
|
8004706: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
return rslt;
|
|
8004708: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
800470c: 4618 mov r0, r3
|
|
800470e: 371c adds r7, #28
|
|
8004710: 46bd mov sp, r7
|
|
8004712: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004716: 4770 bx lr
|
|
|
|
08004718 <null_ptr_check>:
|
|
/*!
|
|
* @brief This internal API is used to validate the device structure pointer for
|
|
* null conditions.
|
|
*/
|
|
static int8_t null_ptr_check(const struct bme680_dev *dev)
|
|
{
|
|
8004718: b480 push {r7}
|
|
800471a: b085 sub sp, #20
|
|
800471c: af00 add r7, sp, #0
|
|
800471e: 6078 str r0, [r7, #4]
|
|
int8_t rslt;
|
|
|
|
if ((dev == NULL) || (dev->read == NULL) || (dev->write == NULL) || (dev->delay_ms == NULL)) {
|
|
8004720: 687b ldr r3, [r7, #4]
|
|
8004722: 2b00 cmp r3, #0
|
|
8004724: d00b beq.n 800473e <null_ptr_check+0x26>
|
|
8004726: 687b ldr r3, [r7, #4]
|
|
8004728: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
800472a: 2b00 cmp r3, #0
|
|
800472c: d007 beq.n 800473e <null_ptr_check+0x26>
|
|
800472e: 687b ldr r3, [r7, #4]
|
|
8004730: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
8004732: 2b00 cmp r3, #0
|
|
8004734: d003 beq.n 800473e <null_ptr_check+0x26>
|
|
8004736: 687b ldr r3, [r7, #4]
|
|
8004738: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
800473a: 2b00 cmp r3, #0
|
|
800473c: d102 bne.n 8004744 <null_ptr_check+0x2c>
|
|
/* Device structure pointer is not valid */
|
|
rslt = BME680_E_NULL_PTR;
|
|
800473e: 23ff movs r3, #255 ; 0xff
|
|
8004740: 73fb strb r3, [r7, #15]
|
|
8004742: e001 b.n 8004748 <null_ptr_check+0x30>
|
|
} else {
|
|
/* Device structure is fine */
|
|
rslt = BME680_OK;
|
|
8004744: 2300 movs r3, #0
|
|
8004746: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return rslt;
|
|
8004748: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
800474c: 4618 mov r0, r3
|
|
800474e: 3714 adds r7, #20
|
|
8004750: 46bd mov sp, r7
|
|
8004752: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004756: 4770 bx lr
|
|
|
|
08004758 <gas_Sensor_Init>:
|
|
#include "sys_sensors.h"
|
|
#include "main.h"
|
|
#include "bme680_selftest.h"
|
|
|
|
HAL_StatusTypeDef gas_Sensor_Init(struct bme680_dev *gas_sensor)
|
|
{
|
|
8004758: b580 push {r7, lr}
|
|
800475a: b084 sub sp, #16
|
|
800475c: af00 add r7, sp, #0
|
|
800475e: 6078 str r0, [r7, #4]
|
|
|
|
|
|
gas_sensor->dev_id = BME680_I2C_ADDR_PRIMARY;
|
|
8004760: 687b ldr r3, [r7, #4]
|
|
8004762: 2276 movs r2, #118 ; 0x76
|
|
8004764: 705a strb r2, [r3, #1]
|
|
gas_sensor->intf = BME680_I2C_INTF;
|
|
8004766: 687b ldr r3, [r7, #4]
|
|
8004768: 2201 movs r2, #1
|
|
800476a: 709a strb r2, [r3, #2]
|
|
gas_sensor->read = user_i2c_read;
|
|
800476c: 687a ldr r2, [r7, #4]
|
|
800476e: f241 33fd movw r3, #5117 ; 0x13fd
|
|
8004772: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8004776: 6493 str r3, [r2, #72] ; 0x48
|
|
gas_sensor->write = user_i2c_write;
|
|
8004778: 687a ldr r2, [r7, #4]
|
|
800477a: f241 4355 movw r3, #5205 ; 0x1455
|
|
800477e: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8004782: 64d3 str r3, [r2, #76] ; 0x4c
|
|
gas_sensor->delay_ms = HAL_Delay;
|
|
8004784: 687a ldr r2, [r7, #4]
|
|
8004786: f644 2323 movw r3, #18979 ; 0x4a23
|
|
800478a: f6c0 0300 movt r3, #2048 ; 0x800
|
|
800478e: 6513 str r3, [r2, #80] ; 0x50
|
|
/* amb_temp can be set to 25 prior to configuring the gas sensor
|
|
* or by performing a few temperature readings without operating the gas sensor.
|
|
*/
|
|
gas_sensor->amb_temp = 25;
|
|
8004790: 687b ldr r3, [r7, #4]
|
|
8004792: 2219 movs r2, #25
|
|
8004794: 711a strb r2, [r3, #4]
|
|
MX_I2C1_Init();
|
|
8004796: f7fd fcb1 bl 80020fc <MX_I2C1_Init>
|
|
|
|
HAL_StatusTypeDef rslt = BME680_OK;
|
|
800479a: 2300 movs r3, #0
|
|
800479c: 73fb strb r3, [r7, #15]
|
|
rslt=bme680_init(gas_sensor);
|
|
800479e: 6878 ldr r0, [r7, #4]
|
|
80047a0: f7fe fd69 bl 8003276 <bme680_init>
|
|
80047a4: 4603 mov r3, r0
|
|
80047a6: 73fb strb r3, [r7, #15]
|
|
//rslt=bme680_Config_ForcedMode(gas_sensor);
|
|
|
|
|
|
return rslt;
|
|
80047a8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80047aa: 4618 mov r0, r3
|
|
80047ac: 3710 adds r7, #16
|
|
80047ae: 46bd mov sp, r7
|
|
80047b0: bd80 pop {r7, pc}
|
|
|
|
080047b2 <gas_Sensor_Read_data>:
|
|
|
|
HAL_StatusTypeDef gas_Sensor_Read_data(struct bme680_dev *gas_sensor,sensor_t *sensor_data)
|
|
{
|
|
80047b2: b580 push {r7, lr}
|
|
80047b4: b0a2 sub sp, #136 ; 0x88
|
|
80047b6: af00 add r7, sp, #0
|
|
80047b8: 6078 str r0, [r7, #4]
|
|
80047ba: 6039 str r1, [r7, #0]
|
|
|
|
rslt=bme680_Config_ForcedMode(gas_sensor);
|
|
gas_sensor->delay_ms(meas_period);
|
|
|
|
rslt=bme680_get_sensor_data(gas_sensor_data, gas_sensor);*/
|
|
uint8_t rslt=BME680_OK;
|
|
80047bc: 2300 movs r3, #0
|
|
80047be: f887 3087 strb.w r3, [r7, #135] ; 0x87
|
|
|
|
gas_sensor->power_mode = BME680_FORCED_MODE;
|
|
80047c2: 687b ldr r3, [r7, #4]
|
|
80047c4: 2201 movs r2, #1
|
|
80047c6: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
uint16_t settings_sel;
|
|
|
|
/* Set the temperature, pressure and humidity & filter settings */
|
|
gas_sensor->tph_sett.os_hum = BME680_OS_1X;
|
|
80047ca: 687b ldr r3, [r7, #4]
|
|
80047cc: 2201 movs r2, #1
|
|
80047ce: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
gas_sensor->tph_sett.os_pres = BME680_OS_16X;
|
|
80047d2: 687b ldr r3, [r7, #4]
|
|
80047d4: 2205 movs r2, #5
|
|
80047d6: f883 203a strb.w r2, [r3, #58] ; 0x3a
|
|
gas_sensor->tph_sett.os_temp = BME680_OS_2X;
|
|
80047da: 687b ldr r3, [r7, #4]
|
|
80047dc: 2202 movs r2, #2
|
|
80047de: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Set the remaining gas sensor settings and link the heating profile */
|
|
gas_sensor->gas_sett.run_gas = BME680_ENABLE_GAS_MEAS;
|
|
80047e2: 687b ldr r3, [r7, #4]
|
|
80047e4: 2201 movs r2, #1
|
|
80047e6: f883 203e strb.w r2, [r3, #62] ; 0x3e
|
|
gas_sensor->gas_sett.heatr_dur = HEATR_DUR;
|
|
80047ea: 687b ldr r3, [r7, #4]
|
|
80047ec: f44f 62fa mov.w r2, #2000 ; 0x7d0
|
|
80047f0: f8a3 2042 strh.w r2, [r3, #66] ; 0x42
|
|
|
|
settings_sel = BME680_OST_SEL | BME680_OSP_SEL | BME680_OSH_SEL | BME680_GAS_SENSOR_SEL;
|
|
80047f4: 23cf movs r3, #207 ; 0xcf
|
|
80047f6: f8a7 3084 strh.w r3, [r7, #132] ; 0x84
|
|
uint16_t profile_dur = 0;
|
|
80047fa: 2300 movs r3, #0
|
|
80047fc: f8a7 3082 strh.w r3, [r7, #130] ; 0x82
|
|
struct bme680_field_data data[N_MEAS];
|
|
bme680_get_profile_dur(&profile_dur, gas_sensor);
|
|
8004800: f107 0382 add.w r3, r7, #130 ; 0x82
|
|
8004804: 6879 ldr r1, [r7, #4]
|
|
8004806: 4618 mov r0, r3
|
|
8004808: f7ff f8ab bl 8003962 <bme680_get_profile_dur>
|
|
|
|
uint8_t i = 0;
|
|
800480c: 2300 movs r3, #0
|
|
800480e: f887 3086 strb.w r3, [r7, #134] ; 0x86
|
|
while ((rslt == BME680_OK) && (i < N_MEAS)) {
|
|
8004812: e042 b.n 800489a <gas_Sensor_Read_data+0xe8>
|
|
if (rslt == BME680_OK) {
|
|
8004814: f897 3087 ldrb.w r3, [r7, #135] ; 0x87
|
|
8004818: 2b00 cmp r3, #0
|
|
800481a: d139 bne.n 8004890 <gas_Sensor_Read_data+0xde>
|
|
|
|
if (i % 2 == 0)
|
|
800481c: f897 3086 ldrb.w r3, [r7, #134] ; 0x86
|
|
8004820: f003 0301 and.w r3, r3, #1
|
|
8004824: b2db uxtb r3, r3
|
|
8004826: 2b00 cmp r3, #0
|
|
8004828: d105 bne.n 8004836 <gas_Sensor_Read_data+0x84>
|
|
gas_sensor->gas_sett.heatr_temp = HIGH_TEMP; /* Higher temperature */
|
|
800482a: 687b ldr r3, [r7, #4]
|
|
800482c: f44f 72af mov.w r2, #350 ; 0x15e
|
|
8004830: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
|
|
8004834: e003 b.n 800483e <gas_Sensor_Read_data+0x8c>
|
|
else
|
|
gas_sensor->gas_sett.heatr_temp = LOW_TEMP; /* Lower temperature */
|
|
8004836: 687b ldr r3, [r7, #4]
|
|
8004838: 2296 movs r2, #150 ; 0x96
|
|
800483a: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
|
|
|
|
rslt = bme680_set_sensor_settings(settings_sel, gas_sensor);
|
|
800483e: f8b7 3084 ldrh.w r3, [r7, #132] ; 0x84
|
|
8004842: 6879 ldr r1, [r7, #4]
|
|
8004844: 4618 mov r0, r3
|
|
8004846: f7fe fe56 bl 80034f6 <bme680_set_sensor_settings>
|
|
800484a: 4603 mov r3, r0
|
|
800484c: f887 3087 strb.w r3, [r7, #135] ; 0x87
|
|
|
|
if (rslt == BME680_OK) {
|
|
8004850: f897 3087 ldrb.w r3, [r7, #135] ; 0x87
|
|
8004854: 2b00 cmp r3, #0
|
|
8004856: d11b bne.n 8004890 <gas_Sensor_Read_data+0xde>
|
|
|
|
rslt = bme680_set_sensor_mode(gas_sensor); /* Trigger a measurement */
|
|
8004858: 6878 ldr r0, [r7, #4]
|
|
800485a: f7ff f81e bl 800389a <bme680_set_sensor_mode>
|
|
800485e: 4603 mov r3, r0
|
|
8004860: f887 3087 strb.w r3, [r7, #135] ; 0x87
|
|
|
|
gas_sensor->delay_ms(profile_dur); /* Wait for the measurement to complete */
|
|
8004864: 687b ldr r3, [r7, #4]
|
|
8004866: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
8004868: f8b7 2082 ldrh.w r2, [r7, #130] ; 0x82
|
|
800486c: 4610 mov r0, r2
|
|
800486e: 4798 blx r3
|
|
|
|
rslt = bme680_get_sensor_data(&data[i], gas_sensor);
|
|
8004870: f897 2086 ldrb.w r2, [r7, #134] ; 0x86
|
|
8004874: f107 0108 add.w r1, r7, #8
|
|
8004878: 4613 mov r3, r2
|
|
800487a: 009b lsls r3, r3, #2
|
|
800487c: 4413 add r3, r2
|
|
800487e: 009b lsls r3, r3, #2
|
|
8004880: 440b add r3, r1
|
|
8004882: 6879 ldr r1, [r7, #4]
|
|
8004884: 4618 mov r0, r3
|
|
8004886: f7ff f8d3 bl 8003a30 <bme680_get_sensor_data>
|
|
800488a: 4603 mov r3, r0
|
|
800488c: f887 3087 strb.w r3, [r7, #135] ; 0x87
|
|
}
|
|
}
|
|
i++;
|
|
8004890: f897 3086 ldrb.w r3, [r7, #134] ; 0x86
|
|
8004894: 3301 adds r3, #1
|
|
8004896: f887 3086 strb.w r3, [r7, #134] ; 0x86
|
|
while ((rslt == BME680_OK) && (i < N_MEAS)) {
|
|
800489a: f897 3087 ldrb.w r3, [r7, #135] ; 0x87
|
|
800489e: 2b00 cmp r3, #0
|
|
80048a0: d103 bne.n 80048aa <gas_Sensor_Read_data+0xf8>
|
|
80048a2: f897 3086 ldrb.w r3, [r7, #134] ; 0x86
|
|
80048a6: 2b05 cmp r3, #5
|
|
80048a8: d9b4 bls.n 8004814 <gas_Sensor_Read_data+0x62>
|
|
}
|
|
|
|
|
|
|
|
|
|
sensor_data->humidity = (float)data->humidity;
|
|
80048aa: 697b ldr r3, [r7, #20]
|
|
80048ac: ee07 3a90 vmov s15, r3
|
|
80048b0: eef8 7a67 vcvt.f32.u32 s15, s15
|
|
80048b4: 683b ldr r3, [r7, #0]
|
|
80048b6: edc3 7a02 vstr s15, [r3, #8]
|
|
sensor_data->temperature = (float) data->temperature;
|
|
80048ba: f9b7 300c ldrsh.w r3, [r7, #12]
|
|
80048be: ee07 3a90 vmov s15, r3
|
|
80048c2: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80048c6: 683b ldr r3, [r7, #0]
|
|
80048c8: edc3 7a01 vstr s15, [r3, #4]
|
|
sensor_data->pressure = (float)data->pressure;
|
|
80048cc: 693b ldr r3, [r7, #16]
|
|
80048ce: ee07 3a90 vmov s15, r3
|
|
80048d2: eef8 7a67 vcvt.f32.u32 s15, s15
|
|
80048d6: 683b ldr r3, [r7, #0]
|
|
80048d8: edc3 7a00 vstr s15, [r3]
|
|
|
|
return rslt;
|
|
80048dc: f897 3087 ldrb.w r3, [r7, #135] ; 0x87
|
|
|
|
}
|
|
80048e0: 4618 mov r0, r3
|
|
80048e2: 3788 adds r7, #136 ; 0x88
|
|
80048e4: 46bd mov sp, r7
|
|
80048e6: bd80 pop {r7, pc}
|
|
|
|
080048e8 <UTIL_MEM_cpy_8>:
|
|
/* Global variables ----------------------------------------------------------*/
|
|
/* Private function prototypes -----------------------------------------------*/
|
|
/* Functions Definition ------------------------------------------------------*/
|
|
|
|
void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size )
|
|
{
|
|
80048e8: b480 push {r7}
|
|
80048ea: b087 sub sp, #28
|
|
80048ec: af00 add r7, sp, #0
|
|
80048ee: 60f8 str r0, [r7, #12]
|
|
80048f0: 60b9 str r1, [r7, #8]
|
|
80048f2: 4613 mov r3, r2
|
|
80048f4: 80fb strh r3, [r7, #6]
|
|
uint8_t* dst8= (uint8_t *) dst;
|
|
80048f6: 68fb ldr r3, [r7, #12]
|
|
80048f8: 617b str r3, [r7, #20]
|
|
uint8_t* src8= (uint8_t *) src;
|
|
80048fa: 68bb ldr r3, [r7, #8]
|
|
80048fc: 613b str r3, [r7, #16]
|
|
|
|
while( size-- )
|
|
80048fe: e007 b.n 8004910 <UTIL_MEM_cpy_8+0x28>
|
|
{
|
|
*dst8++ = *src8++;
|
|
8004900: 693a ldr r2, [r7, #16]
|
|
8004902: 1c53 adds r3, r2, #1
|
|
8004904: 613b str r3, [r7, #16]
|
|
8004906: 697b ldr r3, [r7, #20]
|
|
8004908: 1c59 adds r1, r3, #1
|
|
800490a: 6179 str r1, [r7, #20]
|
|
800490c: 7812 ldrb r2, [r2, #0]
|
|
800490e: 701a strb r2, [r3, #0]
|
|
while( size-- )
|
|
8004910: 88fb ldrh r3, [r7, #6]
|
|
8004912: 1e5a subs r2, r3, #1
|
|
8004914: 80fa strh r2, [r7, #6]
|
|
8004916: 2b00 cmp r3, #0
|
|
8004918: d1f2 bne.n 8004900 <UTIL_MEM_cpy_8+0x18>
|
|
}
|
|
}
|
|
800491a: bf00 nop
|
|
800491c: bf00 nop
|
|
800491e: 371c adds r7, #28
|
|
8004920: 46bd mov sp, r7
|
|
8004922: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004926: 4770 bx lr
|
|
|
|
08004928 <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8004928: b580 push {r7, lr}
|
|
800492a: b082 sub sp, #8
|
|
800492c: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800492e: 2300 movs r3, #0
|
|
8004930: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8004932: 2003 movs r0, #3
|
|
8004934: f001 fe06 bl 8006544 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
8004938: 2000 movs r0, #0
|
|
800493a: f000 f80d bl 8004958 <HAL_InitTick>
|
|
800493e: 4603 mov r3, r0
|
|
8004940: 2b00 cmp r3, #0
|
|
8004942: d002 beq.n 800494a <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004944: 2301 movs r3, #1
|
|
8004946: 71fb strb r3, [r7, #7]
|
|
8004948: e001 b.n 800494e <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
800494a: f7fd fecc bl 80026e6 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
800494e: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8004950: 4618 mov r0, r3
|
|
8004952: 3708 adds r7, #8
|
|
8004954: 46bd mov sp, r7
|
|
8004956: bd80 pop {r7, pc}
|
|
|
|
08004958 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8004958: b580 push {r7, lr}
|
|
800495a: b084 sub sp, #16
|
|
800495c: af00 add r7, sp, #0
|
|
800495e: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004960: 2300 movs r3, #0
|
|
8004962: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
8004964: f240 2354 movw r3, #596 ; 0x254
|
|
8004968: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800496c: 781b ldrb r3, [r3, #0]
|
|
800496e: 2b00 cmp r3, #0
|
|
8004970: d02c beq.n 80049cc <HAL_InitTick+0x74>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
|
8004972: f240 234c movw r3, #588 ; 0x24c
|
|
8004976: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800497a: 681a ldr r2, [r3, #0]
|
|
800497c: f240 2354 movw r3, #596 ; 0x254
|
|
8004980: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8004984: 781b ldrb r3, [r3, #0]
|
|
8004986: 4619 mov r1, r3
|
|
8004988: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
800498c: fbb3 f3f1 udiv r3, r3, r1
|
|
8004990: fbb2 f3f3 udiv r3, r2, r3
|
|
8004994: 4618 mov r0, r3
|
|
8004996: f001 fe0a bl 80065ae <HAL_SYSTICK_Config>
|
|
800499a: 4603 mov r3, r0
|
|
800499c: 2b00 cmp r3, #0
|
|
800499e: d112 bne.n 80049c6 <HAL_InitTick+0x6e>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80049a0: 687b ldr r3, [r7, #4]
|
|
80049a2: 2b0f cmp r3, #15
|
|
80049a4: d80c bhi.n 80049c0 <HAL_InitTick+0x68>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80049a6: 2200 movs r2, #0
|
|
80049a8: 6879 ldr r1, [r7, #4]
|
|
80049aa: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
80049ae: f001 fdd4 bl 800655a <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80049b2: f240 2350 movw r3, #592 ; 0x250
|
|
80049b6: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80049ba: 687a ldr r2, [r7, #4]
|
|
80049bc: 601a str r2, [r3, #0]
|
|
80049be: e007 b.n 80049d0 <HAL_InitTick+0x78>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80049c0: 2301 movs r3, #1
|
|
80049c2: 73fb strb r3, [r7, #15]
|
|
80049c4: e004 b.n 80049d0 <HAL_InitTick+0x78>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80049c6: 2301 movs r3, #1
|
|
80049c8: 73fb strb r3, [r7, #15]
|
|
80049ca: e001 b.n 80049d0 <HAL_InitTick+0x78>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80049cc: 2301 movs r3, #1
|
|
80049ce: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
80049d0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80049d2: 4618 mov r0, r3
|
|
80049d4: 3710 adds r7, #16
|
|
80049d6: 46bd mov sp, r7
|
|
80049d8: bd80 pop {r7, pc}
|
|
|
|
080049da <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80049da: b480 push {r7}
|
|
80049dc: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
80049de: f240 2354 movw r3, #596 ; 0x254
|
|
80049e2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80049e6: 781b ldrb r3, [r3, #0]
|
|
80049e8: 461a mov r2, r3
|
|
80049ea: f640 2378 movw r3, #2680 ; 0xa78
|
|
80049ee: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80049f2: 681b ldr r3, [r3, #0]
|
|
80049f4: 441a add r2, r3
|
|
80049f6: f640 2378 movw r3, #2680 ; 0xa78
|
|
80049fa: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80049fe: 601a str r2, [r3, #0]
|
|
}
|
|
8004a00: bf00 nop
|
|
8004a02: 46bd mov sp, r7
|
|
8004a04: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004a08: 4770 bx lr
|
|
|
|
08004a0a <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
8004a0a: b480 push {r7}
|
|
8004a0c: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8004a0e: f640 2378 movw r3, #2680 ; 0xa78
|
|
8004a12: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8004a16: 681b ldr r3, [r3, #0]
|
|
}
|
|
8004a18: 4618 mov r0, r3
|
|
8004a1a: 46bd mov sp, r7
|
|
8004a1c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004a20: 4770 bx lr
|
|
|
|
08004a22 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8004a22: b580 push {r7, lr}
|
|
8004a24: b084 sub sp, #16
|
|
8004a26: af00 add r7, sp, #0
|
|
8004a28: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8004a2a: f7ff ffee bl 8004a0a <HAL_GetTick>
|
|
8004a2e: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8004a30: 687b ldr r3, [r7, #4]
|
|
8004a32: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a period to guaranty minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8004a34: 68fb ldr r3, [r7, #12]
|
|
8004a36: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
|
|
8004a3a: d008 beq.n 8004a4e <HAL_Delay+0x2c>
|
|
{
|
|
wait += (uint32_t)uwTickFreq;
|
|
8004a3c: f240 2354 movw r3, #596 ; 0x254
|
|
8004a40: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8004a44: 781b ldrb r3, [r3, #0]
|
|
8004a46: 461a mov r2, r3
|
|
8004a48: 68fb ldr r3, [r7, #12]
|
|
8004a4a: 4413 add r3, r2
|
|
8004a4c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
8004a4e: bf00 nop
|
|
8004a50: f7ff ffdb bl 8004a0a <HAL_GetTick>
|
|
8004a54: 4602 mov r2, r0
|
|
8004a56: 68bb ldr r3, [r7, #8]
|
|
8004a58: 1ad3 subs r3, r2, r3
|
|
8004a5a: 68fa ldr r2, [r7, #12]
|
|
8004a5c: 429a cmp r2, r3
|
|
8004a5e: d8f7 bhi.n 8004a50 <HAL_Delay+0x2e>
|
|
{
|
|
}
|
|
}
|
|
8004a60: bf00 nop
|
|
8004a62: bf00 nop
|
|
8004a64: 3710 adds r7, #16
|
|
8004a66: 46bd mov sp, r7
|
|
8004a68: bd80 pop {r7, pc}
|
|
|
|
08004a6a <HAL_SuspendTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_SuspendTick(void)
|
|
{
|
|
8004a6a: b480 push {r7}
|
|
8004a6c: af00 add r7, sp, #0
|
|
/* Disable SysTick Interrupt */
|
|
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
|
8004a6e: f24e 0310 movw r3, #57360 ; 0xe010
|
|
8004a72: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8004a76: 681a ldr r2, [r3, #0]
|
|
8004a78: f24e 0310 movw r3, #57360 ; 0xe010
|
|
8004a7c: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8004a80: f022 0202 bic.w r2, r2, #2
|
|
8004a84: 601a str r2, [r3, #0]
|
|
}
|
|
8004a86: bf00 nop
|
|
8004a88: 46bd mov sp, r7
|
|
8004a8a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004a8e: 4770 bx lr
|
|
|
|
08004a90 <HAL_ResumeTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ResumeTick(void)
|
|
{
|
|
8004a90: b480 push {r7}
|
|
8004a92: af00 add r7, sp, #0
|
|
/* Enable SysTick Interrupt */
|
|
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
|
8004a94: f24e 0310 movw r3, #57360 ; 0xe010
|
|
8004a98: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8004a9c: 681a ldr r2, [r3, #0]
|
|
8004a9e: f24e 0310 movw r3, #57360 ; 0xe010
|
|
8004aa2: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8004aa6: f042 0202 orr.w r2, r2, #2
|
|
8004aaa: 601a str r2, [r3, #0]
|
|
}
|
|
8004aac: bf00 nop
|
|
8004aae: 46bd mov sp, r7
|
|
8004ab0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ab4: 4770 bx lr
|
|
|
|
08004ab6 <LL_ADC_SetCommonClock>:
|
|
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
|
|
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
|
|
{
|
|
8004ab6: b480 push {r7}
|
|
8004ab8: b083 sub sp, #12
|
|
8004aba: af00 add r7, sp, #0
|
|
8004abc: 6078 str r0, [r7, #4]
|
|
8004abe: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
|
|
8004ac0: 687b ldr r3, [r7, #4]
|
|
8004ac2: 689b ldr r3, [r3, #8]
|
|
8004ac4: f423 127c bic.w r2, r3, #4128768 ; 0x3f0000
|
|
8004ac8: 683b ldr r3, [r7, #0]
|
|
8004aca: 431a orrs r2, r3
|
|
8004acc: 687b ldr r3, [r7, #4]
|
|
8004ace: 609a str r2, [r3, #8]
|
|
}
|
|
8004ad0: bf00 nop
|
|
8004ad2: 370c adds r7, #12
|
|
8004ad4: 46bd mov sp, r7
|
|
8004ad6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ada: 4770 bx lr
|
|
|
|
08004adc <LL_ADC_SetCommonPathInternalCh>:
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
|
|
{
|
|
8004adc: b480 push {r7}
|
|
8004ade: b083 sub sp, #12
|
|
8004ae0: af00 add r7, sp, #0
|
|
8004ae2: 6078 str r0, [r7, #4]
|
|
8004ae4: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
|
|
8004ae6: 687b ldr r3, [r7, #4]
|
|
8004ae8: 689b ldr r3, [r3, #8]
|
|
8004aea: f023 72e0 bic.w r2, r3, #29360128 ; 0x1c00000
|
|
8004aee: 683b ldr r3, [r7, #0]
|
|
8004af0: 431a orrs r2, r3
|
|
8004af2: 687b ldr r3, [r7, #4]
|
|
8004af4: 609a str r2, [r3, #8]
|
|
}
|
|
8004af6: bf00 nop
|
|
8004af8: 370c adds r7, #12
|
|
8004afa: 46bd mov sp, r7
|
|
8004afc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b00: 4770 bx lr
|
|
|
|
08004b02 <LL_ADC_GetCommonPathInternalCh>:
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
|
|
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
|
|
{
|
|
8004b02: b480 push {r7}
|
|
8004b04: b083 sub sp, #12
|
|
8004b06: af00 add r7, sp, #0
|
|
8004b08: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
|
|
8004b0a: 687b ldr r3, [r7, #4]
|
|
8004b0c: 689b ldr r3, [r3, #8]
|
|
8004b0e: f003 73e0 and.w r3, r3, #29360128 ; 0x1c00000
|
|
}
|
|
8004b12: 4618 mov r0, r3
|
|
8004b14: 370c adds r7, #12
|
|
8004b16: 46bd mov sp, r7
|
|
8004b18: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b1c: 4770 bx lr
|
|
|
|
08004b1e <LL_ADC_SetOffset>:
|
|
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
|
|
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
|
|
{
|
|
8004b1e: b480 push {r7}
|
|
8004b20: b087 sub sp, #28
|
|
8004b22: af00 add r7, sp, #0
|
|
8004b24: 60f8 str r0, [r7, #12]
|
|
8004b26: 60b9 str r1, [r7, #8]
|
|
8004b28: 607a str r2, [r7, #4]
|
|
8004b2a: 603b str r3, [r7, #0]
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
8004b2c: 68fb ldr r3, [r7, #12]
|
|
8004b2e: 3360 adds r3, #96 ; 0x60
|
|
8004b30: 461a mov r2, r3
|
|
8004b32: 68bb ldr r3, [r7, #8]
|
|
8004b34: 009b lsls r3, r3, #2
|
|
8004b36: 4413 add r3, r2
|
|
8004b38: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
8004b3a: 697b ldr r3, [r7, #20]
|
|
8004b3c: 681a ldr r2, [r3, #0]
|
|
8004b3e: f44f 4370 mov.w r3, #61440 ; 0xf000
|
|
8004b42: f2c0 33ff movt r3, #1023 ; 0x3ff
|
|
8004b46: 4013 ands r3, r2
|
|
8004b48: 687a ldr r2, [r7, #4]
|
|
8004b4a: f002 41f8 and.w r1, r2, #2080374784 ; 0x7c000000
|
|
8004b4e: 683a ldr r2, [r7, #0]
|
|
8004b50: 430a orrs r2, r1
|
|
8004b52: 4313 orrs r3, r2
|
|
8004b54: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000
|
|
8004b58: 697b ldr r3, [r7, #20]
|
|
8004b5a: 601a str r2, [r3, #0]
|
|
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
|
|
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
|
|
}
|
|
8004b5c: bf00 nop
|
|
8004b5e: 371c adds r7, #28
|
|
8004b60: 46bd mov sp, r7
|
|
8004b62: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b66: 4770 bx lr
|
|
|
|
08004b68 <LL_ADC_GetOffsetChannel>:
|
|
* (1, 2, 3, 4) For ADC channel read back from ADC register,
|
|
* comparison with internal channel parameter to be done
|
|
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
|
|
{
|
|
8004b68: b480 push {r7}
|
|
8004b6a: b085 sub sp, #20
|
|
8004b6c: af00 add r7, sp, #0
|
|
8004b6e: 6078 str r0, [r7, #4]
|
|
8004b70: 6039 str r1, [r7, #0]
|
|
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
8004b72: 687b ldr r3, [r7, #4]
|
|
8004b74: 3360 adds r3, #96 ; 0x60
|
|
8004b76: 461a mov r2, r3
|
|
8004b78: 683b ldr r3, [r7, #0]
|
|
8004b7a: 009b lsls r3, r3, #2
|
|
8004b7c: 4413 add r3, r2
|
|
8004b7e: 60fb str r3, [r7, #12]
|
|
|
|
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
|
|
8004b80: 68fb ldr r3, [r7, #12]
|
|
8004b82: 681b ldr r3, [r3, #0]
|
|
8004b84: f003 43f8 and.w r3, r3, #2080374784 ; 0x7c000000
|
|
}
|
|
8004b88: 4618 mov r0, r3
|
|
8004b8a: 3714 adds r7, #20
|
|
8004b8c: 46bd mov sp, r7
|
|
8004b8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004b92: 4770 bx lr
|
|
|
|
08004b94 <LL_ADC_SetOffsetState>:
|
|
* @arg @ref LL_ADC_OFFSET_DISABLE
|
|
* @arg @ref LL_ADC_OFFSET_ENABLE
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
|
|
{
|
|
8004b94: b480 push {r7}
|
|
8004b96: b087 sub sp, #28
|
|
8004b98: af00 add r7, sp, #0
|
|
8004b9a: 60f8 str r0, [r7, #12]
|
|
8004b9c: 60b9 str r1, [r7, #8]
|
|
8004b9e: 607a str r2, [r7, #4]
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
|
|
8004ba0: 68fb ldr r3, [r7, #12]
|
|
8004ba2: 3360 adds r3, #96 ; 0x60
|
|
8004ba4: 461a mov r2, r3
|
|
8004ba6: 68bb ldr r3, [r7, #8]
|
|
8004ba8: 009b lsls r3, r3, #2
|
|
8004baa: 4413 add r3, r2
|
|
8004bac: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
8004bae: 697b ldr r3, [r7, #20]
|
|
8004bb0: 681b ldr r3, [r3, #0]
|
|
8004bb2: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
|
|
8004bb6: 687b ldr r3, [r7, #4]
|
|
8004bb8: 431a orrs r2, r3
|
|
8004bba: 697b ldr r3, [r7, #20]
|
|
8004bbc: 601a str r2, [r3, #0]
|
|
ADC_OFR1_OFFSET1_EN,
|
|
OffsetState);
|
|
}
|
|
8004bbe: bf00 nop
|
|
8004bc0: 371c adds r7, #28
|
|
8004bc2: 46bd mov sp, r7
|
|
8004bc4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004bc8: 4770 bx lr
|
|
|
|
08004bca <LL_ADC_REG_IsTriggerSourceSWStart>:
|
|
* @param ADCx ADC instance
|
|
* @retval Value "0" if trigger source external trigger
|
|
* Value "1" if trigger source SW start.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
|
|
{
|
|
8004bca: b480 push {r7}
|
|
8004bcc: b083 sub sp, #12
|
|
8004bce: af00 add r7, sp, #0
|
|
8004bd0: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
|
|
8004bd2: 687b ldr r3, [r7, #4]
|
|
8004bd4: 68db ldr r3, [r3, #12]
|
|
8004bd6: f403 6340 and.w r3, r3, #3072 ; 0xc00
|
|
8004bda: 2b00 cmp r3, #0
|
|
8004bdc: d101 bne.n 8004be2 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
|
|
8004bde: 2301 movs r3, #1
|
|
8004be0: e000 b.n 8004be4 <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
|
|
8004be2: 2300 movs r3, #0
|
|
}
|
|
8004be4: 4618 mov r0, r3
|
|
8004be6: 370c adds r7, #12
|
|
8004be8: 46bd mov sp, r7
|
|
8004bea: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004bee: 4770 bx lr
|
|
|
|
08004bf0 <LL_ADC_REG_SetSequencerRanks>:
|
|
* (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
|
|
* Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
|
|
{
|
|
8004bf0: b480 push {r7}
|
|
8004bf2: b087 sub sp, #28
|
|
8004bf4: af00 add r7, sp, #0
|
|
8004bf6: 60f8 str r0, [r7, #12]
|
|
8004bf8: 60b9 str r1, [r7, #8]
|
|
8004bfa: 607a str r2, [r7, #4]
|
|
/* Set bits with content of parameter "Channel" with bits position */
|
|
/* in register and register position depending on parameter "Rank". */
|
|
/* Parameters "Rank" and "Channel" are used with masks because containing */
|
|
/* other bits reserved for other purpose. */
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
|
|
8004bfc: 68fb ldr r3, [r7, #12]
|
|
8004bfe: 3330 adds r3, #48 ; 0x30
|
|
8004c00: 461a mov r2, r3
|
|
8004c02: 68bb ldr r3, [r7, #8]
|
|
8004c04: 0a1b lsrs r3, r3, #8
|
|
8004c06: 009b lsls r3, r3, #2
|
|
8004c08: f003 030c and.w r3, r3, #12
|
|
8004c0c: 4413 add r3, r2
|
|
8004c0e: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
8004c10: 697b ldr r3, [r7, #20]
|
|
8004c12: 681a ldr r2, [r3, #0]
|
|
8004c14: 68bb ldr r3, [r7, #8]
|
|
8004c16: f003 031f and.w r3, r3, #31
|
|
8004c1a: 211f movs r1, #31
|
|
8004c1c: fa01 f303 lsl.w r3, r1, r3
|
|
8004c20: 43db mvns r3, r3
|
|
8004c22: 401a ands r2, r3
|
|
8004c24: 687b ldr r3, [r7, #4]
|
|
8004c26: 0e9b lsrs r3, r3, #26
|
|
8004c28: f003 011f and.w r1, r3, #31
|
|
8004c2c: 68bb ldr r3, [r7, #8]
|
|
8004c2e: f003 031f and.w r3, r3, #31
|
|
8004c32: fa01 f303 lsl.w r3, r1, r3
|
|
8004c36: 431a orrs r2, r3
|
|
8004c38: 697b ldr r3, [r7, #20]
|
|
8004c3a: 601a str r2, [r3, #0]
|
|
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
|
|
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
|
|
}
|
|
8004c3c: bf00 nop
|
|
8004c3e: 371c adds r7, #28
|
|
8004c40: 46bd mov sp, r7
|
|
8004c42: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c46: 4770 bx lr
|
|
|
|
08004c48 <LL_ADC_SetChannelSamplingTime>:
|
|
* can be replaced by 3.5 ADC clock cycles.
|
|
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
|
|
{
|
|
8004c48: b480 push {r7}
|
|
8004c4a: b087 sub sp, #28
|
|
8004c4c: af00 add r7, sp, #0
|
|
8004c4e: 60f8 str r0, [r7, #12]
|
|
8004c50: 60b9 str r1, [r7, #8]
|
|
8004c52: 607a str r2, [r7, #4]
|
|
/* Set bits with content of parameter "SamplingTime" with bits position */
|
|
/* in register and register position depending on parameter "Channel". */
|
|
/* Parameter "Channel" is used with masks because containing */
|
|
/* other bits reserved for other purpose. */
|
|
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
|
|
8004c54: 68fb ldr r3, [r7, #12]
|
|
8004c56: 3314 adds r3, #20
|
|
8004c58: 461a mov r2, r3
|
|
8004c5a: 68bb ldr r3, [r7, #8]
|
|
8004c5c: 0e5b lsrs r3, r3, #25
|
|
8004c5e: 009b lsls r3, r3, #2
|
|
8004c60: f003 0304 and.w r3, r3, #4
|
|
8004c64: 4413 add r3, r2
|
|
8004c66: 617b str r3, [r7, #20]
|
|
|
|
MODIFY_REG(*preg,
|
|
8004c68: 697b ldr r3, [r7, #20]
|
|
8004c6a: 681a ldr r2, [r3, #0]
|
|
8004c6c: 68bb ldr r3, [r7, #8]
|
|
8004c6e: 0d1b lsrs r3, r3, #20
|
|
8004c70: f003 031f and.w r3, r3, #31
|
|
8004c74: 2107 movs r1, #7
|
|
8004c76: fa01 f303 lsl.w r3, r1, r3
|
|
8004c7a: 43db mvns r3, r3
|
|
8004c7c: 401a ands r2, r3
|
|
8004c7e: 68bb ldr r3, [r7, #8]
|
|
8004c80: 0d1b lsrs r3, r3, #20
|
|
8004c82: f003 031f and.w r3, r3, #31
|
|
8004c86: 6879 ldr r1, [r7, #4]
|
|
8004c88: fa01 f303 lsl.w r3, r1, r3
|
|
8004c8c: 431a orrs r2, r3
|
|
8004c8e: 697b ldr r3, [r7, #20]
|
|
8004c90: 601a str r2, [r3, #0]
|
|
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
|
|
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
|
|
}
|
|
8004c92: bf00 nop
|
|
8004c94: 371c adds r7, #28
|
|
8004c96: 46bd mov sp, r7
|
|
8004c98: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c9c: 4770 bx lr
|
|
|
|
08004c9e <LL_ADC_SetChannelSingleDiff>:
|
|
* @arg @ref LL_ADC_SINGLE_ENDED
|
|
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
|
|
{
|
|
8004c9e: b480 push {r7}
|
|
8004ca0: b085 sub sp, #20
|
|
8004ca2: af00 add r7, sp, #0
|
|
8004ca4: 60f8 str r0, [r7, #12]
|
|
8004ca6: 60b9 str r1, [r7, #8]
|
|
8004ca8: 607a str r2, [r7, #4]
|
|
/* Bits of channels in single or differential mode are set only for */
|
|
/* differential mode (for single mode, mask of bits allowed to be set is */
|
|
/* shifted out of range of bits of channels in single or differential mode. */
|
|
MODIFY_REG(ADCx->DIFSEL,
|
|
8004caa: 68fb ldr r3, [r7, #12]
|
|
8004cac: f8d3 20b0 ldr.w r2, [r3, #176] ; 0xb0
|
|
8004cb0: 68bb ldr r3, [r7, #8]
|
|
8004cb2: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8004cb6: 43db mvns r3, r3
|
|
8004cb8: 401a ands r2, r3
|
|
8004cba: 687b ldr r3, [r7, #4]
|
|
8004cbc: f003 0118 and.w r1, r3, #24
|
|
8004cc0: f64f 73ff movw r3, #65535 ; 0xffff
|
|
8004cc4: f2c0 0307 movt r3, #7
|
|
8004cc8: fa23 f101 lsr.w r1, r3, r1
|
|
8004ccc: 68bb ldr r3, [r7, #8]
|
|
8004cce: 400b ands r3, r1
|
|
8004cd0: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8004cd4: 431a orrs r2, r3
|
|
8004cd6: 68fb ldr r3, [r7, #12]
|
|
8004cd8: f8c3 20b0 str.w r2, [r3, #176] ; 0xb0
|
|
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
|
|
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
|
|
}
|
|
8004cdc: bf00 nop
|
|
8004cde: 3714 adds r7, #20
|
|
8004ce0: 46bd mov sp, r7
|
|
8004ce2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ce6: 4770 bx lr
|
|
|
|
08004ce8 <LL_ADC_GetMultimode>:
|
|
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
|
|
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
|
|
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
|
|
{
|
|
8004ce8: b480 push {r7}
|
|
8004cea: b083 sub sp, #12
|
|
8004cec: af00 add r7, sp, #0
|
|
8004cee: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
|
|
8004cf0: 687b ldr r3, [r7, #4]
|
|
8004cf2: 689b ldr r3, [r3, #8]
|
|
8004cf4: f003 031f and.w r3, r3, #31
|
|
}
|
|
8004cf8: 4618 mov r0, r3
|
|
8004cfa: 370c adds r7, #12
|
|
8004cfc: 46bd mov sp, r7
|
|
8004cfe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d02: 4770 bx lr
|
|
|
|
08004d04 <LL_ADC_GetMultiDMATransfer>:
|
|
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
|
|
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
|
|
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
|
|
{
|
|
8004d04: b480 push {r7}
|
|
8004d06: b083 sub sp, #12
|
|
8004d08: af00 add r7, sp, #0
|
|
8004d0a: 6078 str r0, [r7, #4]
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
|
|
8004d0c: 687b ldr r3, [r7, #4]
|
|
8004d0e: 689b ldr r3, [r3, #8]
|
|
8004d10: f403 4360 and.w r3, r3, #57344 ; 0xe000
|
|
}
|
|
8004d14: 4618 mov r0, r3
|
|
8004d16: 370c adds r7, #12
|
|
8004d18: 46bd mov sp, r7
|
|
8004d1a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d1e: 4770 bx lr
|
|
|
|
08004d20 <LL_ADC_DisableDeepPowerDown>:
|
|
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
|
|
{
|
|
8004d20: b480 push {r7}
|
|
8004d22: b083 sub sp, #12
|
|
8004d24: af00 add r7, sp, #0
|
|
8004d26: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
|
|
8004d28: 687b ldr r3, [r7, #4]
|
|
8004d2a: 689b ldr r3, [r3, #8]
|
|
8004d2c: f023 4320 bic.w r3, r3, #2684354560 ; 0xa0000000
|
|
8004d30: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
8004d34: 687a ldr r2, [r7, #4]
|
|
8004d36: 6093 str r3, [r2, #8]
|
|
}
|
|
8004d38: bf00 nop
|
|
8004d3a: 370c adds r7, #12
|
|
8004d3c: 46bd mov sp, r7
|
|
8004d3e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d42: 4770 bx lr
|
|
|
|
08004d44 <LL_ADC_IsDeepPowerDownEnabled>:
|
|
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
|
|
* @param ADCx ADC instance
|
|
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
|
|
{
|
|
8004d44: b480 push {r7}
|
|
8004d46: b083 sub sp, #12
|
|
8004d48: af00 add r7, sp, #0
|
|
8004d4a: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
|
|
8004d4c: 687b ldr r3, [r7, #4]
|
|
8004d4e: 689b ldr r3, [r3, #8]
|
|
8004d50: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
|
8004d54: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
8004d58: d101 bne.n 8004d5e <LL_ADC_IsDeepPowerDownEnabled+0x1a>
|
|
8004d5a: 2301 movs r3, #1
|
|
8004d5c: e000 b.n 8004d60 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
|
|
8004d5e: 2300 movs r3, #0
|
|
}
|
|
8004d60: 4618 mov r0, r3
|
|
8004d62: 370c adds r7, #12
|
|
8004d64: 46bd mov sp, r7
|
|
8004d66: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d6a: 4770 bx lr
|
|
|
|
08004d6c <LL_ADC_EnableInternalRegulator>:
|
|
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
|
|
{
|
|
8004d6c: b480 push {r7}
|
|
8004d6e: b083 sub sp, #12
|
|
8004d70: af00 add r7, sp, #0
|
|
8004d72: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8004d74: 687b ldr r3, [r7, #4]
|
|
8004d76: 689b ldr r3, [r3, #8]
|
|
8004d78: f023 4310 bic.w r3, r3, #2415919104 ; 0x90000000
|
|
8004d7c: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
8004d80: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000
|
|
8004d84: 687b ldr r3, [r7, #4]
|
|
8004d86: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADVREGEN);
|
|
}
|
|
8004d88: bf00 nop
|
|
8004d8a: 370c adds r7, #12
|
|
8004d8c: 46bd mov sp, r7
|
|
8004d8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d92: 4770 bx lr
|
|
|
|
08004d94 <LL_ADC_IsInternalRegulatorEnabled>:
|
|
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
|
|
* @param ADCx ADC instance
|
|
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
|
|
{
|
|
8004d94: b480 push {r7}
|
|
8004d96: b083 sub sp, #12
|
|
8004d98: af00 add r7, sp, #0
|
|
8004d9a: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
|
|
8004d9c: 687b ldr r3, [r7, #4]
|
|
8004d9e: 689b ldr r3, [r3, #8]
|
|
8004da0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8004da4: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
|
|
8004da8: d101 bne.n 8004dae <LL_ADC_IsInternalRegulatorEnabled+0x1a>
|
|
8004daa: 2301 movs r3, #1
|
|
8004dac: e000 b.n 8004db0 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
|
|
8004dae: 2300 movs r3, #0
|
|
}
|
|
8004db0: 4618 mov r0, r3
|
|
8004db2: 370c adds r7, #12
|
|
8004db4: 46bd mov sp, r7
|
|
8004db6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004dba: 4770 bx lr
|
|
|
|
08004dbc <LL_ADC_Enable>:
|
|
* @rmtoll CR ADEN LL_ADC_Enable
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
|
|
{
|
|
8004dbc: b480 push {r7}
|
|
8004dbe: b083 sub sp, #12
|
|
8004dc0: af00 add r7, sp, #0
|
|
8004dc2: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8004dc4: 687b ldr r3, [r7, #4]
|
|
8004dc6: 689b ldr r3, [r3, #8]
|
|
8004dc8: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
|
|
8004dcc: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
8004dd0: f043 0201 orr.w r2, r3, #1
|
|
8004dd4: 687b ldr r3, [r7, #4]
|
|
8004dd6: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADEN);
|
|
}
|
|
8004dd8: bf00 nop
|
|
8004dda: 370c adds r7, #12
|
|
8004ddc: 46bd mov sp, r7
|
|
8004dde: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004de2: 4770 bx lr
|
|
|
|
08004de4 <LL_ADC_Disable>:
|
|
* @rmtoll CR ADDIS LL_ADC_Disable
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
|
|
{
|
|
8004de4: b480 push {r7}
|
|
8004de6: b083 sub sp, #12
|
|
8004de8: af00 add r7, sp, #0
|
|
8004dea: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8004dec: 687b ldr r3, [r7, #4]
|
|
8004dee: 689b ldr r3, [r3, #8]
|
|
8004df0: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
|
|
8004df4: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
8004df8: f043 0202 orr.w r2, r3, #2
|
|
8004dfc: 687b ldr r3, [r7, #4]
|
|
8004dfe: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADDIS);
|
|
}
|
|
8004e00: bf00 nop
|
|
8004e02: 370c adds r7, #12
|
|
8004e04: 46bd mov sp, r7
|
|
8004e06: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004e0a: 4770 bx lr
|
|
|
|
08004e0c <LL_ADC_IsEnabled>:
|
|
* @rmtoll CR ADEN LL_ADC_IsEnabled
|
|
* @param ADCx ADC instance
|
|
* @retval 0: ADC is disabled, 1: ADC is enabled.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
|
|
{
|
|
8004e0c: b480 push {r7}
|
|
8004e0e: b083 sub sp, #12
|
|
8004e10: af00 add r7, sp, #0
|
|
8004e12: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
|
|
8004e14: 687b ldr r3, [r7, #4]
|
|
8004e16: 689b ldr r3, [r3, #8]
|
|
8004e18: f003 0301 and.w r3, r3, #1
|
|
8004e1c: 2b01 cmp r3, #1
|
|
8004e1e: d101 bne.n 8004e24 <LL_ADC_IsEnabled+0x18>
|
|
8004e20: 2301 movs r3, #1
|
|
8004e22: e000 b.n 8004e26 <LL_ADC_IsEnabled+0x1a>
|
|
8004e24: 2300 movs r3, #0
|
|
}
|
|
8004e26: 4618 mov r0, r3
|
|
8004e28: 370c adds r7, #12
|
|
8004e2a: 46bd mov sp, r7
|
|
8004e2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004e30: 4770 bx lr
|
|
|
|
08004e32 <LL_ADC_IsDisableOngoing>:
|
|
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
|
|
* @param ADCx ADC instance
|
|
* @retval 0: no ADC disable command on going.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
|
|
{
|
|
8004e32: b480 push {r7}
|
|
8004e34: b083 sub sp, #12
|
|
8004e36: af00 add r7, sp, #0
|
|
8004e38: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
|
|
8004e3a: 687b ldr r3, [r7, #4]
|
|
8004e3c: 689b ldr r3, [r3, #8]
|
|
8004e3e: f003 0302 and.w r3, r3, #2
|
|
8004e42: 2b02 cmp r3, #2
|
|
8004e44: d101 bne.n 8004e4a <LL_ADC_IsDisableOngoing+0x18>
|
|
8004e46: 2301 movs r3, #1
|
|
8004e48: e000 b.n 8004e4c <LL_ADC_IsDisableOngoing+0x1a>
|
|
8004e4a: 2300 movs r3, #0
|
|
}
|
|
8004e4c: 4618 mov r0, r3
|
|
8004e4e: 370c adds r7, #12
|
|
8004e50: 46bd mov sp, r7
|
|
8004e52: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004e56: 4770 bx lr
|
|
|
|
08004e58 <LL_ADC_REG_StartConversion>:
|
|
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
|
|
{
|
|
8004e58: b480 push {r7}
|
|
8004e5a: b083 sub sp, #12
|
|
8004e5c: af00 add r7, sp, #0
|
|
8004e5e: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8004e60: 687b ldr r3, [r7, #4]
|
|
8004e62: 689b ldr r3, [r3, #8]
|
|
8004e64: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
|
|
8004e68: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
8004e6c: f043 0204 orr.w r2, r3, #4
|
|
8004e70: 687b ldr r3, [r7, #4]
|
|
8004e72: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADSTART);
|
|
}
|
|
8004e74: bf00 nop
|
|
8004e76: 370c adds r7, #12
|
|
8004e78: 46bd mov sp, r7
|
|
8004e7a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004e7e: 4770 bx lr
|
|
|
|
08004e80 <LL_ADC_REG_StopConversion>:
|
|
* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
|
|
{
|
|
8004e80: b480 push {r7}
|
|
8004e82: b083 sub sp, #12
|
|
8004e84: af00 add r7, sp, #0
|
|
8004e86: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8004e88: 687b ldr r3, [r7, #4]
|
|
8004e8a: 689b ldr r3, [r3, #8]
|
|
8004e8c: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
|
|
8004e90: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
8004e94: f043 0210 orr.w r2, r3, #16
|
|
8004e98: 687b ldr r3, [r7, #4]
|
|
8004e9a: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_ADSTP);
|
|
}
|
|
8004e9c: bf00 nop
|
|
8004e9e: 370c adds r7, #12
|
|
8004ea0: 46bd mov sp, r7
|
|
8004ea2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ea6: 4770 bx lr
|
|
|
|
08004ea8 <LL_ADC_REG_IsConversionOngoing>:
|
|
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
|
|
* @param ADCx ADC instance
|
|
* @retval 0: no conversion is on going on ADC group regular.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
|
|
{
|
|
8004ea8: b480 push {r7}
|
|
8004eaa: b083 sub sp, #12
|
|
8004eac: af00 add r7, sp, #0
|
|
8004eae: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
|
|
8004eb0: 687b ldr r3, [r7, #4]
|
|
8004eb2: 689b ldr r3, [r3, #8]
|
|
8004eb4: f003 0304 and.w r3, r3, #4
|
|
8004eb8: 2b04 cmp r3, #4
|
|
8004eba: d101 bne.n 8004ec0 <LL_ADC_REG_IsConversionOngoing+0x18>
|
|
8004ebc: 2301 movs r3, #1
|
|
8004ebe: e000 b.n 8004ec2 <LL_ADC_REG_IsConversionOngoing+0x1a>
|
|
8004ec0: 2300 movs r3, #0
|
|
}
|
|
8004ec2: 4618 mov r0, r3
|
|
8004ec4: 370c adds r7, #12
|
|
8004ec6: 46bd mov sp, r7
|
|
8004ec8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ecc: 4770 bx lr
|
|
|
|
08004ece <LL_ADC_INJ_StopConversion>:
|
|
* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
|
|
* @param ADCx ADC instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
|
|
{
|
|
8004ece: b480 push {r7}
|
|
8004ed0: b083 sub sp, #12
|
|
8004ed2: af00 add r7, sp, #0
|
|
8004ed4: 6078 str r0, [r7, #4]
|
|
/* Note: Write register with some additional bits forced to state reset */
|
|
/* instead of modifying only the selected bit for this function, */
|
|
/* to not interfere with bits with HW property "rs". */
|
|
MODIFY_REG(ADCx->CR,
|
|
8004ed6: 687b ldr r3, [r7, #4]
|
|
8004ed8: 689b ldr r3, [r3, #8]
|
|
8004eda: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
|
|
8004ede: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
8004ee2: f043 0220 orr.w r2, r3, #32
|
|
8004ee6: 687b ldr r3, [r7, #4]
|
|
8004ee8: 609a str r2, [r3, #8]
|
|
ADC_CR_BITS_PROPERTY_RS,
|
|
ADC_CR_JADSTP);
|
|
}
|
|
8004eea: bf00 nop
|
|
8004eec: 370c adds r7, #12
|
|
8004eee: 46bd mov sp, r7
|
|
8004ef0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004ef4: 4770 bx lr
|
|
|
|
08004ef6 <LL_ADC_INJ_IsConversionOngoing>:
|
|
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
|
|
* @param ADCx ADC instance
|
|
* @retval 0: no conversion is on going on ADC group injected.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
|
|
{
|
|
8004ef6: b480 push {r7}
|
|
8004ef8: b083 sub sp, #12
|
|
8004efa: af00 add r7, sp, #0
|
|
8004efc: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
|
|
8004efe: 687b ldr r3, [r7, #4]
|
|
8004f00: 689b ldr r3, [r3, #8]
|
|
8004f02: f003 0308 and.w r3, r3, #8
|
|
8004f06: 2b08 cmp r3, #8
|
|
8004f08: d101 bne.n 8004f0e <LL_ADC_INJ_IsConversionOngoing+0x18>
|
|
8004f0a: 2301 movs r3, #1
|
|
8004f0c: e000 b.n 8004f10 <LL_ADC_INJ_IsConversionOngoing+0x1a>
|
|
8004f0e: 2300 movs r3, #0
|
|
}
|
|
8004f10: 4618 mov r0, r3
|
|
8004f12: 370c adds r7, #12
|
|
8004f14: 46bd mov sp, r7
|
|
8004f16: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004f1a: 4770 bx lr
|
|
|
|
08004f1c <HAL_ADC_Init>:
|
|
* without disabling the other ADCs.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8004f1c: b590 push {r4, r7, lr}
|
|
8004f1e: b089 sub sp, #36 ; 0x24
|
|
8004f20: af00 add r7, sp, #0
|
|
8004f22: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8004f24: 2300 movs r3, #0
|
|
8004f26: 77fb strb r3, [r7, #31]
|
|
uint32_t tmpCFGR;
|
|
uint32_t tmp_adc_reg_is_conversion_on_going;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8004f28: 2300 movs r3, #0
|
|
8004f2a: 60bb str r3, [r7, #8]
|
|
uint32_t tmp_adc_is_conversion_on_going_regular;
|
|
uint32_t tmp_adc_is_conversion_on_going_injected;
|
|
|
|
/* Check ADC handle */
|
|
if (hadc == NULL)
|
|
8004f2c: 687b ldr r3, [r7, #4]
|
|
8004f2e: 2b00 cmp r3, #0
|
|
8004f30: d101 bne.n 8004f36 <HAL_ADC_Init+0x1a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004f32: 2301 movs r3, #1
|
|
8004f34: e14a b.n 80051cc <HAL_ADC_Init+0x2b0>
|
|
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
|
|
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
|
|
|
|
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
|
|
8004f36: 687b ldr r3, [r7, #4]
|
|
8004f38: 691b ldr r3, [r3, #16]
|
|
8004f3a: 2b00 cmp r3, #0
|
|
/* DISCEN and CONT bits cannot be set at the same time */
|
|
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
|
|
|
|
/* Actions performed only if ADC is coming from state reset: */
|
|
/* - Initialization of ADC MSP */
|
|
if (hadc->State == HAL_ADC_STATE_RESET)
|
|
8004f3c: 687b ldr r3, [r7, #4]
|
|
8004f3e: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8004f40: 2b00 cmp r3, #0
|
|
8004f42: d109 bne.n 8004f58 <HAL_ADC_Init+0x3c>
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
8004f44: 6878 ldr r0, [r7, #4]
|
|
8004f46: f7fd fc01 bl 800274c <HAL_ADC_MspInit>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8004f4a: 687b ldr r3, [r7, #4]
|
|
8004f4c: 2200 movs r2, #0
|
|
8004f4e: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
/* Initialize Lock */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
8004f50: 687b ldr r3, [r7, #4]
|
|
8004f52: 2200 movs r2, #0
|
|
8004f54: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
}
|
|
|
|
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
|
|
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
|
|
8004f58: 687b ldr r3, [r7, #4]
|
|
8004f5a: 681b ldr r3, [r3, #0]
|
|
8004f5c: 4618 mov r0, r3
|
|
8004f5e: f7ff fef1 bl 8004d44 <LL_ADC_IsDeepPowerDownEnabled>
|
|
8004f62: 4603 mov r3, r0
|
|
8004f64: 2b00 cmp r3, #0
|
|
8004f66: d004 beq.n 8004f72 <HAL_ADC_Init+0x56>
|
|
{
|
|
/* Disable ADC deep power down mode */
|
|
LL_ADC_DisableDeepPowerDown(hadc->Instance);
|
|
8004f68: 687b ldr r3, [r7, #4]
|
|
8004f6a: 681b ldr r3, [r3, #0]
|
|
8004f6c: 4618 mov r0, r3
|
|
8004f6e: f7ff fed7 bl 8004d20 <LL_ADC_DisableDeepPowerDown>
|
|
/* System was in deep power down mode, calibration must
|
|
be relaunched or a previously saved calibration factor
|
|
re-applied once the ADC voltage regulator is enabled */
|
|
}
|
|
|
|
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
|
|
8004f72: 687b ldr r3, [r7, #4]
|
|
8004f74: 681b ldr r3, [r3, #0]
|
|
8004f76: 4618 mov r0, r3
|
|
8004f78: f7ff ff0c bl 8004d94 <LL_ADC_IsInternalRegulatorEnabled>
|
|
8004f7c: 4603 mov r3, r0
|
|
8004f7e: 2b00 cmp r3, #0
|
|
8004f80: d11b bne.n 8004fba <HAL_ADC_Init+0x9e>
|
|
{
|
|
/* Enable ADC internal voltage regulator */
|
|
LL_ADC_EnableInternalRegulator(hadc->Instance);
|
|
8004f82: 687b ldr r3, [r7, #4]
|
|
8004f84: 681b ldr r3, [r3, #0]
|
|
8004f86: 4618 mov r0, r3
|
|
8004f88: f7ff fef0 bl 8004d6c <LL_ADC_EnableInternalRegulator>
|
|
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles, scaling in us split to not */
|
|
/* exceed 32 bits register capacity and handle low frequency. */
|
|
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
8004f8c: f240 234c movw r3, #588 ; 0x24c
|
|
8004f90: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8004f94: 681b ldr r3, [r3, #0]
|
|
8004f96: 099a lsrs r2, r3, #6
|
|
8004f98: f642 5363 movw r3, #11619 ; 0x2d63
|
|
8004f9c: f2c0 533e movt r3, #1342 ; 0x53e
|
|
8004fa0: fba3 2302 umull r2, r3, r3, r2
|
|
8004fa4: 099b lsrs r3, r3, #6
|
|
8004fa6: 3301 adds r3, #1
|
|
8004fa8: 005b lsls r3, r3, #1
|
|
8004faa: 60bb str r3, [r7, #8]
|
|
while (wait_loop_index != 0UL)
|
|
8004fac: e002 b.n 8004fb4 <HAL_ADC_Init+0x98>
|
|
{
|
|
wait_loop_index--;
|
|
8004fae: 68bb ldr r3, [r7, #8]
|
|
8004fb0: 3b01 subs r3, #1
|
|
8004fb2: 60bb str r3, [r7, #8]
|
|
while (wait_loop_index != 0UL)
|
|
8004fb4: 68bb ldr r3, [r7, #8]
|
|
8004fb6: 2b00 cmp r3, #0
|
|
8004fb8: d1f9 bne.n 8004fae <HAL_ADC_Init+0x92>
|
|
}
|
|
|
|
/* Verification that ADC voltage regulator is correctly enabled, whether */
|
|
/* or not ADC is coming from state reset (if any potential problem of */
|
|
/* clocking, voltage regulator would not be enabled). */
|
|
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
|
|
8004fba: 687b ldr r3, [r7, #4]
|
|
8004fbc: 681b ldr r3, [r3, #0]
|
|
8004fbe: 4618 mov r0, r3
|
|
8004fc0: f7ff fee8 bl 8004d94 <LL_ADC_IsInternalRegulatorEnabled>
|
|
8004fc4: 4603 mov r3, r0
|
|
8004fc6: 2b00 cmp r3, #0
|
|
8004fc8: d10d bne.n 8004fe6 <HAL_ADC_Init+0xca>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8004fca: 687b ldr r3, [r7, #4]
|
|
8004fcc: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8004fce: f043 0210 orr.w r2, r3, #16
|
|
8004fd2: 687b ldr r3, [r7, #4]
|
|
8004fd4: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8004fd6: 687b ldr r3, [r7, #4]
|
|
8004fd8: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8004fda: f043 0201 orr.w r2, r3, #1
|
|
8004fde: 687b ldr r3, [r7, #4]
|
|
8004fe0: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8004fe2: 2301 movs r3, #1
|
|
8004fe4: 77fb strb r3, [r7, #31]
|
|
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed and if there is no conversion on going on regular */
|
|
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
|
|
/* called to update a parameter on the fly). */
|
|
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
8004fe6: 687b ldr r3, [r7, #4]
|
|
8004fe8: 681b ldr r3, [r3, #0]
|
|
8004fea: 4618 mov r0, r3
|
|
8004fec: f7ff ff5c bl 8004ea8 <LL_ADC_REG_IsConversionOngoing>
|
|
8004ff0: 6178 str r0, [r7, #20]
|
|
|
|
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
|
|
8004ff2: 687b ldr r3, [r7, #4]
|
|
8004ff4: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8004ff6: f003 0310 and.w r3, r3, #16
|
|
8004ffa: 2b00 cmp r3, #0
|
|
8004ffc: f040 80dd bne.w 80051ba <HAL_ADC_Init+0x29e>
|
|
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
|
|
8005000: 697b ldr r3, [r7, #20]
|
|
8005002: 2b00 cmp r3, #0
|
|
8005004: f040 80d9 bne.w 80051ba <HAL_ADC_Init+0x29e>
|
|
)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8005008: 687b ldr r3, [r7, #4]
|
|
800500a: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800500c: f423 7381 bic.w r3, r3, #258 ; 0x102
|
|
8005010: f043 0202 orr.w r2, r3, #2
|
|
8005014: 687b ldr r3, [r7, #4]
|
|
8005016: 655a str r2, [r3, #84] ; 0x54
|
|
/* Configuration of common ADC parameters */
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - clock configuration */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
8005018: 687b ldr r3, [r7, #4]
|
|
800501a: 681b ldr r3, [r3, #0]
|
|
800501c: 4618 mov r0, r3
|
|
800501e: f7ff fef5 bl 8004e0c <LL_ADC_IsEnabled>
|
|
8005022: 4603 mov r3, r0
|
|
8005024: 2b00 cmp r3, #0
|
|
8005026: d120 bne.n 800506a <HAL_ADC_Init+0x14e>
|
|
{
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
8005028: 2000 movs r0, #0
|
|
800502a: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
800502e: f7ff feed bl 8004e0c <LL_ADC_IsEnabled>
|
|
8005032: 4604 mov r4, r0
|
|
8005034: f44f 7080 mov.w r0, #256 ; 0x100
|
|
8005038: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
800503c: f7ff fee6 bl 8004e0c <LL_ADC_IsEnabled>
|
|
8005040: 4603 mov r3, r0
|
|
8005042: 431c orrs r4, r3
|
|
8005044: f44f 7000 mov.w r0, #512 ; 0x200
|
|
8005048: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
800504c: f7ff fede bl 8004e0c <LL_ADC_IsEnabled>
|
|
8005050: 4603 mov r3, r0
|
|
8005052: 4323 orrs r3, r4
|
|
8005054: 2b00 cmp r3, #0
|
|
8005056: d108 bne.n 800506a <HAL_ADC_Init+0x14e>
|
|
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
|
|
/* HAL_ADCEx_MultiModeConfigChannel() ) */
|
|
/* - internal measurement paths: Vbat, temperature sensor, Vref */
|
|
/* (set into HAL_ADC_ConfigChannel() or */
|
|
/* HAL_ADCEx_InjectedConfigChannel() ) */
|
|
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
|
|
8005058: 687b ldr r3, [r7, #4]
|
|
800505a: 685b ldr r3, [r3, #4]
|
|
800505c: 4619 mov r1, r3
|
|
800505e: f44f 7040 mov.w r0, #768 ; 0x300
|
|
8005062: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8005066: f7ff fd26 bl 8004ab6 <LL_ADC_SetCommonClock>
|
|
/* - external trigger polarity Init.ExternalTrigConvEdge */
|
|
/* - continuous conversion mode Init.ContinuousConvMode */
|
|
/* - overrun Init.Overrun */
|
|
/* - discontinuous mode Init.DiscontinuousConvMode */
|
|
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
|
|
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
800506a: 687b ldr r3, [r7, #4]
|
|
800506c: 7e5b ldrb r3, [r3, #25]
|
|
800506e: 035a lsls r2, r3, #13
|
|
hadc->Init.Overrun |
|
|
8005070: 687b ldr r3, [r7, #4]
|
|
8005072: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
8005074: 431a orrs r2, r3
|
|
hadc->Init.DataAlign |
|
|
8005076: 687b ldr r3, [r7, #4]
|
|
8005078: 68db ldr r3, [r3, #12]
|
|
hadc->Init.Overrun |
|
|
800507a: 431a orrs r2, r3
|
|
hadc->Init.Resolution |
|
|
800507c: 687b ldr r3, [r7, #4]
|
|
800507e: 689b ldr r3, [r3, #8]
|
|
hadc->Init.DataAlign |
|
|
8005080: 431a orrs r2, r3
|
|
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
|
|
8005082: 687b ldr r3, [r7, #4]
|
|
8005084: f893 3020 ldrb.w r3, [r3, #32]
|
|
8005088: 041b lsls r3, r3, #16
|
|
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
800508a: 4313 orrs r3, r2
|
|
800508c: 61bb str r3, [r7, #24]
|
|
|
|
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
|
800508e: 687b ldr r3, [r7, #4]
|
|
8005090: f893 3020 ldrb.w r3, [r3, #32]
|
|
8005094: 2b01 cmp r3, #1
|
|
8005096: d106 bne.n 80050a6 <HAL_ADC_Init+0x18a>
|
|
{
|
|
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
|
|
8005098: 687b ldr r3, [r7, #4]
|
|
800509a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800509c: 3b01 subs r3, #1
|
|
800509e: 045b lsls r3, r3, #17
|
|
80050a0: 69ba ldr r2, [r7, #24]
|
|
80050a2: 4313 orrs r3, r2
|
|
80050a4: 61bb str r3, [r7, #24]
|
|
/* Enable external trigger if trigger selection is different of software */
|
|
/* start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
|
80050a6: 687b ldr r3, [r7, #4]
|
|
80050a8: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
80050aa: 2b00 cmp r3, #0
|
|
80050ac: d009 beq.n 80050c2 <HAL_ADC_Init+0x1a6>
|
|
{
|
|
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
|
|
80050ae: 687b ldr r3, [r7, #4]
|
|
80050b0: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
80050b2: f403 7270 and.w r2, r3, #960 ; 0x3c0
|
|
| hadc->Init.ExternalTrigConvEdge
|
|
80050b6: 687b ldr r3, [r7, #4]
|
|
80050b8: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
80050ba: 4313 orrs r3, r2
|
|
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
|
|
80050bc: 69ba ldr r2, [r7, #24]
|
|
80050be: 4313 orrs r3, r2
|
|
80050c0: 61bb str r3, [r7, #24]
|
|
);
|
|
}
|
|
|
|
/* Update Configuration Register CFGR */
|
|
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
|
|
80050c2: 687b ldr r3, [r7, #4]
|
|
80050c4: 681b ldr r3, [r3, #0]
|
|
80050c6: 68da ldr r2, [r3, #12]
|
|
80050c8: f24c 0307 movw r3, #49159 ; 0xc007
|
|
80050cc: f6cf 73f0 movt r3, #65520 ; 0xfff0
|
|
80050d0: 4013 ands r3, r2
|
|
80050d2: 687a ldr r2, [r7, #4]
|
|
80050d4: 6812 ldr r2, [r2, #0]
|
|
80050d6: 69b9 ldr r1, [r7, #24]
|
|
80050d8: 430b orrs r3, r1
|
|
80050da: 60d3 str r3, [r2, #12]
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular and injected groups: */
|
|
/* - DMA continuous request Init.DMAContinuousRequests */
|
|
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
|
|
/* - Oversampling parameters Init.Oversampling */
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
80050dc: 687b ldr r3, [r7, #4]
|
|
80050de: 681b ldr r3, [r3, #0]
|
|
80050e0: 4618 mov r0, r3
|
|
80050e2: f7ff fee1 bl 8004ea8 <LL_ADC_REG_IsConversionOngoing>
|
|
80050e6: 6138 str r0, [r7, #16]
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
80050e8: 687b ldr r3, [r7, #4]
|
|
80050ea: 681b ldr r3, [r3, #0]
|
|
80050ec: 4618 mov r0, r3
|
|
80050ee: f7ff ff02 bl 8004ef6 <LL_ADC_INJ_IsConversionOngoing>
|
|
80050f2: 60f8 str r0, [r7, #12]
|
|
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
80050f4: 693b ldr r3, [r7, #16]
|
|
80050f6: 2b00 cmp r3, #0
|
|
80050f8: d13d bne.n 8005176 <HAL_ADC_Init+0x25a>
|
|
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
|
80050fa: 68fb ldr r3, [r7, #12]
|
|
80050fc: 2b00 cmp r3, #0
|
|
80050fe: d13a bne.n 8005176 <HAL_ADC_Init+0x25a>
|
|
)
|
|
{
|
|
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
|
|
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
8005100: 687b ldr r3, [r7, #4]
|
|
8005102: 7e1b ldrb r3, [r3, #24]
|
|
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
|
|
8005104: 039a lsls r2, r3, #14
|
|
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
|
|
8005106: 687b ldr r3, [r7, #4]
|
|
8005108: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
800510c: 005b lsls r3, r3, #1
|
|
tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
|
|
800510e: 4313 orrs r3, r2
|
|
8005110: 61bb str r3, [r7, #24]
|
|
|
|
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
|
|
8005112: 687b ldr r3, [r7, #4]
|
|
8005114: 681b ldr r3, [r3, #0]
|
|
8005116: 68db ldr r3, [r3, #12]
|
|
8005118: f423 4380 bic.w r3, r3, #16384 ; 0x4000
|
|
800511c: f023 0302 bic.w r3, r3, #2
|
|
8005120: 687a ldr r2, [r7, #4]
|
|
8005122: 6812 ldr r2, [r2, #0]
|
|
8005124: 69b9 ldr r1, [r7, #24]
|
|
8005126: 430b orrs r3, r1
|
|
8005128: 60d3 str r3, [r2, #12]
|
|
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
800512a: 687b ldr r3, [r7, #4]
|
|
800512c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
|
|
8005130: 2b01 cmp r3, #1
|
|
8005132: d118 bne.n 8005166 <HAL_ADC_Init+0x24a>
|
|
/* Configuration of Oversampler: */
|
|
/* - Oversampling Ratio */
|
|
/* - Right bit shift */
|
|
/* - Triggered mode */
|
|
/* - Oversampling mode (continued/resumed) */
|
|
MODIFY_REG(hadc->Instance->CFGR2,
|
|
8005134: 687b ldr r3, [r7, #4]
|
|
8005136: 681b ldr r3, [r3, #0]
|
|
8005138: 691b ldr r3, [r3, #16]
|
|
800513a: f423 63ff bic.w r3, r3, #2040 ; 0x7f8
|
|
800513e: f023 0304 bic.w r3, r3, #4
|
|
8005142: 687a ldr r2, [r7, #4]
|
|
8005144: 6bd1 ldr r1, [r2, #60] ; 0x3c
|
|
8005146: 687a ldr r2, [r7, #4]
|
|
8005148: 6c12 ldr r2, [r2, #64] ; 0x40
|
|
800514a: 4311 orrs r1, r2
|
|
800514c: 687a ldr r2, [r7, #4]
|
|
800514e: 6c52 ldr r2, [r2, #68] ; 0x44
|
|
8005150: 4311 orrs r1, r2
|
|
8005152: 687a ldr r2, [r7, #4]
|
|
8005154: 6c92 ldr r2, [r2, #72] ; 0x48
|
|
8005156: 430a orrs r2, r1
|
|
8005158: 431a orrs r2, r3
|
|
800515a: 687b ldr r3, [r7, #4]
|
|
800515c: 681b ldr r3, [r3, #0]
|
|
800515e: f042 0201 orr.w r2, r2, #1
|
|
8005162: 611a str r2, [r3, #16]
|
|
8005164: e007 b.n 8005176 <HAL_ADC_Init+0x25a>
|
|
);
|
|
}
|
|
else
|
|
{
|
|
/* Disable ADC oversampling scope on ADC group regular */
|
|
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
|
|
8005166: 687b ldr r3, [r7, #4]
|
|
8005168: 681b ldr r3, [r3, #0]
|
|
800516a: 691a ldr r2, [r3, #16]
|
|
800516c: 687b ldr r3, [r7, #4]
|
|
800516e: 681b ldr r3, [r3, #0]
|
|
8005170: f022 0201 bic.w r2, r2, #1
|
|
8005174: 611a str r2, [r3, #16]
|
|
/* Note: Scan mode is not present by hardware on this device, but */
|
|
/* emulated by software for alignment over all STM32 devices. */
|
|
/* - if scan mode is enabled, regular channels sequence length is set to */
|
|
/* parameter "NbrOfConversion". */
|
|
|
|
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
|
|
8005176: 687b ldr r3, [r7, #4]
|
|
8005178: 691b ldr r3, [r3, #16]
|
|
800517a: 2b01 cmp r3, #1
|
|
800517c: d10c bne.n 8005198 <HAL_ADC_Init+0x27c>
|
|
{
|
|
/* Set number of ranks in regular group sequencer */
|
|
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
|
|
800517e: 687b ldr r3, [r7, #4]
|
|
8005180: 681b ldr r3, [r3, #0]
|
|
8005182: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8005184: f023 010f bic.w r1, r3, #15
|
|
8005188: 687b ldr r3, [r7, #4]
|
|
800518a: 69db ldr r3, [r3, #28]
|
|
800518c: 1e5a subs r2, r3, #1
|
|
800518e: 687b ldr r3, [r7, #4]
|
|
8005190: 681b ldr r3, [r3, #0]
|
|
8005192: 430a orrs r2, r1
|
|
8005194: 631a str r2, [r3, #48] ; 0x30
|
|
8005196: e007 b.n 80051a8 <HAL_ADC_Init+0x28c>
|
|
}
|
|
else
|
|
{
|
|
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
|
|
8005198: 687b ldr r3, [r7, #4]
|
|
800519a: 681b ldr r3, [r3, #0]
|
|
800519c: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
800519e: 687b ldr r3, [r7, #4]
|
|
80051a0: 681b ldr r3, [r3, #0]
|
|
80051a2: f022 020f bic.w r2, r2, #15
|
|
80051a6: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* Initialize the ADC state */
|
|
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
|
|
80051a8: 687b ldr r3, [r7, #4]
|
|
80051aa: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80051ac: f023 0303 bic.w r3, r3, #3
|
|
80051b0: f043 0201 orr.w r2, r3, #1
|
|
80051b4: 687b ldr r3, [r7, #4]
|
|
80051b6: 655a str r2, [r3, #84] ; 0x54
|
|
80051b8: e007 b.n 80051ca <HAL_ADC_Init+0x2ae>
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80051ba: 687b ldr r3, [r7, #4]
|
|
80051bc: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80051be: f043 0210 orr.w r2, r3, #16
|
|
80051c2: 687b ldr r3, [r7, #4]
|
|
80051c4: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
80051c6: 2301 movs r3, #1
|
|
80051c8: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
80051ca: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
80051cc: 4618 mov r0, r3
|
|
80051ce: 3724 adds r7, #36 ; 0x24
|
|
80051d0: 46bd mov sp, r7
|
|
80051d2: bd90 pop {r4, r7, pc}
|
|
|
|
080051d4 <HAL_ADC_Start>:
|
|
* if ADC is master, ADC is enabled and multimode conversion is started.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
|
|
{
|
|
80051d4: b580 push {r7, lr}
|
|
80051d6: b086 sub sp, #24
|
|
80051d8: af00 add r7, sp, #0
|
|
80051da: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
const ADC_TypeDef *tmpADC_Master;
|
|
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
80051dc: f44f 7040 mov.w r0, #768 ; 0x300
|
|
80051e0: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
80051e4: f7ff fd80 bl 8004ce8 <LL_ADC_GetMultimode>
|
|
80051e8: 6138 str r0, [r7, #16]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Perform ADC enable and conversion start if no conversion is on going */
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
80051ea: 687b ldr r3, [r7, #4]
|
|
80051ec: 681b ldr r3, [r3, #0]
|
|
80051ee: 4618 mov r0, r3
|
|
80051f0: f7ff fe5a bl 8004ea8 <LL_ADC_REG_IsConversionOngoing>
|
|
80051f4: 4603 mov r3, r0
|
|
80051f6: 2b00 cmp r3, #0
|
|
80051f8: f040 80ab bne.w 8005352 <HAL_ADC_Start+0x17e>
|
|
{
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
80051fc: 687b ldr r3, [r7, #4]
|
|
80051fe: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
|
|
8005202: 2b01 cmp r3, #1
|
|
8005204: d101 bne.n 800520a <HAL_ADC_Start+0x36>
|
|
8005206: 2302 movs r3, #2
|
|
8005208: e0a6 b.n 8005358 <HAL_ADC_Start+0x184>
|
|
800520a: 687b ldr r3, [r7, #4]
|
|
800520c: 2201 movs r2, #1
|
|
800520e: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* Enable the ADC peripheral */
|
|
tmp_hal_status = ADC_Enable(hadc);
|
|
8005212: 6878 ldr r0, [r7, #4]
|
|
8005214: f000 fe86 bl 8005f24 <ADC_Enable>
|
|
8005218: 4603 mov r3, r0
|
|
800521a: 75fb strb r3, [r7, #23]
|
|
|
|
/* Start conversion if ADC is effectively enabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
800521c: 7dfb ldrb r3, [r7, #23]
|
|
800521e: 2b00 cmp r3, #0
|
|
8005220: f040 8092 bne.w 8005348 <HAL_ADC_Start+0x174>
|
|
{
|
|
/* Set ADC state */
|
|
/* - Clear state bitfield related to regular group conversion results */
|
|
/* - Set state bitfield related to regular operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8005224: 687b ldr r3, [r7, #4]
|
|
8005226: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005228: f423 6370 bic.w r3, r3, #3840 ; 0xf00
|
|
800522c: f023 0301 bic.w r3, r3, #1
|
|
8005230: f443 7280 orr.w r2, r3, #256 ; 0x100
|
|
8005234: 687b ldr r3, [r7, #4]
|
|
8005236: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
|
|
- if ADC instance is master or if multimode feature is not available
|
|
- if multimode setting is disabled (ADC instance slave in independent mode) */
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
8005238: 687b ldr r3, [r7, #4]
|
|
800523a: 681a ldr r2, [r3, #0]
|
|
800523c: f44f 7380 mov.w r3, #256 ; 0x100
|
|
8005240: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005244: 429a cmp r2, r3
|
|
8005246: d002 beq.n 800524e <HAL_ADC_Start+0x7a>
|
|
8005248: 687b ldr r3, [r7, #4]
|
|
800524a: 681b ldr r3, [r3, #0]
|
|
800524c: e002 b.n 8005254 <HAL_ADC_Start+0x80>
|
|
800524e: 2300 movs r3, #0
|
|
8005250: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005254: 687a ldr r2, [r7, #4]
|
|
8005256: 6812 ldr r2, [r2, #0]
|
|
8005258: 4293 cmp r3, r2
|
|
800525a: d002 beq.n 8005262 <HAL_ADC_Start+0x8e>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
800525c: 693b ldr r3, [r7, #16]
|
|
800525e: 2b00 cmp r3, #0
|
|
8005260: d105 bne.n 800526e <HAL_ADC_Start+0x9a>
|
|
)
|
|
{
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
8005262: 687b ldr r3, [r7, #4]
|
|
8005264: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005266: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
|
|
800526a: 687b ldr r3, [r7, #4]
|
|
800526c: 655a str r2, [r3, #84] ; 0x54
|
|
}
|
|
#endif
|
|
|
|
/* Set ADC error code */
|
|
/* Check if a conversion is on going on ADC group injected */
|
|
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
|
|
800526e: 687b ldr r3, [r7, #4]
|
|
8005270: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005272: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
|
8005276: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800527a: d106 bne.n 800528a <HAL_ADC_Start+0xb6>
|
|
{
|
|
/* Reset ADC error code fields related to regular conversions only */
|
|
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
|
|
800527c: 687b ldr r3, [r7, #4]
|
|
800527e: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8005280: f023 0206 bic.w r2, r3, #6
|
|
8005284: 687b ldr r3, [r7, #4]
|
|
8005286: 659a str r2, [r3, #88] ; 0x58
|
|
8005288: e002 b.n 8005290 <HAL_ADC_Start+0xbc>
|
|
}
|
|
else
|
|
{
|
|
/* Reset all ADC error code fields */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
800528a: 687b ldr r3, [r7, #4]
|
|
800528c: 2200 movs r2, #0
|
|
800528e: 659a str r2, [r3, #88] ; 0x58
|
|
}
|
|
|
|
/* Clear ADC group regular conversion flag and overrun flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
|
|
8005290: 687b ldr r3, [r7, #4]
|
|
8005292: 681b ldr r3, [r3, #0]
|
|
8005294: 221c movs r2, #28
|
|
8005296: 601a str r2, [r3, #0]
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
8005298: 687b ldr r3, [r7, #4]
|
|
800529a: 2200 movs r2, #0
|
|
800529c: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
/* Case of multimode enabled (when multimode feature is available): */
|
|
/* - if ADC is slave and dual regular conversions are enabled, ADC is */
|
|
/* enabled only (conversion is not started), */
|
|
/* - if ADC is master, ADC is enabled and conversion is started. */
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
80052a0: 687b ldr r3, [r7, #4]
|
|
80052a2: 681a ldr r2, [r3, #0]
|
|
80052a4: f44f 7380 mov.w r3, #256 ; 0x100
|
|
80052a8: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
80052ac: 429a cmp r2, r3
|
|
80052ae: d002 beq.n 80052b6 <HAL_ADC_Start+0xe2>
|
|
80052b0: 687b ldr r3, [r7, #4]
|
|
80052b2: 681b ldr r3, [r3, #0]
|
|
80052b4: e002 b.n 80052bc <HAL_ADC_Start+0xe8>
|
|
80052b6: 2300 movs r3, #0
|
|
80052b8: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
80052bc: 687a ldr r2, [r7, #4]
|
|
80052be: 6812 ldr r2, [r2, #0]
|
|
80052c0: 4293 cmp r3, r2
|
|
80052c2: d008 beq.n 80052d6 <HAL_ADC_Start+0x102>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
80052c4: 693b ldr r3, [r7, #16]
|
|
80052c6: 2b00 cmp r3, #0
|
|
80052c8: d005 beq.n 80052d6 <HAL_ADC_Start+0x102>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|
|
80052ca: 693b ldr r3, [r7, #16]
|
|
80052cc: 2b05 cmp r3, #5
|
|
80052ce: d002 beq.n 80052d6 <HAL_ADC_Start+0x102>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
|
|
80052d0: 693b ldr r3, [r7, #16]
|
|
80052d2: 2b09 cmp r3, #9
|
|
80052d4: d114 bne.n 8005300 <HAL_ADC_Start+0x12c>
|
|
)
|
|
{
|
|
/* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
|
|
80052d6: 687b ldr r3, [r7, #4]
|
|
80052d8: 681b ldr r3, [r3, #0]
|
|
80052da: 68db ldr r3, [r3, #12]
|
|
80052dc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80052e0: 2b00 cmp r3, #0
|
|
80052e2: d007 beq.n 80052f4 <HAL_ADC_Start+0x120>
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
80052e4: 687b ldr r3, [r7, #4]
|
|
80052e6: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80052e8: f423 5340 bic.w r3, r3, #12288 ; 0x3000
|
|
80052ec: f443 5280 orr.w r2, r3, #4096 ; 0x1000
|
|
80052f0: 687b ldr r3, [r7, #4]
|
|
80052f2: 655a str r2, [r3, #84] ; 0x54
|
|
}
|
|
|
|
/* Start ADC group regular conversion */
|
|
LL_ADC_REG_StartConversion(hadc->Instance);
|
|
80052f4: 687b ldr r3, [r7, #4]
|
|
80052f6: 681b ldr r3, [r3, #0]
|
|
80052f8: 4618 mov r0, r3
|
|
80052fa: f7ff fdad bl 8004e58 <LL_ADC_REG_StartConversion>
|
|
80052fe: e02a b.n 8005356 <HAL_ADC_Start+0x182>
|
|
}
|
|
else
|
|
{
|
|
/* ADC instance is a multimode slave instance with multimode regular conversions enabled */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
8005300: 687b ldr r3, [r7, #4]
|
|
8005302: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005304: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
|
|
8005308: 687b ldr r3, [r7, #4]
|
|
800530a: 655a str r2, [r3, #84] ; 0x54
|
|
/* if Master ADC JAUTO bit is set, update Slave State in setting
|
|
HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
|
|
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
|
|
800530c: 687b ldr r3, [r7, #4]
|
|
800530e: 681a ldr r2, [r3, #0]
|
|
8005310: f44f 7380 mov.w r3, #256 ; 0x100
|
|
8005314: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005318: 429a cmp r2, r3
|
|
800531a: d002 beq.n 8005322 <HAL_ADC_Start+0x14e>
|
|
800531c: 687b ldr r3, [r7, #4]
|
|
800531e: 681b ldr r3, [r3, #0]
|
|
8005320: e002 b.n 8005328 <HAL_ADC_Start+0x154>
|
|
8005322: 2300 movs r3, #0
|
|
8005324: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005328: 60fb str r3, [r7, #12]
|
|
if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
|
|
800532a: 68fb ldr r3, [r7, #12]
|
|
800532c: 68db ldr r3, [r3, #12]
|
|
800532e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8005332: 2b00 cmp r3, #0
|
|
8005334: d00f beq.n 8005356 <HAL_ADC_Start+0x182>
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
8005336: 687b ldr r3, [r7, #4]
|
|
8005338: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800533a: f423 5340 bic.w r3, r3, #12288 ; 0x3000
|
|
800533e: f443 5280 orr.w r2, r3, #4096 ; 0x1000
|
|
8005342: 687b ldr r3, [r7, #4]
|
|
8005344: 655a str r2, [r3, #84] ; 0x54
|
|
8005346: e006 b.n 8005356 <HAL_ADC_Start+0x182>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8005348: 687b ldr r3, [r7, #4]
|
|
800534a: 2200 movs r2, #0
|
|
800534c: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
8005350: e001 b.n 8005356 <HAL_ADC_Start+0x182>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_BUSY;
|
|
8005352: 2302 movs r3, #2
|
|
8005354: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8005356: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8005358: 4618 mov r0, r3
|
|
800535a: 3718 adds r7, #24
|
|
800535c: 46bd mov sp, r7
|
|
800535e: bd80 pop {r7, pc}
|
|
|
|
08005360 <HAL_ADC_Stop>:
|
|
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8005360: b580 push {r7, lr}
|
|
8005362: b084 sub sp, #16
|
|
8005364: af00 add r7, sp, #0
|
|
8005366: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8005368: 687b ldr r3, [r7, #4]
|
|
800536a: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
|
|
800536e: 2b01 cmp r3, #1
|
|
8005370: d101 bne.n 8005376 <HAL_ADC_Stop+0x16>
|
|
8005372: 2302 movs r3, #2
|
|
8005374: e023 b.n 80053be <HAL_ADC_Stop+0x5e>
|
|
8005376: 687b ldr r3, [r7, #4]
|
|
8005378: 2201 movs r2, #1
|
|
800537a: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* 1. Stop potential conversion on going, on ADC groups regular and injected */
|
|
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
|
|
800537e: 2103 movs r1, #3
|
|
8005380: 6878 ldr r0, [r7, #4]
|
|
8005382: f000 fd13 bl 8005dac <ADC_ConversionStop>
|
|
8005386: 4603 mov r3, r0
|
|
8005388: 73fb strb r3, [r7, #15]
|
|
|
|
/* Disable ADC peripheral if conversions are effectively stopped */
|
|
if (tmp_hal_status == HAL_OK)
|
|
800538a: 7bfb ldrb r3, [r7, #15]
|
|
800538c: 2b00 cmp r3, #0
|
|
800538e: d111 bne.n 80053b4 <HAL_ADC_Stop+0x54>
|
|
{
|
|
/* 2. Disable the ADC peripheral */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
8005390: 6878 ldr r0, [r7, #4]
|
|
8005392: f000 fe28 bl 8005fe6 <ADC_Disable>
|
|
8005396: 4603 mov r3, r0
|
|
8005398: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
800539a: 7bfb ldrb r3, [r7, #15]
|
|
800539c: 2b00 cmp r3, #0
|
|
800539e: d109 bne.n 80053b4 <HAL_ADC_Stop+0x54>
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80053a0: 687b ldr r3, [r7, #4]
|
|
80053a2: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80053a4: f423 5388 bic.w r3, r3, #4352 ; 0x1100
|
|
80053a8: f023 0301 bic.w r3, r3, #1
|
|
80053ac: f043 0201 orr.w r2, r3, #1
|
|
80053b0: 687b ldr r3, [r7, #4]
|
|
80053b2: 655a str r2, [r3, #84] ; 0x54
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80053b4: 687b ldr r3, [r7, #4]
|
|
80053b6: 2200 movs r2, #0
|
|
80053b8: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
80053bc: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80053be: 4618 mov r0, r3
|
|
80053c0: 3710 adds r7, #16
|
|
80053c2: 46bd mov sp, r7
|
|
80053c4: bd80 pop {r7, pc}
|
|
|
|
080053c6 <HAL_ADC_PollForConversion>:
|
|
* @param hadc ADC handle
|
|
* @param Timeout Timeout value in millisecond.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
|
|
{
|
|
80053c6: b580 push {r7, lr}
|
|
80053c8: b088 sub sp, #32
|
|
80053ca: af00 add r7, sp, #0
|
|
80053cc: 6078 str r0, [r7, #4]
|
|
80053ce: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
uint32_t tmp_Flag_End;
|
|
uint32_t tmp_cfgr;
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
const ADC_TypeDef *tmpADC_Master;
|
|
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
80053d0: f44f 7040 mov.w r0, #768 ; 0x300
|
|
80053d4: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
80053d8: f7ff fc86 bl 8004ce8 <LL_ADC_GetMultimode>
|
|
80053dc: 6178 str r0, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* If end of conversion selected to end of sequence conversions */
|
|
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
|
|
80053de: 687b ldr r3, [r7, #4]
|
|
80053e0: 695b ldr r3, [r3, #20]
|
|
80053e2: 2b08 cmp r3, #8
|
|
80053e4: d102 bne.n 80053ec <HAL_ADC_PollForConversion+0x26>
|
|
{
|
|
tmp_Flag_End = ADC_FLAG_EOS;
|
|
80053e6: 2308 movs r3, #8
|
|
80053e8: 61fb str r3, [r7, #28]
|
|
80053ea: e02d b.n 8005448 <HAL_ADC_PollForConversion+0x82>
|
|
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
|
|
/* several ranks and polling for end of each conversion. */
|
|
/* For code simplicity sake, this particular case is generalized to */
|
|
/* ADC configured in DMA mode and and polling for end of each conversion. */
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
80053ec: 697b ldr r3, [r7, #20]
|
|
80053ee: 2b00 cmp r3, #0
|
|
80053f0: d005 beq.n 80053fe <HAL_ADC_PollForConversion+0x38>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|
|
80053f2: 697b ldr r3, [r7, #20]
|
|
80053f4: 2b05 cmp r3, #5
|
|
80053f6: d002 beq.n 80053fe <HAL_ADC_PollForConversion+0x38>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
|
|
80053f8: 697b ldr r3, [r7, #20]
|
|
80053fa: 2b09 cmp r3, #9
|
|
80053fc: d111 bne.n 8005422 <HAL_ADC_PollForConversion+0x5c>
|
|
)
|
|
{
|
|
/* Check ADC DMA mode in independent mode on ADC group regular */
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
|
|
80053fe: 687b ldr r3, [r7, #4]
|
|
8005400: 681b ldr r3, [r3, #0]
|
|
8005402: 68db ldr r3, [r3, #12]
|
|
8005404: f003 0301 and.w r3, r3, #1
|
|
8005408: 2b00 cmp r3, #0
|
|
800540a: d007 beq.n 800541c <HAL_ADC_PollForConversion+0x56>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
800540c: 687b ldr r3, [r7, #4]
|
|
800540e: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005410: f043 0220 orr.w r2, r3, #32
|
|
8005414: 687b ldr r3, [r7, #4]
|
|
8005416: 655a str r2, [r3, #84] ; 0x54
|
|
return HAL_ERROR;
|
|
8005418: 2301 movs r3, #1
|
|
800541a: e0b1 b.n 8005580 <HAL_ADC_PollForConversion+0x1ba>
|
|
}
|
|
else
|
|
{
|
|
tmp_Flag_End = (ADC_FLAG_EOC);
|
|
800541c: 2304 movs r3, #4
|
|
800541e: 61fb str r3, [r7, #28]
|
|
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
|
|
8005420: e012 b.n 8005448 <HAL_ADC_PollForConversion+0x82>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check ADC DMA mode in multimode on ADC group regular */
|
|
if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
|
|
8005422: f44f 7040 mov.w r0, #768 ; 0x300
|
|
8005426: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
800542a: f7ff fc6b bl 8004d04 <LL_ADC_GetMultiDMATransfer>
|
|
800542e: 4603 mov r3, r0
|
|
8005430: 2b00 cmp r3, #0
|
|
8005432: d007 beq.n 8005444 <HAL_ADC_PollForConversion+0x7e>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8005434: 687b ldr r3, [r7, #4]
|
|
8005436: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005438: f043 0220 orr.w r2, r3, #32
|
|
800543c: 687b ldr r3, [r7, #4]
|
|
800543e: 655a str r2, [r3, #84] ; 0x54
|
|
return HAL_ERROR;
|
|
8005440: 2301 movs r3, #1
|
|
8005442: e09d b.n 8005580 <HAL_ADC_PollForConversion+0x1ba>
|
|
}
|
|
else
|
|
{
|
|
tmp_Flag_End = (ADC_FLAG_EOC);
|
|
8005444: 2304 movs r3, #4
|
|
8005446: 61fb str r3, [r7, #28]
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* Get tick count */
|
|
tickstart = HAL_GetTick();
|
|
8005448: f7ff fadf bl 8004a0a <HAL_GetTick>
|
|
800544c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait until End of unitary conversion or sequence conversions flag is raised */
|
|
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
800544e: e021 b.n 8005494 <HAL_ADC_PollForConversion+0xce>
|
|
{
|
|
/* Check if timeout is disabled (set to infinite wait) */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8005450: 683b ldr r3, [r7, #0]
|
|
8005452: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
|
|
8005456: d01d beq.n 8005494 <HAL_ADC_PollForConversion+0xce>
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
|
|
8005458: f7ff fad7 bl 8004a0a <HAL_GetTick>
|
|
800545c: 4602 mov r2, r0
|
|
800545e: 693b ldr r3, [r7, #16]
|
|
8005460: 1ad3 subs r3, r2, r3
|
|
8005462: 683a ldr r2, [r7, #0]
|
|
8005464: 429a cmp r2, r3
|
|
8005466: d302 bcc.n 800546e <HAL_ADC_PollForConversion+0xa8>
|
|
8005468: 683b ldr r3, [r7, #0]
|
|
800546a: 2b00 cmp r3, #0
|
|
800546c: d112 bne.n 8005494 <HAL_ADC_PollForConversion+0xce>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
800546e: 687b ldr r3, [r7, #4]
|
|
8005470: 681b ldr r3, [r3, #0]
|
|
8005472: 681a ldr r2, [r3, #0]
|
|
8005474: 69fb ldr r3, [r7, #28]
|
|
8005476: 4013 ands r3, r2
|
|
8005478: 2b00 cmp r3, #0
|
|
800547a: d10b bne.n 8005494 <HAL_ADC_PollForConversion+0xce>
|
|
{
|
|
/* Update ADC state machine to timeout */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
|
800547c: 687b ldr r3, [r7, #4]
|
|
800547e: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005480: f043 0204 orr.w r2, r3, #4
|
|
8005484: 687b ldr r3, [r7, #4]
|
|
8005486: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8005488: 687b ldr r3, [r7, #4]
|
|
800548a: 2200 movs r2, #0
|
|
800548c: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
return HAL_TIMEOUT;
|
|
8005490: 2303 movs r3, #3
|
|
8005492: e075 b.n 8005580 <HAL_ADC_PollForConversion+0x1ba>
|
|
while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
|
|
8005494: 687b ldr r3, [r7, #4]
|
|
8005496: 681b ldr r3, [r3, #0]
|
|
8005498: 681a ldr r2, [r3, #0]
|
|
800549a: 69fb ldr r3, [r7, #28]
|
|
800549c: 4013 ands r3, r2
|
|
800549e: 2b00 cmp r3, #0
|
|
80054a0: d0d6 beq.n 8005450 <HAL_ADC_PollForConversion+0x8a>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update ADC state machine */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
|
|
80054a2: 687b ldr r3, [r7, #4]
|
|
80054a4: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80054a6: f443 7200 orr.w r2, r3, #512 ; 0x200
|
|
80054aa: 687b ldr r3, [r7, #4]
|
|
80054ac: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Determine whether any further conversion upcoming on group regular */
|
|
/* by external trigger, continuous mode or scan sequence on going. */
|
|
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
|
|
80054ae: 687b ldr r3, [r7, #4]
|
|
80054b0: 681b ldr r3, [r3, #0]
|
|
80054b2: 4618 mov r0, r3
|
|
80054b4: f7ff fb89 bl 8004bca <LL_ADC_REG_IsTriggerSourceSWStart>
|
|
80054b8: 4603 mov r3, r0
|
|
80054ba: 2b00 cmp r3, #0
|
|
80054bc: d01c beq.n 80054f8 <HAL_ADC_PollForConversion+0x132>
|
|
&& (hadc->Init.ContinuousConvMode == DISABLE)
|
|
80054be: 687b ldr r3, [r7, #4]
|
|
80054c0: 7e5b ldrb r3, [r3, #25]
|
|
80054c2: 2b00 cmp r3, #0
|
|
80054c4: d118 bne.n 80054f8 <HAL_ADC_PollForConversion+0x132>
|
|
)
|
|
{
|
|
/* Check whether end of sequence is reached */
|
|
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
|
|
80054c6: 687b ldr r3, [r7, #4]
|
|
80054c8: 681b ldr r3, [r3, #0]
|
|
80054ca: 681b ldr r3, [r3, #0]
|
|
80054cc: f003 0308 and.w r3, r3, #8
|
|
80054d0: 2b08 cmp r3, #8
|
|
80054d2: d111 bne.n 80054f8 <HAL_ADC_PollForConversion+0x132>
|
|
{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
80054d4: 687b ldr r3, [r7, #4]
|
|
80054d6: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80054d8: f423 7280 bic.w r2, r3, #256 ; 0x100
|
|
80054dc: 687b ldr r3, [r7, #4]
|
|
80054de: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
|
|
80054e0: 687b ldr r3, [r7, #4]
|
|
80054e2: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80054e4: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
|
80054e8: 2b00 cmp r3, #0
|
|
80054ea: d105 bne.n 80054f8 <HAL_ADC_PollForConversion+0x132>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
80054ec: 687b ldr r3, [r7, #4]
|
|
80054ee: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80054f0: f043 0201 orr.w r2, r3, #1
|
|
80054f4: 687b ldr r3, [r7, #4]
|
|
80054f6: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Get relevant register CFGR in ADC instance of ADC master or slave */
|
|
/* in function of multimode state (for devices with multimode */
|
|
/* available). */
|
|
#if defined(ADC_MULTIMODE_SUPPORT)
|
|
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
|
|
80054f8: 687b ldr r3, [r7, #4]
|
|
80054fa: 681a ldr r2, [r3, #0]
|
|
80054fc: f44f 7380 mov.w r3, #256 ; 0x100
|
|
8005500: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005504: 429a cmp r2, r3
|
|
8005506: d002 beq.n 800550e <HAL_ADC_PollForConversion+0x148>
|
|
8005508: 687b ldr r3, [r7, #4]
|
|
800550a: 681b ldr r3, [r3, #0]
|
|
800550c: e002 b.n 8005514 <HAL_ADC_PollForConversion+0x14e>
|
|
800550e: 2300 movs r3, #0
|
|
8005510: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005514: 687a ldr r2, [r7, #4]
|
|
8005516: 6812 ldr r2, [r2, #0]
|
|
8005518: 4293 cmp r3, r2
|
|
800551a: d008 beq.n 800552e <HAL_ADC_PollForConversion+0x168>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
|
|
800551c: 697b ldr r3, [r7, #20]
|
|
800551e: 2b00 cmp r3, #0
|
|
8005520: d005 beq.n 800552e <HAL_ADC_PollForConversion+0x168>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
|
|
8005522: 697b ldr r3, [r7, #20]
|
|
8005524: 2b05 cmp r3, #5
|
|
8005526: d002 beq.n 800552e <HAL_ADC_PollForConversion+0x168>
|
|
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
|
|
8005528: 697b ldr r3, [r7, #20]
|
|
800552a: 2b09 cmp r3, #9
|
|
800552c: d104 bne.n 8005538 <HAL_ADC_PollForConversion+0x172>
|
|
)
|
|
{
|
|
/* Retrieve handle ADC CFGR register */
|
|
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
|
800552e: 687b ldr r3, [r7, #4]
|
|
8005530: 681b ldr r3, [r3, #0]
|
|
8005532: 68db ldr r3, [r3, #12]
|
|
8005534: 61bb str r3, [r7, #24]
|
|
8005536: e011 b.n 800555c <HAL_ADC_PollForConversion+0x196>
|
|
}
|
|
else
|
|
{
|
|
/* Retrieve Master ADC CFGR register */
|
|
tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
|
|
8005538: 687b ldr r3, [r7, #4]
|
|
800553a: 681a ldr r2, [r3, #0]
|
|
800553c: f44f 7380 mov.w r3, #256 ; 0x100
|
|
8005540: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005544: 429a cmp r2, r3
|
|
8005546: d002 beq.n 800554e <HAL_ADC_PollForConversion+0x188>
|
|
8005548: 687b ldr r3, [r7, #4]
|
|
800554a: 681b ldr r3, [r3, #0]
|
|
800554c: e002 b.n 8005554 <HAL_ADC_PollForConversion+0x18e>
|
|
800554e: 2300 movs r3, #0
|
|
8005550: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005554: 60fb str r3, [r7, #12]
|
|
tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
|
|
8005556: 68fb ldr r3, [r7, #12]
|
|
8005558: 68db ldr r3, [r3, #12]
|
|
800555a: 61bb str r3, [r7, #24]
|
|
/* Retrieve handle ADC CFGR register */
|
|
tmp_cfgr = READ_REG(hadc->Instance->CFGR);
|
|
#endif
|
|
|
|
/* Clear polled flag */
|
|
if (tmp_Flag_End == ADC_FLAG_EOS)
|
|
800555c: 69fb ldr r3, [r7, #28]
|
|
800555e: 2b08 cmp r3, #8
|
|
8005560: d104 bne.n 800556c <HAL_ADC_PollForConversion+0x1a6>
|
|
{
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
|
|
8005562: 687b ldr r3, [r7, #4]
|
|
8005564: 681b ldr r3, [r3, #0]
|
|
8005566: 2208 movs r2, #8
|
|
8005568: 601a str r2, [r3, #0]
|
|
800556a: e008 b.n 800557e <HAL_ADC_PollForConversion+0x1b8>
|
|
else
|
|
{
|
|
/* Clear end of conversion EOC flag of regular group if low power feature */
|
|
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
|
|
/* until data register is read using function HAL_ADC_GetValue(). */
|
|
if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
|
|
800556c: 69bb ldr r3, [r7, #24]
|
|
800556e: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
8005572: 2b00 cmp r3, #0
|
|
8005574: d103 bne.n 800557e <HAL_ADC_PollForConversion+0x1b8>
|
|
{
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
|
|
8005576: 687b ldr r3, [r7, #4]
|
|
8005578: 681b ldr r3, [r3, #0]
|
|
800557a: 220c movs r2, #12
|
|
800557c: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800557e: 2300 movs r3, #0
|
|
}
|
|
8005580: 4618 mov r0, r3
|
|
8005582: 3720 adds r7, #32
|
|
8005584: 46bd mov sp, r7
|
|
8005586: bd80 pop {r7, pc}
|
|
|
|
08005588 <HAL_ADC_GetValue>:
|
|
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
|
|
* @param hadc ADC handle
|
|
* @retval ADC group regular conversion data
|
|
*/
|
|
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8005588: b480 push {r7}
|
|
800558a: b083 sub sp, #12
|
|
800558c: af00 add r7, sp, #0
|
|
800558e: 6078 str r0, [r7, #4]
|
|
|
|
/* Note: EOC flag is not cleared here by software because automatically */
|
|
/* cleared by hardware when reading register DR. */
|
|
|
|
/* Return ADC converted value */
|
|
return hadc->Instance->DR;
|
|
8005590: 687b ldr r3, [r7, #4]
|
|
8005592: 681b ldr r3, [r3, #0]
|
|
8005594: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
}
|
|
8005596: 4618 mov r0, r3
|
|
8005598: 370c adds r7, #12
|
|
800559a: 46bd mov sp, r7
|
|
800559c: f85d 7b04 ldr.w r7, [sp], #4
|
|
80055a0: 4770 bx lr
|
|
...
|
|
|
|
080055a4 <HAL_ADC_ConfigChannel>:
|
|
* @param hadc ADC handle
|
|
* @param sConfig Structure of ADC channel assigned to ADC group regular.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
|
|
{
|
|
80055a4: b580 push {r7, lr}
|
|
80055a6: b0b6 sub sp, #216 ; 0xd8
|
|
80055a8: af00 add r7, sp, #0
|
|
80055aa: 6078 str r0, [r7, #4]
|
|
80055ac: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
80055ae: 2300 movs r3, #0
|
|
80055b0: f887 30d7 strb.w r3, [r7, #215] ; 0xd7
|
|
uint32_t tmpOffsetShifted;
|
|
uint32_t tmp_config_internal_channel;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
80055b4: 2300 movs r3, #0
|
|
80055b6: 60fb str r3, [r7, #12]
|
|
{
|
|
assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
80055b8: 687b ldr r3, [r7, #4]
|
|
80055ba: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
|
|
80055be: 2b01 cmp r3, #1
|
|
80055c0: d101 bne.n 80055c6 <HAL_ADC_ConfigChannel+0x22>
|
|
80055c2: 2302 movs r3, #2
|
|
80055c4: e3ee b.n 8005da4 <HAL_ADC_ConfigChannel+0x800>
|
|
80055c6: 687b ldr r3, [r7, #4]
|
|
80055c8: 2201 movs r2, #1
|
|
80055ca: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel number */
|
|
/* - Channel rank */
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
80055ce: 687b ldr r3, [r7, #4]
|
|
80055d0: 681b ldr r3, [r3, #0]
|
|
80055d2: 4618 mov r0, r3
|
|
80055d4: f7ff fc68 bl 8004ea8 <LL_ADC_REG_IsConversionOngoing>
|
|
80055d8: 4603 mov r3, r0
|
|
80055da: 2b00 cmp r3, #0
|
|
80055dc: f040 83cf bne.w 8005d7e <HAL_ADC_ConfigChannel+0x7da>
|
|
/* Correspondence for compatibility with legacy definition of */
|
|
/* sequencer ranks in direct number format. This correspondence can */
|
|
/* be done only on ranks 1 to 5 due to literal values. */
|
|
/* Note: Sequencer ranks in direct number format are no more used */
|
|
/* and are detected by activating USE_FULL_ASSERT feature. */
|
|
if (sConfig->Rank <= 5U)
|
|
80055e0: 683b ldr r3, [r7, #0]
|
|
80055e2: 685b ldr r3, [r3, #4]
|
|
80055e4: 2b05 cmp r3, #5
|
|
80055e6: d824 bhi.n 8005632 <HAL_ADC_ConfigChannel+0x8e>
|
|
{
|
|
switch (sConfig->Rank)
|
|
80055e8: 683b ldr r3, [r7, #0]
|
|
80055ea: 685b ldr r3, [r3, #4]
|
|
80055ec: 3b02 subs r3, #2
|
|
80055ee: 2b03 cmp r3, #3
|
|
80055f0: d81b bhi.n 800562a <HAL_ADC_ConfigChannel+0x86>
|
|
80055f2: a201 add r2, pc, #4 ; (adr r2, 80055f8 <HAL_ADC_ConfigChannel+0x54>)
|
|
80055f4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80055f8: 08005609 .word 0x08005609
|
|
80055fc: 08005611 .word 0x08005611
|
|
8005600: 08005619 .word 0x08005619
|
|
8005604: 08005621 .word 0x08005621
|
|
{
|
|
case 2U:
|
|
sConfig->Rank = ADC_REGULAR_RANK_2;
|
|
8005608: 683b ldr r3, [r7, #0]
|
|
800560a: 220c movs r2, #12
|
|
800560c: 605a str r2, [r3, #4]
|
|
break;
|
|
800560e: e011 b.n 8005634 <HAL_ADC_ConfigChannel+0x90>
|
|
case 3U:
|
|
sConfig->Rank = ADC_REGULAR_RANK_3;
|
|
8005610: 683b ldr r3, [r7, #0]
|
|
8005612: 2212 movs r2, #18
|
|
8005614: 605a str r2, [r3, #4]
|
|
break;
|
|
8005616: e00d b.n 8005634 <HAL_ADC_ConfigChannel+0x90>
|
|
case 4U:
|
|
sConfig->Rank = ADC_REGULAR_RANK_4;
|
|
8005618: 683b ldr r3, [r7, #0]
|
|
800561a: 2218 movs r2, #24
|
|
800561c: 605a str r2, [r3, #4]
|
|
break;
|
|
800561e: e009 b.n 8005634 <HAL_ADC_ConfigChannel+0x90>
|
|
case 5U:
|
|
sConfig->Rank = ADC_REGULAR_RANK_5;
|
|
8005620: 683b ldr r3, [r7, #0]
|
|
8005622: f44f 7280 mov.w r2, #256 ; 0x100
|
|
8005626: 605a str r2, [r3, #4]
|
|
break;
|
|
8005628: e004 b.n 8005634 <HAL_ADC_ConfigChannel+0x90>
|
|
/* case 1U */
|
|
default:
|
|
sConfig->Rank = ADC_REGULAR_RANK_1;
|
|
800562a: 683b ldr r3, [r7, #0]
|
|
800562c: 2206 movs r2, #6
|
|
800562e: 605a str r2, [r3, #4]
|
|
break;
|
|
8005630: e000 b.n 8005634 <HAL_ADC_ConfigChannel+0x90>
|
|
}
|
|
}
|
|
8005632: bf00 nop
|
|
#endif
|
|
|
|
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
|
|
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
|
|
8005634: 687b ldr r3, [r7, #4]
|
|
8005636: 6818 ldr r0, [r3, #0]
|
|
8005638: 683b ldr r3, [r7, #0]
|
|
800563a: 6859 ldr r1, [r3, #4]
|
|
800563c: 683b ldr r3, [r7, #0]
|
|
800563e: 681b ldr r3, [r3, #0]
|
|
8005640: 461a mov r2, r3
|
|
8005642: f7ff fad5 bl 8004bf0 <LL_ADC_REG_SetSequencerRanks>
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel sampling time */
|
|
/* - Channel offset */
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
8005646: 687b ldr r3, [r7, #4]
|
|
8005648: 681b ldr r3, [r3, #0]
|
|
800564a: 4618 mov r0, r3
|
|
800564c: f7ff fc2c bl 8004ea8 <LL_ADC_REG_IsConversionOngoing>
|
|
8005650: f8c7 00d0 str.w r0, [r7, #208] ; 0xd0
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
8005654: 687b ldr r3, [r7, #4]
|
|
8005656: 681b ldr r3, [r3, #0]
|
|
8005658: 4618 mov r0, r3
|
|
800565a: f7ff fc4c bl 8004ef6 <LL_ADC_INJ_IsConversionOngoing>
|
|
800565e: f8c7 00cc str.w r0, [r7, #204] ; 0xcc
|
|
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
|
|
8005662: f8d7 30d0 ldr.w r3, [r7, #208] ; 0xd0
|
|
8005666: 2b00 cmp r3, #0
|
|
8005668: f040 81a6 bne.w 80059b8 <HAL_ADC_ConfigChannel+0x414>
|
|
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
|
|
800566c: f8d7 30cc ldr.w r3, [r7, #204] ; 0xcc
|
|
8005670: 2b00 cmp r3, #0
|
|
8005672: f040 81a1 bne.w 80059b8 <HAL_ADC_ConfigChannel+0x414>
|
|
/* Set ADC sampling time common configuration */
|
|
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
|
|
}
|
|
#else
|
|
/* Set sampling time of the selected ADC channel */
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
|
|
8005676: 687b ldr r3, [r7, #4]
|
|
8005678: 6818 ldr r0, [r3, #0]
|
|
800567a: 683b ldr r3, [r7, #0]
|
|
800567c: 6819 ldr r1, [r3, #0]
|
|
800567e: 683b ldr r3, [r7, #0]
|
|
8005680: 689b ldr r3, [r3, #8]
|
|
8005682: 461a mov r2, r3
|
|
8005684: f7ff fae0 bl 8004c48 <LL_ADC_SetChannelSamplingTime>
|
|
|
|
/* Configure the offset: offset enable/disable, channel, offset value */
|
|
|
|
/* Shift the offset with respect to the selected ADC resolution. */
|
|
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
|
|
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
|
|
8005688: 683b ldr r3, [r7, #0]
|
|
800568a: 695a ldr r2, [r3, #20]
|
|
800568c: 687b ldr r3, [r7, #4]
|
|
800568e: 681b ldr r3, [r3, #0]
|
|
8005690: 68db ldr r3, [r3, #12]
|
|
8005692: 08db lsrs r3, r3, #3
|
|
8005694: f003 0303 and.w r3, r3, #3
|
|
8005698: 005b lsls r3, r3, #1
|
|
800569a: fa02 f303 lsl.w r3, r2, r3
|
|
800569e: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
|
|
|
|
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
|
|
80056a2: 683b ldr r3, [r7, #0]
|
|
80056a4: 691b ldr r3, [r3, #16]
|
|
80056a6: 2b04 cmp r3, #4
|
|
80056a8: d00a beq.n 80056c0 <HAL_ADC_ConfigChannel+0x11c>
|
|
{
|
|
/* Set ADC selected offset number */
|
|
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
|
|
80056aa: 687b ldr r3, [r7, #4]
|
|
80056ac: 6818 ldr r0, [r3, #0]
|
|
80056ae: 683b ldr r3, [r7, #0]
|
|
80056b0: 6919 ldr r1, [r3, #16]
|
|
80056b2: 683b ldr r3, [r7, #0]
|
|
80056b4: 681a ldr r2, [r3, #0]
|
|
80056b6: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8
|
|
80056ba: f7ff fa30 bl 8004b1e <LL_ADC_SetOffset>
|
|
80056be: e17b b.n 80059b8 <HAL_ADC_ConfigChannel+0x414>
|
|
}
|
|
else
|
|
{
|
|
/* Scan each offset register to check if the selected channel is targeted. */
|
|
/* If this is the case, the corresponding offset number is disabled. */
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
|
|
80056c0: 687b ldr r3, [r7, #4]
|
|
80056c2: 681b ldr r3, [r3, #0]
|
|
80056c4: 2100 movs r1, #0
|
|
80056c6: 4618 mov r0, r3
|
|
80056c8: f7ff fa4e bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
80056cc: 4603 mov r3, r0
|
|
80056ce: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80056d2: 2b00 cmp r3, #0
|
|
80056d4: d10a bne.n 80056ec <HAL_ADC_ConfigChannel+0x148>
|
|
80056d6: 687b ldr r3, [r7, #4]
|
|
80056d8: 681b ldr r3, [r3, #0]
|
|
80056da: 2100 movs r1, #0
|
|
80056dc: 4618 mov r0, r3
|
|
80056de: f7ff fa43 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
80056e2: 4603 mov r3, r0
|
|
80056e4: 0e9b lsrs r3, r3, #26
|
|
80056e6: f003 021f and.w r2, r3, #31
|
|
80056ea: e01e b.n 800572a <HAL_ADC_ConfigChannel+0x186>
|
|
80056ec: 687b ldr r3, [r7, #4]
|
|
80056ee: 681b ldr r3, [r3, #0]
|
|
80056f0: 2100 movs r1, #0
|
|
80056f2: 4618 mov r0, r3
|
|
80056f4: f7ff fa38 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
80056f8: 4603 mov r3, r0
|
|
80056fa: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
uint32_t result;
|
|
|
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
|
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
|
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80056fe: f8d7 30bc ldr.w r3, [r7, #188] ; 0xbc
|
|
8005702: fa93 f3a3 rbit r3, r3
|
|
8005706: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
|
|
result |= value & 1U;
|
|
s--;
|
|
}
|
|
result <<= s; /* shift when v's highest bits are zero */
|
|
#endif
|
|
return result;
|
|
800570a: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8
|
|
800570e: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
|
|
optimisations using the logic "value was passed to __builtin_clz, so it
|
|
is non-zero".
|
|
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
|
|
single CLZ instruction.
|
|
*/
|
|
if (value == 0U)
|
|
8005712: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0
|
|
8005716: 2b00 cmp r3, #0
|
|
8005718: d101 bne.n 800571e <HAL_ADC_ConfigChannel+0x17a>
|
|
{
|
|
return 32U;
|
|
800571a: 2320 movs r3, #32
|
|
800571c: e004 b.n 8005728 <HAL_ADC_ConfigChannel+0x184>
|
|
}
|
|
return __builtin_clz(value);
|
|
800571e: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0
|
|
8005722: fab3 f383 clz r3, r3
|
|
8005726: b2db uxtb r3, r3
|
|
8005728: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
|
800572a: 683b ldr r3, [r7, #0]
|
|
800572c: 681b ldr r3, [r3, #0]
|
|
800572e: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005732: 2b00 cmp r3, #0
|
|
8005734: d105 bne.n 8005742 <HAL_ADC_ConfigChannel+0x19e>
|
|
8005736: 683b ldr r3, [r7, #0]
|
|
8005738: 681b ldr r3, [r3, #0]
|
|
800573a: 0e9b lsrs r3, r3, #26
|
|
800573c: f003 031f and.w r3, r3, #31
|
|
8005740: e018 b.n 8005774 <HAL_ADC_ConfigChannel+0x1d0>
|
|
8005742: 683b ldr r3, [r7, #0]
|
|
8005744: 681b ldr r3, [r3, #0]
|
|
8005746: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800574a: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0
|
|
800574e: fa93 f3a3 rbit r3, r3
|
|
8005752: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
|
return result;
|
|
8005756: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
|
|
800575a: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
|
|
if (value == 0U)
|
|
800575e: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4
|
|
8005762: 2b00 cmp r3, #0
|
|
8005764: d101 bne.n 800576a <HAL_ADC_ConfigChannel+0x1c6>
|
|
return 32U;
|
|
8005766: 2320 movs r3, #32
|
|
8005768: e004 b.n 8005774 <HAL_ADC_ConfigChannel+0x1d0>
|
|
return __builtin_clz(value);
|
|
800576a: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4
|
|
800576e: fab3 f383 clz r3, r3
|
|
8005772: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
|
|
8005774: 429a cmp r2, r3
|
|
8005776: d106 bne.n 8005786 <HAL_ADC_ConfigChannel+0x1e2>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
|
|
8005778: 687b ldr r3, [r7, #4]
|
|
800577a: 681b ldr r3, [r3, #0]
|
|
800577c: 2200 movs r2, #0
|
|
800577e: 2100 movs r1, #0
|
|
8005780: 4618 mov r0, r3
|
|
8005782: f7ff fa07 bl 8004b94 <LL_ADC_SetOffsetState>
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
|
|
8005786: 687b ldr r3, [r7, #4]
|
|
8005788: 681b ldr r3, [r3, #0]
|
|
800578a: 2101 movs r1, #1
|
|
800578c: 4618 mov r0, r3
|
|
800578e: f7ff f9eb bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
8005792: 4603 mov r3, r0
|
|
8005794: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005798: 2b00 cmp r3, #0
|
|
800579a: d10a bne.n 80057b2 <HAL_ADC_ConfigChannel+0x20e>
|
|
800579c: 687b ldr r3, [r7, #4]
|
|
800579e: 681b ldr r3, [r3, #0]
|
|
80057a0: 2101 movs r1, #1
|
|
80057a2: 4618 mov r0, r3
|
|
80057a4: f7ff f9e0 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
80057a8: 4603 mov r3, r0
|
|
80057aa: 0e9b lsrs r3, r3, #26
|
|
80057ac: f003 021f and.w r2, r3, #31
|
|
80057b0: e01e b.n 80057f0 <HAL_ADC_ConfigChannel+0x24c>
|
|
80057b2: 687b ldr r3, [r7, #4]
|
|
80057b4: 681b ldr r3, [r3, #0]
|
|
80057b6: 2101 movs r1, #1
|
|
80057b8: 4618 mov r0, r3
|
|
80057ba: f7ff f9d5 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
80057be: 4603 mov r3, r0
|
|
80057c0: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80057c4: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
|
|
80057c8: fa93 f3a3 rbit r3, r3
|
|
80057cc: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
|
return result;
|
|
80057d0: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
|
|
80057d4: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
|
|
if (value == 0U)
|
|
80057d8: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
|
|
80057dc: 2b00 cmp r3, #0
|
|
80057de: d101 bne.n 80057e4 <HAL_ADC_ConfigChannel+0x240>
|
|
return 32U;
|
|
80057e0: 2320 movs r3, #32
|
|
80057e2: e004 b.n 80057ee <HAL_ADC_ConfigChannel+0x24a>
|
|
return __builtin_clz(value);
|
|
80057e4: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
|
|
80057e8: fab3 f383 clz r3, r3
|
|
80057ec: b2db uxtb r3, r3
|
|
80057ee: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
|
80057f0: 683b ldr r3, [r7, #0]
|
|
80057f2: 681b ldr r3, [r3, #0]
|
|
80057f4: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80057f8: 2b00 cmp r3, #0
|
|
80057fa: d105 bne.n 8005808 <HAL_ADC_ConfigChannel+0x264>
|
|
80057fc: 683b ldr r3, [r7, #0]
|
|
80057fe: 681b ldr r3, [r3, #0]
|
|
8005800: 0e9b lsrs r3, r3, #26
|
|
8005802: f003 031f and.w r3, r3, #31
|
|
8005806: e018 b.n 800583a <HAL_ADC_ConfigChannel+0x296>
|
|
8005808: 683b ldr r3, [r7, #0]
|
|
800580a: 681b ldr r3, [r3, #0]
|
|
800580c: f8c7 3098 str.w r3, [r7, #152] ; 0x98
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005810: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98
|
|
8005814: fa93 f3a3 rbit r3, r3
|
|
8005818: f8c7 3094 str.w r3, [r7, #148] ; 0x94
|
|
return result;
|
|
800581c: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94
|
|
8005820: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
|
if (value == 0U)
|
|
8005824: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
|
|
8005828: 2b00 cmp r3, #0
|
|
800582a: d101 bne.n 8005830 <HAL_ADC_ConfigChannel+0x28c>
|
|
return 32U;
|
|
800582c: 2320 movs r3, #32
|
|
800582e: e004 b.n 800583a <HAL_ADC_ConfigChannel+0x296>
|
|
return __builtin_clz(value);
|
|
8005830: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
|
|
8005834: fab3 f383 clz r3, r3
|
|
8005838: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
|
|
800583a: 429a cmp r2, r3
|
|
800583c: d106 bne.n 800584c <HAL_ADC_ConfigChannel+0x2a8>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
|
|
800583e: 687b ldr r3, [r7, #4]
|
|
8005840: 681b ldr r3, [r3, #0]
|
|
8005842: 2200 movs r2, #0
|
|
8005844: 2101 movs r1, #1
|
|
8005846: 4618 mov r0, r3
|
|
8005848: f7ff f9a4 bl 8004b94 <LL_ADC_SetOffsetState>
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
|
|
800584c: 687b ldr r3, [r7, #4]
|
|
800584e: 681b ldr r3, [r3, #0]
|
|
8005850: 2102 movs r1, #2
|
|
8005852: 4618 mov r0, r3
|
|
8005854: f7ff f988 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
8005858: 4603 mov r3, r0
|
|
800585a: f3c3 0312 ubfx r3, r3, #0, #19
|
|
800585e: 2b00 cmp r3, #0
|
|
8005860: d10a bne.n 8005878 <HAL_ADC_ConfigChannel+0x2d4>
|
|
8005862: 687b ldr r3, [r7, #4]
|
|
8005864: 681b ldr r3, [r3, #0]
|
|
8005866: 2102 movs r1, #2
|
|
8005868: 4618 mov r0, r3
|
|
800586a: f7ff f97d bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
800586e: 4603 mov r3, r0
|
|
8005870: 0e9b lsrs r3, r3, #26
|
|
8005872: f003 021f and.w r2, r3, #31
|
|
8005876: e01e b.n 80058b6 <HAL_ADC_ConfigChannel+0x312>
|
|
8005878: 687b ldr r3, [r7, #4]
|
|
800587a: 681b ldr r3, [r3, #0]
|
|
800587c: 2102 movs r1, #2
|
|
800587e: 4618 mov r0, r3
|
|
8005880: f7ff f972 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
8005884: 4603 mov r3, r0
|
|
8005886: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800588a: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
|
|
800588e: fa93 f3a3 rbit r3, r3
|
|
8005892: f8c7 3088 str.w r3, [r7, #136] ; 0x88
|
|
return result;
|
|
8005896: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
|
|
800589a: f8c7 3090 str.w r3, [r7, #144] ; 0x90
|
|
if (value == 0U)
|
|
800589e: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
|
|
80058a2: 2b00 cmp r3, #0
|
|
80058a4: d101 bne.n 80058aa <HAL_ADC_ConfigChannel+0x306>
|
|
return 32U;
|
|
80058a6: 2320 movs r3, #32
|
|
80058a8: e004 b.n 80058b4 <HAL_ADC_ConfigChannel+0x310>
|
|
return __builtin_clz(value);
|
|
80058aa: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
|
|
80058ae: fab3 f383 clz r3, r3
|
|
80058b2: b2db uxtb r3, r3
|
|
80058b4: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
|
80058b6: 683b ldr r3, [r7, #0]
|
|
80058b8: 681b ldr r3, [r3, #0]
|
|
80058ba: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80058be: 2b00 cmp r3, #0
|
|
80058c0: d105 bne.n 80058ce <HAL_ADC_ConfigChannel+0x32a>
|
|
80058c2: 683b ldr r3, [r7, #0]
|
|
80058c4: 681b ldr r3, [r3, #0]
|
|
80058c6: 0e9b lsrs r3, r3, #26
|
|
80058c8: f003 031f and.w r3, r3, #31
|
|
80058cc: e016 b.n 80058fc <HAL_ADC_ConfigChannel+0x358>
|
|
80058ce: 683b ldr r3, [r7, #0]
|
|
80058d0: 681b ldr r3, [r3, #0]
|
|
80058d2: f8c7 3080 str.w r3, [r7, #128] ; 0x80
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
80058d6: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80
|
|
80058da: fa93 f3a3 rbit r3, r3
|
|
80058de: 67fb str r3, [r7, #124] ; 0x7c
|
|
return result;
|
|
80058e0: 6ffb ldr r3, [r7, #124] ; 0x7c
|
|
80058e2: f8c7 3084 str.w r3, [r7, #132] ; 0x84
|
|
if (value == 0U)
|
|
80058e6: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
|
|
80058ea: 2b00 cmp r3, #0
|
|
80058ec: d101 bne.n 80058f2 <HAL_ADC_ConfigChannel+0x34e>
|
|
return 32U;
|
|
80058ee: 2320 movs r3, #32
|
|
80058f0: e004 b.n 80058fc <HAL_ADC_ConfigChannel+0x358>
|
|
return __builtin_clz(value);
|
|
80058f2: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
|
|
80058f6: fab3 f383 clz r3, r3
|
|
80058fa: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
|
|
80058fc: 429a cmp r2, r3
|
|
80058fe: d106 bne.n 800590e <HAL_ADC_ConfigChannel+0x36a>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
|
|
8005900: 687b ldr r3, [r7, #4]
|
|
8005902: 681b ldr r3, [r3, #0]
|
|
8005904: 2200 movs r2, #0
|
|
8005906: 2102 movs r1, #2
|
|
8005908: 4618 mov r0, r3
|
|
800590a: f7ff f943 bl 8004b94 <LL_ADC_SetOffsetState>
|
|
}
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
|
|
800590e: 687b ldr r3, [r7, #4]
|
|
8005910: 681b ldr r3, [r3, #0]
|
|
8005912: 2103 movs r1, #3
|
|
8005914: 4618 mov r0, r3
|
|
8005916: f7ff f927 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
800591a: 4603 mov r3, r0
|
|
800591c: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005920: 2b00 cmp r3, #0
|
|
8005922: d10a bne.n 800593a <HAL_ADC_ConfigChannel+0x396>
|
|
8005924: 687b ldr r3, [r7, #4]
|
|
8005926: 681b ldr r3, [r3, #0]
|
|
8005928: 2103 movs r1, #3
|
|
800592a: 4618 mov r0, r3
|
|
800592c: f7ff f91c bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
8005930: 4603 mov r3, r0
|
|
8005932: 0e9b lsrs r3, r3, #26
|
|
8005934: f003 021f and.w r2, r3, #31
|
|
8005938: e017 b.n 800596a <HAL_ADC_ConfigChannel+0x3c6>
|
|
800593a: 687b ldr r3, [r7, #4]
|
|
800593c: 681b ldr r3, [r3, #0]
|
|
800593e: 2103 movs r1, #3
|
|
8005940: 4618 mov r0, r3
|
|
8005942: f7ff f911 bl 8004b68 <LL_ADC_GetOffsetChannel>
|
|
8005946: 4603 mov r3, r0
|
|
8005948: 677b str r3, [r7, #116] ; 0x74
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
800594a: 6f7b ldr r3, [r7, #116] ; 0x74
|
|
800594c: fa93 f3a3 rbit r3, r3
|
|
8005950: 673b str r3, [r7, #112] ; 0x70
|
|
return result;
|
|
8005952: 6f3b ldr r3, [r7, #112] ; 0x70
|
|
8005954: 67bb str r3, [r7, #120] ; 0x78
|
|
if (value == 0U)
|
|
8005956: 6fbb ldr r3, [r7, #120] ; 0x78
|
|
8005958: 2b00 cmp r3, #0
|
|
800595a: d101 bne.n 8005960 <HAL_ADC_ConfigChannel+0x3bc>
|
|
return 32U;
|
|
800595c: 2320 movs r3, #32
|
|
800595e: e003 b.n 8005968 <HAL_ADC_ConfigChannel+0x3c4>
|
|
return __builtin_clz(value);
|
|
8005960: 6fbb ldr r3, [r7, #120] ; 0x78
|
|
8005962: fab3 f383 clz r3, r3
|
|
8005966: b2db uxtb r3, r3
|
|
8005968: 461a mov r2, r3
|
|
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
|
|
800596a: 683b ldr r3, [r7, #0]
|
|
800596c: 681b ldr r3, [r3, #0]
|
|
800596e: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005972: 2b00 cmp r3, #0
|
|
8005974: d105 bne.n 8005982 <HAL_ADC_ConfigChannel+0x3de>
|
|
8005976: 683b ldr r3, [r7, #0]
|
|
8005978: 681b ldr r3, [r3, #0]
|
|
800597a: 0e9b lsrs r3, r3, #26
|
|
800597c: f003 031f and.w r3, r3, #31
|
|
8005980: e011 b.n 80059a6 <HAL_ADC_ConfigChannel+0x402>
|
|
8005982: 683b ldr r3, [r7, #0]
|
|
8005984: 681b ldr r3, [r3, #0]
|
|
8005986: 66bb str r3, [r7, #104] ; 0x68
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005988: 6ebb ldr r3, [r7, #104] ; 0x68
|
|
800598a: fa93 f3a3 rbit r3, r3
|
|
800598e: 667b str r3, [r7, #100] ; 0x64
|
|
return result;
|
|
8005990: 6e7b ldr r3, [r7, #100] ; 0x64
|
|
8005992: 66fb str r3, [r7, #108] ; 0x6c
|
|
if (value == 0U)
|
|
8005994: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
8005996: 2b00 cmp r3, #0
|
|
8005998: d101 bne.n 800599e <HAL_ADC_ConfigChannel+0x3fa>
|
|
return 32U;
|
|
800599a: 2320 movs r3, #32
|
|
800599c: e003 b.n 80059a6 <HAL_ADC_ConfigChannel+0x402>
|
|
return __builtin_clz(value);
|
|
800599e: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
80059a0: fab3 f383 clz r3, r3
|
|
80059a4: b2db uxtb r3, r3
|
|
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
|
|
80059a6: 429a cmp r2, r3
|
|
80059a8: d106 bne.n 80059b8 <HAL_ADC_ConfigChannel+0x414>
|
|
{
|
|
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
|
|
80059aa: 687b ldr r3, [r7, #4]
|
|
80059ac: 681b ldr r3, [r3, #0]
|
|
80059ae: 2200 movs r2, #0
|
|
80059b0: 2103 movs r1, #3
|
|
80059b2: 4618 mov r0, r3
|
|
80059b4: f7ff f8ee bl 8004b94 <LL_ADC_SetOffsetState>
|
|
}
|
|
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Single or differential mode */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
80059b8: 687b ldr r3, [r7, #4]
|
|
80059ba: 681b ldr r3, [r3, #0]
|
|
80059bc: 4618 mov r0, r3
|
|
80059be: f7ff fa25 bl 8004e0c <LL_ADC_IsEnabled>
|
|
80059c2: 4603 mov r3, r0
|
|
80059c4: 2b00 cmp r3, #0
|
|
80059c6: f040 813f bne.w 8005c48 <HAL_ADC_ConfigChannel+0x6a4>
|
|
{
|
|
/* Set mode single-ended or differential input of the selected ADC channel */
|
|
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
|
|
80059ca: 687b ldr r3, [r7, #4]
|
|
80059cc: 6818 ldr r0, [r3, #0]
|
|
80059ce: 683b ldr r3, [r7, #0]
|
|
80059d0: 6819 ldr r1, [r3, #0]
|
|
80059d2: 683b ldr r3, [r7, #0]
|
|
80059d4: 68db ldr r3, [r3, #12]
|
|
80059d6: 461a mov r2, r3
|
|
80059d8: f7ff f961 bl 8004c9e <LL_ADC_SetChannelSingleDiff>
|
|
|
|
/* Configuration of differential mode */
|
|
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
|
|
80059dc: 683b ldr r3, [r7, #0]
|
|
80059de: 68da ldr r2, [r3, #12]
|
|
80059e0: 2300 movs r3, #0
|
|
80059e2: f2c4 037f movt r3, #16511 ; 0x407f
|
|
80059e6: 429a cmp r2, r3
|
|
80059e8: f040 812e bne.w 8005c48 <HAL_ADC_ConfigChannel+0x6a4>
|
|
{
|
|
/* Set sampling time of the selected ADC channel */
|
|
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
80059ec: 687b ldr r3, [r7, #4]
|
|
80059ee: 6818 ldr r0, [r3, #0]
|
|
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
|
|
80059f0: 683b ldr r3, [r7, #0]
|
|
80059f2: 681b ldr r3, [r3, #0]
|
|
80059f4: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80059f8: 2b00 cmp r3, #0
|
|
80059fa: d10b bne.n 8005a14 <HAL_ADC_ConfigChannel+0x470>
|
|
80059fc: 683b ldr r3, [r7, #0]
|
|
80059fe: 681b ldr r3, [r3, #0]
|
|
8005a00: 0e9b lsrs r3, r3, #26
|
|
8005a02: 3301 adds r3, #1
|
|
8005a04: f003 031f and.w r3, r3, #31
|
|
8005a08: 2b09 cmp r3, #9
|
|
8005a0a: bf94 ite ls
|
|
8005a0c: 2301 movls r3, #1
|
|
8005a0e: 2300 movhi r3, #0
|
|
8005a10: b2db uxtb r3, r3
|
|
8005a12: e019 b.n 8005a48 <HAL_ADC_ConfigChannel+0x4a4>
|
|
8005a14: 683b ldr r3, [r7, #0]
|
|
8005a16: 681b ldr r3, [r3, #0]
|
|
8005a18: 65fb str r3, [r7, #92] ; 0x5c
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005a1a: 6dfb ldr r3, [r7, #92] ; 0x5c
|
|
8005a1c: fa93 f3a3 rbit r3, r3
|
|
8005a20: 65bb str r3, [r7, #88] ; 0x58
|
|
return result;
|
|
8005a22: 6dbb ldr r3, [r7, #88] ; 0x58
|
|
8005a24: 663b str r3, [r7, #96] ; 0x60
|
|
if (value == 0U)
|
|
8005a26: 6e3b ldr r3, [r7, #96] ; 0x60
|
|
8005a28: 2b00 cmp r3, #0
|
|
8005a2a: d101 bne.n 8005a30 <HAL_ADC_ConfigChannel+0x48c>
|
|
return 32U;
|
|
8005a2c: 2320 movs r3, #32
|
|
8005a2e: e003 b.n 8005a38 <HAL_ADC_ConfigChannel+0x494>
|
|
return __builtin_clz(value);
|
|
8005a30: 6e3b ldr r3, [r7, #96] ; 0x60
|
|
8005a32: fab3 f383 clz r3, r3
|
|
8005a36: b2db uxtb r3, r3
|
|
8005a38: 3301 adds r3, #1
|
|
8005a3a: f003 031f and.w r3, r3, #31
|
|
8005a3e: 2b09 cmp r3, #9
|
|
8005a40: bf94 ite ls
|
|
8005a42: 2301 movls r3, #1
|
|
8005a44: 2300 movhi r3, #0
|
|
8005a46: b2db uxtb r3, r3
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
8005a48: 2b00 cmp r3, #0
|
|
8005a4a: d079 beq.n 8005b40 <HAL_ADC_ConfigChannel+0x59c>
|
|
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
|
|
8005a4c: 683b ldr r3, [r7, #0]
|
|
8005a4e: 681b ldr r3, [r3, #0]
|
|
8005a50: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005a54: 2b00 cmp r3, #0
|
|
8005a56: d107 bne.n 8005a68 <HAL_ADC_ConfigChannel+0x4c4>
|
|
8005a58: 683b ldr r3, [r7, #0]
|
|
8005a5a: 681b ldr r3, [r3, #0]
|
|
8005a5c: 0e9b lsrs r3, r3, #26
|
|
8005a5e: 3301 adds r3, #1
|
|
8005a60: 069b lsls r3, r3, #26
|
|
8005a62: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
|
|
8005a66: e015 b.n 8005a94 <HAL_ADC_ConfigChannel+0x4f0>
|
|
8005a68: 683b ldr r3, [r7, #0]
|
|
8005a6a: 681b ldr r3, [r3, #0]
|
|
8005a6c: 653b str r3, [r7, #80] ; 0x50
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005a6e: 6d3b ldr r3, [r7, #80] ; 0x50
|
|
8005a70: fa93 f3a3 rbit r3, r3
|
|
8005a74: 64fb str r3, [r7, #76] ; 0x4c
|
|
return result;
|
|
8005a76: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
8005a78: 657b str r3, [r7, #84] ; 0x54
|
|
if (value == 0U)
|
|
8005a7a: 6d7b ldr r3, [r7, #84] ; 0x54
|
|
8005a7c: 2b00 cmp r3, #0
|
|
8005a7e: d101 bne.n 8005a84 <HAL_ADC_ConfigChannel+0x4e0>
|
|
return 32U;
|
|
8005a80: 2320 movs r3, #32
|
|
8005a82: e003 b.n 8005a8c <HAL_ADC_ConfigChannel+0x4e8>
|
|
return __builtin_clz(value);
|
|
8005a84: 6d7b ldr r3, [r7, #84] ; 0x54
|
|
8005a86: fab3 f383 clz r3, r3
|
|
8005a8a: b2db uxtb r3, r3
|
|
8005a8c: 3301 adds r3, #1
|
|
8005a8e: 069b lsls r3, r3, #26
|
|
8005a90: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
|
|
8005a94: 683b ldr r3, [r7, #0]
|
|
8005a96: 681b ldr r3, [r3, #0]
|
|
8005a98: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005a9c: 2b00 cmp r3, #0
|
|
8005a9e: d109 bne.n 8005ab4 <HAL_ADC_ConfigChannel+0x510>
|
|
8005aa0: 683b ldr r3, [r7, #0]
|
|
8005aa2: 681b ldr r3, [r3, #0]
|
|
8005aa4: 0e9b lsrs r3, r3, #26
|
|
8005aa6: 3301 adds r3, #1
|
|
8005aa8: f003 031f and.w r3, r3, #31
|
|
8005aac: 2101 movs r1, #1
|
|
8005aae: fa01 f303 lsl.w r3, r1, r3
|
|
8005ab2: e017 b.n 8005ae4 <HAL_ADC_ConfigChannel+0x540>
|
|
8005ab4: 683b ldr r3, [r7, #0]
|
|
8005ab6: 681b ldr r3, [r3, #0]
|
|
8005ab8: 647b str r3, [r7, #68] ; 0x44
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005aba: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
8005abc: fa93 f3a3 rbit r3, r3
|
|
8005ac0: 643b str r3, [r7, #64] ; 0x40
|
|
return result;
|
|
8005ac2: 6c3b ldr r3, [r7, #64] ; 0x40
|
|
8005ac4: 64bb str r3, [r7, #72] ; 0x48
|
|
if (value == 0U)
|
|
8005ac6: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8005ac8: 2b00 cmp r3, #0
|
|
8005aca: d101 bne.n 8005ad0 <HAL_ADC_ConfigChannel+0x52c>
|
|
return 32U;
|
|
8005acc: 2320 movs r3, #32
|
|
8005ace: e003 b.n 8005ad8 <HAL_ADC_ConfigChannel+0x534>
|
|
return __builtin_clz(value);
|
|
8005ad0: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8005ad2: fab3 f383 clz r3, r3
|
|
8005ad6: b2db uxtb r3, r3
|
|
8005ad8: 3301 adds r3, #1
|
|
8005ada: f003 031f and.w r3, r3, #31
|
|
8005ade: 2101 movs r1, #1
|
|
8005ae0: fa01 f303 lsl.w r3, r1, r3
|
|
8005ae4: ea42 0103 orr.w r1, r2, r3
|
|
8005ae8: 683b ldr r3, [r7, #0]
|
|
8005aea: 681b ldr r3, [r3, #0]
|
|
8005aec: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005af0: 2b00 cmp r3, #0
|
|
8005af2: d10a bne.n 8005b0a <HAL_ADC_ConfigChannel+0x566>
|
|
8005af4: 683b ldr r3, [r7, #0]
|
|
8005af6: 681b ldr r3, [r3, #0]
|
|
8005af8: 0e9b lsrs r3, r3, #26
|
|
8005afa: 3301 adds r3, #1
|
|
8005afc: f003 021f and.w r2, r3, #31
|
|
8005b00: 4613 mov r3, r2
|
|
8005b02: 005b lsls r3, r3, #1
|
|
8005b04: 4413 add r3, r2
|
|
8005b06: 051b lsls r3, r3, #20
|
|
8005b08: e018 b.n 8005b3c <HAL_ADC_ConfigChannel+0x598>
|
|
8005b0a: 683b ldr r3, [r7, #0]
|
|
8005b0c: 681b ldr r3, [r3, #0]
|
|
8005b0e: 63bb str r3, [r7, #56] ; 0x38
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005b10: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
8005b12: fa93 f3a3 rbit r3, r3
|
|
8005b16: 637b str r3, [r7, #52] ; 0x34
|
|
return result;
|
|
8005b18: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
8005b1a: 63fb str r3, [r7, #60] ; 0x3c
|
|
if (value == 0U)
|
|
8005b1c: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8005b1e: 2b00 cmp r3, #0
|
|
8005b20: d101 bne.n 8005b26 <HAL_ADC_ConfigChannel+0x582>
|
|
return 32U;
|
|
8005b22: 2320 movs r3, #32
|
|
8005b24: e003 b.n 8005b2e <HAL_ADC_ConfigChannel+0x58a>
|
|
return __builtin_clz(value);
|
|
8005b26: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8005b28: fab3 f383 clz r3, r3
|
|
8005b2c: b2db uxtb r3, r3
|
|
8005b2e: 3301 adds r3, #1
|
|
8005b30: f003 021f and.w r2, r3, #31
|
|
8005b34: 4613 mov r3, r2
|
|
8005b36: 005b lsls r3, r3, #1
|
|
8005b38: 4413 add r3, r2
|
|
8005b3a: 051b lsls r3, r3, #20
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
8005b3c: 430b orrs r3, r1
|
|
8005b3e: e07e b.n 8005c3e <HAL_ADC_ConfigChannel+0x69a>
|
|
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
|
|
8005b40: 683b ldr r3, [r7, #0]
|
|
8005b42: 681b ldr r3, [r3, #0]
|
|
8005b44: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005b48: 2b00 cmp r3, #0
|
|
8005b4a: d107 bne.n 8005b5c <HAL_ADC_ConfigChannel+0x5b8>
|
|
8005b4c: 683b ldr r3, [r7, #0]
|
|
8005b4e: 681b ldr r3, [r3, #0]
|
|
8005b50: 0e9b lsrs r3, r3, #26
|
|
8005b52: 3301 adds r3, #1
|
|
8005b54: 069b lsls r3, r3, #26
|
|
8005b56: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
|
|
8005b5a: e015 b.n 8005b88 <HAL_ADC_ConfigChannel+0x5e4>
|
|
8005b5c: 683b ldr r3, [r7, #0]
|
|
8005b5e: 681b ldr r3, [r3, #0]
|
|
8005b60: 62fb str r3, [r7, #44] ; 0x2c
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005b62: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8005b64: fa93 f3a3 rbit r3, r3
|
|
8005b68: 62bb str r3, [r7, #40] ; 0x28
|
|
return result;
|
|
8005b6a: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8005b6c: 633b str r3, [r7, #48] ; 0x30
|
|
if (value == 0U)
|
|
8005b6e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8005b70: 2b00 cmp r3, #0
|
|
8005b72: d101 bne.n 8005b78 <HAL_ADC_ConfigChannel+0x5d4>
|
|
return 32U;
|
|
8005b74: 2320 movs r3, #32
|
|
8005b76: e003 b.n 8005b80 <HAL_ADC_ConfigChannel+0x5dc>
|
|
return __builtin_clz(value);
|
|
8005b78: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8005b7a: fab3 f383 clz r3, r3
|
|
8005b7e: b2db uxtb r3, r3
|
|
8005b80: 3301 adds r3, #1
|
|
8005b82: 069b lsls r3, r3, #26
|
|
8005b84: f003 42f8 and.w r2, r3, #2080374784 ; 0x7c000000
|
|
8005b88: 683b ldr r3, [r7, #0]
|
|
8005b8a: 681b ldr r3, [r3, #0]
|
|
8005b8c: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005b90: 2b00 cmp r3, #0
|
|
8005b92: d109 bne.n 8005ba8 <HAL_ADC_ConfigChannel+0x604>
|
|
8005b94: 683b ldr r3, [r7, #0]
|
|
8005b96: 681b ldr r3, [r3, #0]
|
|
8005b98: 0e9b lsrs r3, r3, #26
|
|
8005b9a: 3301 adds r3, #1
|
|
8005b9c: f003 031f and.w r3, r3, #31
|
|
8005ba0: 2101 movs r1, #1
|
|
8005ba2: fa01 f303 lsl.w r3, r1, r3
|
|
8005ba6: e017 b.n 8005bd8 <HAL_ADC_ConfigChannel+0x634>
|
|
8005ba8: 683b ldr r3, [r7, #0]
|
|
8005baa: 681b ldr r3, [r3, #0]
|
|
8005bac: 623b str r3, [r7, #32]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005bae: 6a3b ldr r3, [r7, #32]
|
|
8005bb0: fa93 f3a3 rbit r3, r3
|
|
8005bb4: 61fb str r3, [r7, #28]
|
|
return result;
|
|
8005bb6: 69fb ldr r3, [r7, #28]
|
|
8005bb8: 627b str r3, [r7, #36] ; 0x24
|
|
if (value == 0U)
|
|
8005bba: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8005bbc: 2b00 cmp r3, #0
|
|
8005bbe: d101 bne.n 8005bc4 <HAL_ADC_ConfigChannel+0x620>
|
|
return 32U;
|
|
8005bc0: 2320 movs r3, #32
|
|
8005bc2: e003 b.n 8005bcc <HAL_ADC_ConfigChannel+0x628>
|
|
return __builtin_clz(value);
|
|
8005bc4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8005bc6: fab3 f383 clz r3, r3
|
|
8005bca: b2db uxtb r3, r3
|
|
8005bcc: 3301 adds r3, #1
|
|
8005bce: f003 031f and.w r3, r3, #31
|
|
8005bd2: 2101 movs r1, #1
|
|
8005bd4: fa01 f303 lsl.w r3, r1, r3
|
|
8005bd8: ea42 0103 orr.w r1, r2, r3
|
|
8005bdc: 683b ldr r3, [r7, #0]
|
|
8005bde: 681b ldr r3, [r3, #0]
|
|
8005be0: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8005be4: 2b00 cmp r3, #0
|
|
8005be6: d10d bne.n 8005c04 <HAL_ADC_ConfigChannel+0x660>
|
|
8005be8: 683b ldr r3, [r7, #0]
|
|
8005bea: 681b ldr r3, [r3, #0]
|
|
8005bec: 0e9b lsrs r3, r3, #26
|
|
8005bee: 3301 adds r3, #1
|
|
8005bf0: f003 021f and.w r2, r3, #31
|
|
8005bf4: 4613 mov r3, r2
|
|
8005bf6: 005b lsls r3, r3, #1
|
|
8005bf8: 4413 add r3, r2
|
|
8005bfa: 3b1e subs r3, #30
|
|
8005bfc: 051b lsls r3, r3, #20
|
|
8005bfe: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
|
|
8005c02: e01b b.n 8005c3c <HAL_ADC_ConfigChannel+0x698>
|
|
8005c04: 683b ldr r3, [r7, #0]
|
|
8005c06: 681b ldr r3, [r3, #0]
|
|
8005c08: 617b str r3, [r7, #20]
|
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
|
8005c0a: 697b ldr r3, [r7, #20]
|
|
8005c0c: fa93 f3a3 rbit r3, r3
|
|
8005c10: 613b str r3, [r7, #16]
|
|
return result;
|
|
8005c12: 693b ldr r3, [r7, #16]
|
|
8005c14: 61bb str r3, [r7, #24]
|
|
if (value == 0U)
|
|
8005c16: 69bb ldr r3, [r7, #24]
|
|
8005c18: 2b00 cmp r3, #0
|
|
8005c1a: d101 bne.n 8005c20 <HAL_ADC_ConfigChannel+0x67c>
|
|
return 32U;
|
|
8005c1c: 2320 movs r3, #32
|
|
8005c1e: e003 b.n 8005c28 <HAL_ADC_ConfigChannel+0x684>
|
|
return __builtin_clz(value);
|
|
8005c20: 69bb ldr r3, [r7, #24]
|
|
8005c22: fab3 f383 clz r3, r3
|
|
8005c26: b2db uxtb r3, r3
|
|
8005c28: 3301 adds r3, #1
|
|
8005c2a: f003 021f and.w r2, r3, #31
|
|
8005c2e: 4613 mov r3, r2
|
|
8005c30: 005b lsls r3, r3, #1
|
|
8005c32: 4413 add r3, r2
|
|
8005c34: 3b1e subs r3, #30
|
|
8005c36: 051b lsls r3, r3, #20
|
|
8005c38: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
|
|
LL_ADC_SetChannelSamplingTime(hadc->Instance,
|
|
8005c3c: 430b orrs r3, r1
|
|
8005c3e: 683a ldr r2, [r7, #0]
|
|
8005c40: 6892 ldr r2, [r2, #8]
|
|
8005c42: 4619 mov r1, r3
|
|
8005c44: f7ff f800 bl 8004c48 <LL_ADC_SetChannelSamplingTime>
|
|
/* If internal channel selected, enable dedicated internal buffers and */
|
|
/* paths. */
|
|
/* Note: these internal measurement paths can be disabled using */
|
|
/* HAL_ADC_DeInit(). */
|
|
|
|
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
|
8005c48: 683b ldr r3, [r7, #0]
|
|
8005c4a: 681a ldr r2, [r3, #0]
|
|
8005c4c: 2300 movs r3, #0
|
|
8005c4e: f2c8 0308 movt r3, #32776 ; 0x8008
|
|
8005c52: 4013 ands r3, r2
|
|
8005c54: 2b00 cmp r3, #0
|
|
8005c56: f000 809f beq.w 8005d98 <HAL_ADC_ConfigChannel+0x7f4>
|
|
{
|
|
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
8005c5a: f44f 7040 mov.w r0, #768 ; 0x300
|
|
8005c5e: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8005c62: f7fe ff4e bl 8004b02 <LL_ADC_GetCommonPathInternalCh>
|
|
8005c66: f8c7 00c4 str.w r0, [r7, #196] ; 0xc4
|
|
|
|
/* If the requested internal measurement path has already been enabled, */
|
|
/* bypass the configuration processing. */
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
8005c6a: 683b ldr r3, [r7, #0]
|
|
8005c6c: 681a ldr r2, [r3, #0]
|
|
8005c6e: 2300 movs r3, #0
|
|
8005c70: f2cc 7352 movt r3, #51026 ; 0xc752
|
|
8005c74: 429a cmp r2, r3
|
|
8005c76: d13a bne.n 8005cee <HAL_ADC_ConfigChannel+0x74a>
|
|
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
|
|
8005c78: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
|
|
8005c7c: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
8005c80: 2b00 cmp r3, #0
|
|
8005c82: d134 bne.n 8005cee <HAL_ADC_ConfigChannel+0x74a>
|
|
{
|
|
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
|
8005c84: 687b ldr r3, [r7, #4]
|
|
8005c86: 681a ldr r2, [r3, #0]
|
|
8005c88: 2300 movs r3, #0
|
|
8005c8a: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005c8e: 429a cmp r2, r3
|
|
8005c90: d007 beq.n 8005ca2 <HAL_ADC_ConfigChannel+0x6fe>
|
|
8005c92: 687b ldr r3, [r7, #4]
|
|
8005c94: 681a ldr r2, [r3, #0]
|
|
8005c96: f44f 7300 mov.w r3, #512 ; 0x200
|
|
8005c9a: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005c9e: 429a cmp r2, r3
|
|
8005ca0: d177 bne.n 8005d92 <HAL_ADC_ConfigChannel+0x7ee>
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8005ca2: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
|
|
8005ca6: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
|
|
8005caa: 4619 mov r1, r3
|
|
8005cac: f44f 7040 mov.w r0, #768 ; 0x300
|
|
8005cb0: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8005cb4: f7fe ff12 bl 8004adc <LL_ADC_SetCommonPathInternalCh>
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Wait loop initialization and execution */
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles, scaling in us split to not */
|
|
/* exceed 32 bits register capacity and handle low frequency. */
|
|
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
|
|
8005cb8: f240 234c movw r3, #588 ; 0x24c
|
|
8005cbc: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8005cc0: 681b ldr r3, [r3, #0]
|
|
8005cc2: 099a lsrs r2, r3, #6
|
|
8005cc4: f642 5363 movw r3, #11619 ; 0x2d63
|
|
8005cc8: f2c0 533e movt r3, #1342 ; 0x53e
|
|
8005ccc: fba3 2302 umull r2, r3, r3, r2
|
|
8005cd0: 099b lsrs r3, r3, #6
|
|
8005cd2: 1c5a adds r2, r3, #1
|
|
8005cd4: 4613 mov r3, r2
|
|
8005cd6: 005b lsls r3, r3, #1
|
|
8005cd8: 4413 add r3, r2
|
|
8005cda: 009b lsls r3, r3, #2
|
|
8005cdc: 60fb str r3, [r7, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8005cde: e002 b.n 8005ce6 <HAL_ADC_ConfigChannel+0x742>
|
|
{
|
|
wait_loop_index--;
|
|
8005ce0: 68fb ldr r3, [r7, #12]
|
|
8005ce2: 3b01 subs r3, #1
|
|
8005ce4: 60fb str r3, [r7, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8005ce6: 68fb ldr r3, [r7, #12]
|
|
8005ce8: 2b00 cmp r3, #0
|
|
8005cea: d1f9 bne.n 8005ce0 <HAL_ADC_ConfigChannel+0x73c>
|
|
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
|
8005cec: e051 b.n 8005d92 <HAL_ADC_ConfigChannel+0x7ee>
|
|
}
|
|
}
|
|
}
|
|
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
|
|
8005cee: 683b ldr r3, [r7, #0]
|
|
8005cf0: 681a ldr r2, [r3, #0]
|
|
8005cf2: 2300 movs r3, #0
|
|
8005cf4: f6cc 3384 movt r3, #52100 ; 0xcb84
|
|
8005cf8: 429a cmp r2, r3
|
|
8005cfa: d120 bne.n 8005d3e <HAL_ADC_ConfigChannel+0x79a>
|
|
8005cfc: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
|
|
8005d00: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
|
|
8005d04: 2b00 cmp r3, #0
|
|
8005d06: d11a bne.n 8005d3e <HAL_ADC_ConfigChannel+0x79a>
|
|
{
|
|
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
|
8005d08: 687b ldr r3, [r7, #4]
|
|
8005d0a: 681a ldr r2, [r3, #0]
|
|
8005d0c: 2300 movs r3, #0
|
|
8005d0e: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005d12: 429a cmp r2, r3
|
|
8005d14: d007 beq.n 8005d26 <HAL_ADC_ConfigChannel+0x782>
|
|
8005d16: 687b ldr r3, [r7, #4]
|
|
8005d18: 681a ldr r2, [r3, #0]
|
|
8005d1a: f44f 7300 mov.w r3, #512 ; 0x200
|
|
8005d1e: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005d22: 429a cmp r2, r3
|
|
8005d24: d137 bne.n 8005d96 <HAL_ADC_ConfigChannel+0x7f2>
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8005d26: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
|
|
8005d2a: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
8005d2e: 4619 mov r1, r3
|
|
8005d30: f44f 7040 mov.w r0, #768 ; 0x300
|
|
8005d34: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8005d38: f7fe fed0 bl 8004adc <LL_ADC_SetCommonPathInternalCh>
|
|
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
|
8005d3c: e02b b.n 8005d96 <HAL_ADC_ConfigChannel+0x7f2>
|
|
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
|
|
}
|
|
}
|
|
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
|
|
8005d3e: 683b ldr r3, [r7, #0]
|
|
8005d40: 681a ldr r2, [r3, #0]
|
|
8005d42: 2301 movs r3, #1
|
|
8005d44: f2c8 0300 movt r3, #32768 ; 0x8000
|
|
8005d48: 429a cmp r2, r3
|
|
8005d4a: d125 bne.n 8005d98 <HAL_ADC_ConfigChannel+0x7f4>
|
|
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
|
|
8005d4c: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
|
|
8005d50: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
8005d54: 2b00 cmp r3, #0
|
|
8005d56: d11f bne.n 8005d98 <HAL_ADC_ConfigChannel+0x7f4>
|
|
{
|
|
if (ADC_VREFINT_INSTANCE(hadc))
|
|
8005d58: 687b ldr r3, [r7, #4]
|
|
8005d5a: 681a ldr r2, [r3, #0]
|
|
8005d5c: 2300 movs r3, #0
|
|
8005d5e: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8005d62: 429a cmp r2, r3
|
|
8005d64: d118 bne.n 8005d98 <HAL_ADC_ConfigChannel+0x7f4>
|
|
{
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8005d66: f8d7 30c4 ldr.w r3, [r7, #196] ; 0xc4
|
|
8005d6a: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
|
|
8005d6e: 4619 mov r1, r3
|
|
8005d70: f44f 7040 mov.w r0, #768 ; 0x300
|
|
8005d74: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8005d78: f7fe feb0 bl 8004adc <LL_ADC_SetCommonPathInternalCh>
|
|
8005d7c: e00c b.n 8005d98 <HAL_ADC_ConfigChannel+0x7f4>
|
|
/* channel could be done on neither of the channel configuration structure */
|
|
/* parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8005d7e: 687b ldr r3, [r7, #4]
|
|
8005d80: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005d82: f043 0220 orr.w r2, r3, #32
|
|
8005d86: 687b ldr r3, [r7, #4]
|
|
8005d88: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
8005d8a: 2301 movs r3, #1
|
|
8005d8c: f887 30d7 strb.w r3, [r7, #215] ; 0xd7
|
|
8005d90: e002 b.n 8005d98 <HAL_ADC_ConfigChannel+0x7f4>
|
|
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
|
|
8005d92: bf00 nop
|
|
8005d94: e000 b.n 8005d98 <HAL_ADC_ConfigChannel+0x7f4>
|
|
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
|
|
8005d96: bf00 nop
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8005d98: 687b ldr r3, [r7, #4]
|
|
8005d9a: 2200 movs r2, #0
|
|
8005d9c: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8005da0: f897 30d7 ldrb.w r3, [r7, #215] ; 0xd7
|
|
}
|
|
8005da4: 4618 mov r0, r3
|
|
8005da6: 37d8 adds r7, #216 ; 0xd8
|
|
8005da8: 46bd mov sp, r7
|
|
8005daa: bd80 pop {r7, pc}
|
|
|
|
08005dac <ADC_ConversionStop>:
|
|
* @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
|
|
* @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
|
|
{
|
|
8005dac: b580 push {r7, lr}
|
|
8005dae: b088 sub sp, #32
|
|
8005db0: af00 add r7, sp, #0
|
|
8005db2: 6078 str r0, [r7, #4]
|
|
8005db4: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
uint32_t Conversion_Timeout_CPU_cycles = 0UL;
|
|
8005db6: 2300 movs r3, #0
|
|
8005db8: 61fb str r3, [r7, #28]
|
|
uint32_t conversion_group_reassigned = ConversionGroup;
|
|
8005dba: 683b ldr r3, [r7, #0]
|
|
8005dbc: 61bb str r3, [r7, #24]
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
|
|
|
|
/* Verification if ADC is not already stopped (on regular and injected */
|
|
/* groups) to bypass this function if not needed. */
|
|
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
8005dbe: 687b ldr r3, [r7, #4]
|
|
8005dc0: 681b ldr r3, [r3, #0]
|
|
8005dc2: 4618 mov r0, r3
|
|
8005dc4: f7ff f870 bl 8004ea8 <LL_ADC_REG_IsConversionOngoing>
|
|
8005dc8: 6138 str r0, [r7, #16]
|
|
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
|
|
8005dca: 687b ldr r3, [r7, #4]
|
|
8005dcc: 681b ldr r3, [r3, #0]
|
|
8005dce: 4618 mov r0, r3
|
|
8005dd0: f7ff f891 bl 8004ef6 <LL_ADC_INJ_IsConversionOngoing>
|
|
8005dd4: 60f8 str r0, [r7, #12]
|
|
if ((tmp_adc_is_conversion_on_going_regular != 0UL)
|
|
8005dd6: 693b ldr r3, [r7, #16]
|
|
8005dd8: 2b00 cmp r3, #0
|
|
8005dda: d103 bne.n 8005de4 <ADC_ConversionStop+0x38>
|
|
|| (tmp_adc_is_conversion_on_going_injected != 0UL)
|
|
8005ddc: 68fb ldr r3, [r7, #12]
|
|
8005dde: 2b00 cmp r3, #0
|
|
8005de0: f000 809b beq.w 8005f1a <ADC_ConversionStop+0x16e>
|
|
/* auto-delay mode. */
|
|
/* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
|
|
/* injected group stop ADC_CR_JADSTP). */
|
|
/* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
|
|
/* (see reference manual). */
|
|
if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
|
|
8005de4: 687b ldr r3, [r7, #4]
|
|
8005de6: 681b ldr r3, [r3, #0]
|
|
8005de8: 68db ldr r3, [r3, #12]
|
|
8005dea: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8005dee: 2b00 cmp r3, #0
|
|
8005df0: d02d beq.n 8005e4e <ADC_ConversionStop+0xa2>
|
|
&& (hadc->Init.ContinuousConvMode == ENABLE)
|
|
8005df2: 687b ldr r3, [r7, #4]
|
|
8005df4: 7e5b ldrb r3, [r3, #25]
|
|
8005df6: 2b01 cmp r3, #1
|
|
8005df8: d129 bne.n 8005e4e <ADC_ConversionStop+0xa2>
|
|
&& (hadc->Init.LowPowerAutoWait == ENABLE)
|
|
8005dfa: 687b ldr r3, [r7, #4]
|
|
8005dfc: 7e1b ldrb r3, [r3, #24]
|
|
8005dfe: 2b01 cmp r3, #1
|
|
8005e00: d125 bne.n 8005e4e <ADC_ConversionStop+0xa2>
|
|
)
|
|
{
|
|
/* Use stop of regular group */
|
|
conversion_group_reassigned = ADC_REGULAR_GROUP;
|
|
8005e02: 2301 movs r3, #1
|
|
8005e04: 61bb str r3, [r7, #24]
|
|
|
|
/* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
|
|
8005e06: e017 b.n 8005e38 <ADC_ConversionStop+0x8c>
|
|
{
|
|
if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
|
|
8005e08: 69fa ldr r2, [r7, #28]
|
|
8005e0a: f64f 73ff movw r3, #65535 ; 0xffff
|
|
8005e0e: f2ca 333f movt r3, #41791 ; 0xa33f
|
|
8005e12: 429a cmp r2, r3
|
|
8005e14: d90d bls.n 8005e32 <ADC_ConversionStop+0x86>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8005e16: 687b ldr r3, [r7, #4]
|
|
8005e18: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005e1a: f043 0210 orr.w r2, r3, #16
|
|
8005e1e: 687b ldr r3, [r7, #4]
|
|
8005e20: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8005e22: 687b ldr r3, [r7, #4]
|
|
8005e24: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8005e26: f043 0201 orr.w r2, r3, #1
|
|
8005e2a: 687b ldr r3, [r7, #4]
|
|
8005e2c: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
return HAL_ERROR;
|
|
8005e2e: 2301 movs r3, #1
|
|
8005e30: e074 b.n 8005f1c <ADC_ConversionStop+0x170>
|
|
}
|
|
Conversion_Timeout_CPU_cycles ++;
|
|
8005e32: 69fb ldr r3, [r7, #28]
|
|
8005e34: 3301 adds r3, #1
|
|
8005e36: 61fb str r3, [r7, #28]
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
|
|
8005e38: 687b ldr r3, [r7, #4]
|
|
8005e3a: 681b ldr r3, [r3, #0]
|
|
8005e3c: 681b ldr r3, [r3, #0]
|
|
8005e3e: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8005e42: 2b40 cmp r3, #64 ; 0x40
|
|
8005e44: d1e0 bne.n 8005e08 <ADC_ConversionStop+0x5c>
|
|
}
|
|
|
|
/* Clear JEOS */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
|
|
8005e46: 687b ldr r3, [r7, #4]
|
|
8005e48: 681b ldr r3, [r3, #0]
|
|
8005e4a: 2240 movs r2, #64 ; 0x40
|
|
8005e4c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Stop potential conversion on going on ADC group regular */
|
|
if (conversion_group_reassigned != ADC_INJECTED_GROUP)
|
|
8005e4e: 69bb ldr r3, [r7, #24]
|
|
8005e50: 2b02 cmp r3, #2
|
|
8005e52: d014 beq.n 8005e7e <ADC_ConversionStop+0xd2>
|
|
{
|
|
/* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
|
|
8005e54: 687b ldr r3, [r7, #4]
|
|
8005e56: 681b ldr r3, [r3, #0]
|
|
8005e58: 4618 mov r0, r3
|
|
8005e5a: f7ff f825 bl 8004ea8 <LL_ADC_REG_IsConversionOngoing>
|
|
8005e5e: 4603 mov r3, r0
|
|
8005e60: 2b00 cmp r3, #0
|
|
8005e62: d00c beq.n 8005e7e <ADC_ConversionStop+0xd2>
|
|
{
|
|
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
|
|
8005e64: 687b ldr r3, [r7, #4]
|
|
8005e66: 681b ldr r3, [r3, #0]
|
|
8005e68: 4618 mov r0, r3
|
|
8005e6a: f7fe ffe2 bl 8004e32 <LL_ADC_IsDisableOngoing>
|
|
8005e6e: 4603 mov r3, r0
|
|
8005e70: 2b00 cmp r3, #0
|
|
8005e72: d104 bne.n 8005e7e <ADC_ConversionStop+0xd2>
|
|
{
|
|
/* Stop ADC group regular conversion */
|
|
LL_ADC_REG_StopConversion(hadc->Instance);
|
|
8005e74: 687b ldr r3, [r7, #4]
|
|
8005e76: 681b ldr r3, [r3, #0]
|
|
8005e78: 4618 mov r0, r3
|
|
8005e7a: f7ff f801 bl 8004e80 <LL_ADC_REG_StopConversion>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Stop potential conversion on going on ADC group injected */
|
|
if (conversion_group_reassigned != ADC_REGULAR_GROUP)
|
|
8005e7e: 69bb ldr r3, [r7, #24]
|
|
8005e80: 2b01 cmp r3, #1
|
|
8005e82: d014 beq.n 8005eae <ADC_ConversionStop+0x102>
|
|
{
|
|
/* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
|
|
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
|
|
8005e84: 687b ldr r3, [r7, #4]
|
|
8005e86: 681b ldr r3, [r3, #0]
|
|
8005e88: 4618 mov r0, r3
|
|
8005e8a: f7ff f834 bl 8004ef6 <LL_ADC_INJ_IsConversionOngoing>
|
|
8005e8e: 4603 mov r3, r0
|
|
8005e90: 2b00 cmp r3, #0
|
|
8005e92: d00c beq.n 8005eae <ADC_ConversionStop+0x102>
|
|
{
|
|
if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
|
|
8005e94: 687b ldr r3, [r7, #4]
|
|
8005e96: 681b ldr r3, [r3, #0]
|
|
8005e98: 4618 mov r0, r3
|
|
8005e9a: f7fe ffca bl 8004e32 <LL_ADC_IsDisableOngoing>
|
|
8005e9e: 4603 mov r3, r0
|
|
8005ea0: 2b00 cmp r3, #0
|
|
8005ea2: d104 bne.n 8005eae <ADC_ConversionStop+0x102>
|
|
{
|
|
/* Stop ADC group injected conversion */
|
|
LL_ADC_INJ_StopConversion(hadc->Instance);
|
|
8005ea4: 687b ldr r3, [r7, #4]
|
|
8005ea6: 681b ldr r3, [r3, #0]
|
|
8005ea8: 4618 mov r0, r3
|
|
8005eaa: f7ff f810 bl 8004ece <LL_ADC_INJ_StopConversion>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Selection of start and stop bits with respect to the regular or injected group */
|
|
switch (conversion_group_reassigned)
|
|
8005eae: 69bb ldr r3, [r7, #24]
|
|
8005eb0: 2b02 cmp r3, #2
|
|
8005eb2: d005 beq.n 8005ec0 <ADC_ConversionStop+0x114>
|
|
8005eb4: 69bb ldr r3, [r7, #24]
|
|
8005eb6: 2b03 cmp r3, #3
|
|
8005eb8: d105 bne.n 8005ec6 <ADC_ConversionStop+0x11a>
|
|
{
|
|
case ADC_REGULAR_INJECTED_GROUP:
|
|
tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
|
|
8005eba: 230c movs r3, #12
|
|
8005ebc: 617b str r3, [r7, #20]
|
|
break;
|
|
8005ebe: e005 b.n 8005ecc <ADC_ConversionStop+0x120>
|
|
case ADC_INJECTED_GROUP:
|
|
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
|
|
8005ec0: 2308 movs r3, #8
|
|
8005ec2: 617b str r3, [r7, #20]
|
|
break;
|
|
8005ec4: e002 b.n 8005ecc <ADC_ConversionStop+0x120>
|
|
/* Case ADC_REGULAR_GROUP only*/
|
|
default:
|
|
tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
|
|
8005ec6: 2304 movs r3, #4
|
|
8005ec8: 617b str r3, [r7, #20]
|
|
break;
|
|
8005eca: bf00 nop
|
|
}
|
|
|
|
/* Wait for conversion effectively stopped */
|
|
tickstart = HAL_GetTick();
|
|
8005ecc: f7fe fd9d bl 8004a0a <HAL_GetTick>
|
|
8005ed0: 60b8 str r0, [r7, #8]
|
|
|
|
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
|
|
8005ed2: e01b b.n 8005f0c <ADC_ConversionStop+0x160>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
|
|
8005ed4: f7fe fd99 bl 8004a0a <HAL_GetTick>
|
|
8005ed8: 4602 mov r2, r0
|
|
8005eda: 68bb ldr r3, [r7, #8]
|
|
8005edc: 1ad3 subs r3, r2, r3
|
|
8005ede: 2b05 cmp r3, #5
|
|
8005ee0: d914 bls.n 8005f0c <ADC_ConversionStop+0x160>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
|
|
8005ee2: 687b ldr r3, [r7, #4]
|
|
8005ee4: 681b ldr r3, [r3, #0]
|
|
8005ee6: 689a ldr r2, [r3, #8]
|
|
8005ee8: 697b ldr r3, [r7, #20]
|
|
8005eea: 4013 ands r3, r2
|
|
8005eec: 2b00 cmp r3, #0
|
|
8005eee: d00d beq.n 8005f0c <ADC_ConversionStop+0x160>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8005ef0: 687b ldr r3, [r7, #4]
|
|
8005ef2: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005ef4: f043 0210 orr.w r2, r3, #16
|
|
8005ef8: 687b ldr r3, [r7, #4]
|
|
8005efa: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8005efc: 687b ldr r3, [r7, #4]
|
|
8005efe: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8005f00: f043 0201 orr.w r2, r3, #1
|
|
8005f04: 687b ldr r3, [r7, #4]
|
|
8005f06: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
return HAL_ERROR;
|
|
8005f08: 2301 movs r3, #1
|
|
8005f0a: e007 b.n 8005f1c <ADC_ConversionStop+0x170>
|
|
while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
|
|
8005f0c: 687b ldr r3, [r7, #4]
|
|
8005f0e: 681b ldr r3, [r3, #0]
|
|
8005f10: 689a ldr r2, [r3, #8]
|
|
8005f12: 697b ldr r3, [r7, #20]
|
|
8005f14: 4013 ands r3, r2
|
|
8005f16: 2b00 cmp r3, #0
|
|
8005f18: d1dc bne.n 8005ed4 <ADC_ConversionStop+0x128>
|
|
}
|
|
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
8005f1a: 2300 movs r3, #0
|
|
}
|
|
8005f1c: 4618 mov r0, r3
|
|
8005f1e: 3720 adds r7, #32
|
|
8005f20: 46bd mov sp, r7
|
|
8005f22: bd80 pop {r7, pc}
|
|
|
|
08005f24 <ADC_Enable>:
|
|
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8005f24: b580 push {r7, lr}
|
|
8005f26: b084 sub sp, #16
|
|
8005f28: af00 add r7, sp, #0
|
|
8005f2a: 6078 str r0, [r7, #4]
|
|
|
|
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
|
|
/* enabling phase not yet completed: flag ADC ready not yet set). */
|
|
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
|
|
/* causes: ADC clock not running, ...). */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
8005f2c: 687b ldr r3, [r7, #4]
|
|
8005f2e: 681b ldr r3, [r3, #0]
|
|
8005f30: 4618 mov r0, r3
|
|
8005f32: f7fe ff6b bl 8004e0c <LL_ADC_IsEnabled>
|
|
8005f36: 4603 mov r3, r0
|
|
8005f38: 2b00 cmp r3, #0
|
|
8005f3a: d14f bne.n 8005fdc <ADC_Enable+0xb8>
|
|
{
|
|
/* Check if conditions to enable the ADC are fulfilled */
|
|
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
|
|
8005f3c: 687b ldr r3, [r7, #4]
|
|
8005f3e: 681b ldr r3, [r3, #0]
|
|
8005f40: 689a ldr r2, [r3, #8]
|
|
8005f42: 233f movs r3, #63 ; 0x3f
|
|
8005f44: f2c8 0300 movt r3, #32768 ; 0x8000
|
|
8005f48: 4013 ands r3, r2
|
|
8005f4a: 2b00 cmp r3, #0
|
|
8005f4c: d00d beq.n 8005f6a <ADC_Enable+0x46>
|
|
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8005f4e: 687b ldr r3, [r7, #4]
|
|
8005f50: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005f52: f043 0210 orr.w r2, r3, #16
|
|
8005f56: 687b ldr r3, [r7, #4]
|
|
8005f58: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8005f5a: 687b ldr r3, [r7, #4]
|
|
8005f5c: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8005f5e: f043 0201 orr.w r2, r3, #1
|
|
8005f62: 687b ldr r3, [r7, #4]
|
|
8005f64: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
return HAL_ERROR;
|
|
8005f66: 2301 movs r3, #1
|
|
8005f68: e039 b.n 8005fde <ADC_Enable+0xba>
|
|
}
|
|
|
|
/* Enable the ADC peripheral */
|
|
LL_ADC_Enable(hadc->Instance);
|
|
8005f6a: 687b ldr r3, [r7, #4]
|
|
8005f6c: 681b ldr r3, [r3, #0]
|
|
8005f6e: 4618 mov r0, r3
|
|
8005f70: f7fe ff24 bl 8004dbc <LL_ADC_Enable>
|
|
|
|
/* Wait for ADC effectively enabled */
|
|
tickstart = HAL_GetTick();
|
|
8005f74: f7fe fd49 bl 8004a0a <HAL_GetTick>
|
|
8005f78: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
|
|
8005f7a: e028 b.n 8005fce <ADC_Enable+0xaa>
|
|
The workaround is to continue setting ADEN until ADRDY is becomes 1.
|
|
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
|
|
4 ADC clock cycle duration */
|
|
/* Note: Test of ADC enabled required due to hardware constraint to */
|
|
/* not enable ADC if already enabled. */
|
|
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
|
|
8005f7c: 687b ldr r3, [r7, #4]
|
|
8005f7e: 681b ldr r3, [r3, #0]
|
|
8005f80: 4618 mov r0, r3
|
|
8005f82: f7fe ff43 bl 8004e0c <LL_ADC_IsEnabled>
|
|
8005f86: 4603 mov r3, r0
|
|
8005f88: 2b00 cmp r3, #0
|
|
8005f8a: d104 bne.n 8005f96 <ADC_Enable+0x72>
|
|
{
|
|
LL_ADC_Enable(hadc->Instance);
|
|
8005f8c: 687b ldr r3, [r7, #4]
|
|
8005f8e: 681b ldr r3, [r3, #0]
|
|
8005f90: 4618 mov r0, r3
|
|
8005f92: f7fe ff13 bl 8004dbc <LL_ADC_Enable>
|
|
}
|
|
|
|
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
|
|
8005f96: f7fe fd38 bl 8004a0a <HAL_GetTick>
|
|
8005f9a: 4602 mov r2, r0
|
|
8005f9c: 68fb ldr r3, [r7, #12]
|
|
8005f9e: 1ad3 subs r3, r2, r3
|
|
8005fa0: 2b02 cmp r3, #2
|
|
8005fa2: d914 bls.n 8005fce <ADC_Enable+0xaa>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
|
|
8005fa4: 687b ldr r3, [r7, #4]
|
|
8005fa6: 681b ldr r3, [r3, #0]
|
|
8005fa8: 681b ldr r3, [r3, #0]
|
|
8005faa: f003 0301 and.w r3, r3, #1
|
|
8005fae: 2b01 cmp r3, #1
|
|
8005fb0: d00d beq.n 8005fce <ADC_Enable+0xaa>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8005fb2: 687b ldr r3, [r7, #4]
|
|
8005fb4: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8005fb6: f043 0210 orr.w r2, r3, #16
|
|
8005fba: 687b ldr r3, [r7, #4]
|
|
8005fbc: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8005fbe: 687b ldr r3, [r7, #4]
|
|
8005fc0: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8005fc2: f043 0201 orr.w r2, r3, #1
|
|
8005fc6: 687b ldr r3, [r7, #4]
|
|
8005fc8: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
return HAL_ERROR;
|
|
8005fca: 2301 movs r3, #1
|
|
8005fcc: e007 b.n 8005fde <ADC_Enable+0xba>
|
|
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
|
|
8005fce: 687b ldr r3, [r7, #4]
|
|
8005fd0: 681b ldr r3, [r3, #0]
|
|
8005fd2: 681b ldr r3, [r3, #0]
|
|
8005fd4: f003 0301 and.w r3, r3, #1
|
|
8005fd8: 2b01 cmp r3, #1
|
|
8005fda: d1cf bne.n 8005f7c <ADC_Enable+0x58>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
8005fdc: 2300 movs r3, #0
|
|
}
|
|
8005fde: 4618 mov r0, r3
|
|
8005fe0: 3710 adds r7, #16
|
|
8005fe2: 46bd mov sp, r7
|
|
8005fe4: bd80 pop {r7, pc}
|
|
|
|
08005fe6 <ADC_Disable>:
|
|
* stopped.
|
|
* @param hadc ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
|
|
{
|
|
8005fe6: b580 push {r7, lr}
|
|
8005fe8: b084 sub sp, #16
|
|
8005fea: af00 add r7, sp, #0
|
|
8005fec: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
|
|
8005fee: 687b ldr r3, [r7, #4]
|
|
8005ff0: 681b ldr r3, [r3, #0]
|
|
8005ff2: 4618 mov r0, r3
|
|
8005ff4: f7fe ff1d bl 8004e32 <LL_ADC_IsDisableOngoing>
|
|
8005ff8: 60f8 str r0, [r7, #12]
|
|
|
|
/* Verification if ADC is not already disabled: */
|
|
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
|
|
/* disabled. */
|
|
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
|
|
8005ffa: 687b ldr r3, [r7, #4]
|
|
8005ffc: 681b ldr r3, [r3, #0]
|
|
8005ffe: 4618 mov r0, r3
|
|
8006000: f7fe ff04 bl 8004e0c <LL_ADC_IsEnabled>
|
|
8006004: 4603 mov r3, r0
|
|
8006006: 2b00 cmp r3, #0
|
|
8006008: d047 beq.n 800609a <ADC_Disable+0xb4>
|
|
&& (tmp_adc_is_disable_on_going == 0UL)
|
|
800600a: 68fb ldr r3, [r7, #12]
|
|
800600c: 2b00 cmp r3, #0
|
|
800600e: d144 bne.n 800609a <ADC_Disable+0xb4>
|
|
)
|
|
{
|
|
/* Check if conditions to disable the ADC are fulfilled */
|
|
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
|
|
8006010: 687b ldr r3, [r7, #4]
|
|
8006012: 681b ldr r3, [r3, #0]
|
|
8006014: 689b ldr r3, [r3, #8]
|
|
8006016: f003 030d and.w r3, r3, #13
|
|
800601a: 2b01 cmp r3, #1
|
|
800601c: d10c bne.n 8006038 <ADC_Disable+0x52>
|
|
{
|
|
/* Disable the ADC peripheral */
|
|
LL_ADC_Disable(hadc->Instance);
|
|
800601e: 687b ldr r3, [r7, #4]
|
|
8006020: 681b ldr r3, [r3, #0]
|
|
8006022: 4618 mov r0, r3
|
|
8006024: f7fe fede bl 8004de4 <LL_ADC_Disable>
|
|
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
|
|
8006028: 687b ldr r3, [r7, #4]
|
|
800602a: 681b ldr r3, [r3, #0]
|
|
800602c: 2203 movs r2, #3
|
|
800602e: 601a str r2, [r3, #0]
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Wait for ADC effectively disabled */
|
|
/* Get tick count */
|
|
tickstart = HAL_GetTick();
|
|
8006030: f7fe fceb bl 8004a0a <HAL_GetTick>
|
|
8006034: 60b8 str r0, [r7, #8]
|
|
|
|
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
|
|
8006036: e029 b.n 800608c <ADC_Disable+0xa6>
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8006038: 687b ldr r3, [r7, #4]
|
|
800603a: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800603c: f043 0210 orr.w r2, r3, #16
|
|
8006040: 687b ldr r3, [r7, #4]
|
|
8006042: 655a str r2, [r3, #84] ; 0x54
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8006044: 687b ldr r3, [r7, #4]
|
|
8006046: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8006048: f043 0201 orr.w r2, r3, #1
|
|
800604c: 687b ldr r3, [r7, #4]
|
|
800604e: 659a str r2, [r3, #88] ; 0x58
|
|
return HAL_ERROR;
|
|
8006050: 2301 movs r3, #1
|
|
8006052: e023 b.n 800609c <ADC_Disable+0xb6>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
|
|
8006054: f7fe fcd9 bl 8004a0a <HAL_GetTick>
|
|
8006058: 4602 mov r2, r0
|
|
800605a: 68bb ldr r3, [r7, #8]
|
|
800605c: 1ad3 subs r3, r2, r3
|
|
800605e: 2b02 cmp r3, #2
|
|
8006060: d914 bls.n 800608c <ADC_Disable+0xa6>
|
|
{
|
|
/* New check to avoid false timeout detection in case of preemption */
|
|
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
|
|
8006062: 687b ldr r3, [r7, #4]
|
|
8006064: 681b ldr r3, [r3, #0]
|
|
8006066: 689b ldr r3, [r3, #8]
|
|
8006068: f003 0301 and.w r3, r3, #1
|
|
800606c: 2b00 cmp r3, #0
|
|
800606e: d00d beq.n 800608c <ADC_Disable+0xa6>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8006070: 687b ldr r3, [r7, #4]
|
|
8006072: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8006074: f043 0210 orr.w r2, r3, #16
|
|
8006078: 687b ldr r3, [r7, #4]
|
|
800607a: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
800607c: 687b ldr r3, [r7, #4]
|
|
800607e: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8006080: f043 0201 orr.w r2, r3, #1
|
|
8006084: 687b ldr r3, [r7, #4]
|
|
8006086: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
return HAL_ERROR;
|
|
8006088: 2301 movs r3, #1
|
|
800608a: e007 b.n 800609c <ADC_Disable+0xb6>
|
|
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
|
|
800608c: 687b ldr r3, [r7, #4]
|
|
800608e: 681b ldr r3, [r3, #0]
|
|
8006090: 689b ldr r3, [r3, #8]
|
|
8006092: f003 0301 and.w r3, r3, #1
|
|
8006096: 2b00 cmp r3, #0
|
|
8006098: d1dc bne.n 8006054 <ADC_Disable+0x6e>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return HAL status */
|
|
return HAL_OK;
|
|
800609a: 2300 movs r3, #0
|
|
}
|
|
800609c: 4618 mov r0, r3
|
|
800609e: 3710 adds r7, #16
|
|
80060a0: 46bd mov sp, r7
|
|
80060a2: bd80 pop {r7, pc}
|
|
|
|
080060a4 <LL_ADC_IsEnabled>:
|
|
{
|
|
80060a4: b480 push {r7}
|
|
80060a6: b083 sub sp, #12
|
|
80060a8: af00 add r7, sp, #0
|
|
80060aa: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
|
|
80060ac: 687b ldr r3, [r7, #4]
|
|
80060ae: 689b ldr r3, [r3, #8]
|
|
80060b0: f003 0301 and.w r3, r3, #1
|
|
80060b4: 2b01 cmp r3, #1
|
|
80060b6: d101 bne.n 80060bc <LL_ADC_IsEnabled+0x18>
|
|
80060b8: 2301 movs r3, #1
|
|
80060ba: e000 b.n 80060be <LL_ADC_IsEnabled+0x1a>
|
|
80060bc: 2300 movs r3, #0
|
|
}
|
|
80060be: 4618 mov r0, r3
|
|
80060c0: 370c adds r7, #12
|
|
80060c2: 46bd mov sp, r7
|
|
80060c4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80060c8: 4770 bx lr
|
|
|
|
080060ca <LL_ADC_StartCalibration>:
|
|
{
|
|
80060ca: b480 push {r7}
|
|
80060cc: b083 sub sp, #12
|
|
80060ce: af00 add r7, sp, #0
|
|
80060d0: 6078 str r0, [r7, #4]
|
|
80060d2: 6039 str r1, [r7, #0]
|
|
MODIFY_REG(ADCx->CR,
|
|
80060d4: 687b ldr r3, [r7, #4]
|
|
80060d6: 689b ldr r3, [r3, #8]
|
|
80060d8: f023 4340 bic.w r3, r3, #3221225472 ; 0xc0000000
|
|
80060dc: f023 033f bic.w r3, r3, #63 ; 0x3f
|
|
80060e0: 683a ldr r2, [r7, #0]
|
|
80060e2: f002 4280 and.w r2, r2, #1073741824 ; 0x40000000
|
|
80060e6: 4313 orrs r3, r2
|
|
80060e8: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000
|
|
80060ec: 687b ldr r3, [r7, #4]
|
|
80060ee: 609a str r2, [r3, #8]
|
|
}
|
|
80060f0: bf00 nop
|
|
80060f2: 370c adds r7, #12
|
|
80060f4: 46bd mov sp, r7
|
|
80060f6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80060fa: 4770 bx lr
|
|
|
|
080060fc <LL_ADC_IsCalibrationOnGoing>:
|
|
{
|
|
80060fc: b480 push {r7}
|
|
80060fe: b083 sub sp, #12
|
|
8006100: af00 add r7, sp, #0
|
|
8006102: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
|
|
8006104: 687b ldr r3, [r7, #4]
|
|
8006106: 689b ldr r3, [r3, #8]
|
|
8006108: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
|
|
800610c: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
|
|
8006110: d101 bne.n 8006116 <LL_ADC_IsCalibrationOnGoing+0x1a>
|
|
8006112: 2301 movs r3, #1
|
|
8006114: e000 b.n 8006118 <LL_ADC_IsCalibrationOnGoing+0x1c>
|
|
8006116: 2300 movs r3, #0
|
|
}
|
|
8006118: 4618 mov r0, r3
|
|
800611a: 370c adds r7, #12
|
|
800611c: 46bd mov sp, r7
|
|
800611e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006122: 4770 bx lr
|
|
|
|
08006124 <LL_ADC_REG_IsConversionOngoing>:
|
|
{
|
|
8006124: b480 push {r7}
|
|
8006126: b083 sub sp, #12
|
|
8006128: af00 add r7, sp, #0
|
|
800612a: 6078 str r0, [r7, #4]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
|
|
800612c: 687b ldr r3, [r7, #4]
|
|
800612e: 689b ldr r3, [r3, #8]
|
|
8006130: f003 0304 and.w r3, r3, #4
|
|
8006134: 2b04 cmp r3, #4
|
|
8006136: d101 bne.n 800613c <LL_ADC_REG_IsConversionOngoing+0x18>
|
|
8006138: 2301 movs r3, #1
|
|
800613a: e000 b.n 800613e <LL_ADC_REG_IsConversionOngoing+0x1a>
|
|
800613c: 2300 movs r3, #0
|
|
}
|
|
800613e: 4618 mov r0, r3
|
|
8006140: 370c adds r7, #12
|
|
8006142: 46bd mov sp, r7
|
|
8006144: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006148: 4770 bx lr
|
|
|
|
0800614a <HAL_ADCEx_Calibration_Start>:
|
|
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
|
|
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
|
|
{
|
|
800614a: b580 push {r7, lr}
|
|
800614c: b084 sub sp, #16
|
|
800614e: af00 add r7, sp, #0
|
|
8006150: 6078 str r0, [r7, #4]
|
|
8006152: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8006154: 2300 movs r3, #0
|
|
8006156: 60bb str r3, [r7, #8]
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8006158: 687b ldr r3, [r7, #4]
|
|
800615a: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
|
|
800615e: 2b01 cmp r3, #1
|
|
8006160: d101 bne.n 8006166 <HAL_ADCEx_Calibration_Start+0x1c>
|
|
8006162: 2302 movs r3, #2
|
|
8006164: e04d b.n 8006202 <HAL_ADCEx_Calibration_Start+0xb8>
|
|
8006166: 687b ldr r3, [r7, #4]
|
|
8006168: 2201 movs r2, #1
|
|
800616a: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* Calibration prerequisite: ADC must be disabled. */
|
|
|
|
/* Disable the ADC (if not already disabled) */
|
|
tmp_hal_status = ADC_Disable(hadc);
|
|
800616e: 6878 ldr r0, [r7, #4]
|
|
8006170: f7ff ff39 bl 8005fe6 <ADC_Disable>
|
|
8006174: 4603 mov r3, r0
|
|
8006176: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
8006178: 7bfb ldrb r3, [r7, #15]
|
|
800617a: 2b00 cmp r3, #0
|
|
800617c: d136 bne.n 80061ec <HAL_ADCEx_Calibration_Start+0xa2>
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
800617e: 687b ldr r3, [r7, #4]
|
|
8006180: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8006182: f423 5388 bic.w r3, r3, #4352 ; 0x1100
|
|
8006186: f023 0302 bic.w r3, r3, #2
|
|
800618a: f043 0202 orr.w r2, r3, #2
|
|
800618e: 687b ldr r3, [r7, #4]
|
|
8006190: 655a str r2, [r3, #84] ; 0x54
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_BUSY_INTERNAL);
|
|
|
|
/* Start ADC calibration in mode single-ended or differential */
|
|
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
|
|
8006192: 687b ldr r3, [r7, #4]
|
|
8006194: 681b ldr r3, [r3, #0]
|
|
8006196: 6839 ldr r1, [r7, #0]
|
|
8006198: 4618 mov r0, r3
|
|
800619a: f7ff ff96 bl 80060ca <LL_ADC_StartCalibration>
|
|
|
|
/* Wait for calibration completion */
|
|
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
|
|
800619e: e014 b.n 80061ca <HAL_ADCEx_Calibration_Start+0x80>
|
|
{
|
|
wait_loop_index++;
|
|
80061a0: 68bb ldr r3, [r7, #8]
|
|
80061a2: 3301 adds r3, #1
|
|
80061a4: 60bb str r3, [r7, #8]
|
|
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
|
|
80061a6: 68bb ldr r3, [r7, #8]
|
|
80061a8: f5b3 2f91 cmp.w r3, #296960 ; 0x48800
|
|
80061ac: d30d bcc.n 80061ca <HAL_ADCEx_Calibration_Start+0x80>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80061ae: 687b ldr r3, [r7, #4]
|
|
80061b0: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80061b2: f023 0312 bic.w r3, r3, #18
|
|
80061b6: f043 0210 orr.w r2, r3, #16
|
|
80061ba: 687b ldr r3, [r7, #4]
|
|
80061bc: 655a str r2, [r3, #84] ; 0x54
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80061be: 687b ldr r3, [r7, #4]
|
|
80061c0: 2200 movs r2, #0
|
|
80061c2: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
return HAL_ERROR;
|
|
80061c6: 2301 movs r3, #1
|
|
80061c8: e01b b.n 8006202 <HAL_ADCEx_Calibration_Start+0xb8>
|
|
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
|
|
80061ca: 687b ldr r3, [r7, #4]
|
|
80061cc: 681b ldr r3, [r3, #0]
|
|
80061ce: 4618 mov r0, r3
|
|
80061d0: f7ff ff94 bl 80060fc <LL_ADC_IsCalibrationOnGoing>
|
|
80061d4: 4603 mov r3, r0
|
|
80061d6: 2b00 cmp r3, #0
|
|
80061d8: d1e2 bne.n 80061a0 <HAL_ADCEx_Calibration_Start+0x56>
|
|
}
|
|
}
|
|
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80061da: 687b ldr r3, [r7, #4]
|
|
80061dc: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80061de: f023 0303 bic.w r3, r3, #3
|
|
80061e2: f043 0201 orr.w r2, r3, #1
|
|
80061e6: 687b ldr r3, [r7, #4]
|
|
80061e8: 655a str r2, [r3, #84] ; 0x54
|
|
80061ea: e005 b.n 80061f8 <HAL_ADCEx_Calibration_Start+0xae>
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80061ec: 687b ldr r3, [r7, #4]
|
|
80061ee: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80061f0: f043 0210 orr.w r2, r3, #16
|
|
80061f4: 687b ldr r3, [r7, #4]
|
|
80061f6: 655a str r2, [r3, #84] ; 0x54
|
|
/* Note: No need to update variable "tmp_hal_status" here: already set */
|
|
/* to state "HAL_ERROR" by function disabling the ADC. */
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80061f8: 687b ldr r3, [r7, #4]
|
|
80061fa: 2200 movs r2, #0
|
|
80061fc: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
8006200: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006202: 4618 mov r0, r3
|
|
8006204: 3710 adds r7, #16
|
|
8006206: 46bd mov sp, r7
|
|
8006208: bd80 pop {r7, pc}
|
|
|
|
0800620a <HAL_ADCEx_MultiModeConfigChannel>:
|
|
* @param hadc Master ADC handle
|
|
* @param multimode Structure of ADC multimode configuration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode)
|
|
{
|
|
800620a: b590 push {r4, r7, lr}
|
|
800620c: b09f sub sp, #124 ; 0x7c
|
|
800620e: af00 add r7, sp, #0
|
|
8006210: 6078 str r0, [r7, #4]
|
|
8006212: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8006214: 2300 movs r3, #0
|
|
8006216: f887 3077 strb.w r3, [r7, #119] ; 0x77
|
|
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
|
|
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
800621a: 687b ldr r3, [r7, #4]
|
|
800621c: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
|
|
8006220: 2b01 cmp r3, #1
|
|
8006222: d101 bne.n 8006228 <HAL_ADCEx_MultiModeConfigChannel+0x1e>
|
|
8006224: 2302 movs r3, #2
|
|
8006226: e0ab b.n 8006380 <HAL_ADCEx_MultiModeConfigChannel+0x176>
|
|
8006228: 687b ldr r3, [r7, #4]
|
|
800622a: 2201 movs r2, #1
|
|
800622c: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* Temporary handle minimum initialization */
|
|
__HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave);
|
|
8006230: 2300 movs r3, #0
|
|
8006232: 65fb str r3, [r7, #92] ; 0x5c
|
|
ADC_CLEAR_ERRORCODE(&tmphadcSlave);
|
|
8006234: 2300 movs r3, #0
|
|
8006236: 663b str r3, [r7, #96] ; 0x60
|
|
|
|
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
|
8006238: 687b ldr r3, [r7, #4]
|
|
800623a: 681a ldr r2, [r3, #0]
|
|
800623c: 2300 movs r3, #0
|
|
800623e: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
8006242: 429a cmp r2, r3
|
|
8006244: d105 bne.n 8006252 <HAL_ADCEx_MultiModeConfigChannel+0x48>
|
|
8006246: f44f 7380 mov.w r3, #256 ; 0x100
|
|
800624a: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
800624e: 60bb str r3, [r7, #8]
|
|
8006250: e001 b.n 8006256 <HAL_ADCEx_MultiModeConfigChannel+0x4c>
|
|
8006252: 2300 movs r3, #0
|
|
8006254: 60bb str r3, [r7, #8]
|
|
|
|
if (tmphadcSlave.Instance == NULL)
|
|
8006256: 68bb ldr r3, [r7, #8]
|
|
8006258: 2b00 cmp r3, #0
|
|
800625a: d10b bne.n 8006274 <HAL_ADCEx_MultiModeConfigChannel+0x6a>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
800625c: 687b ldr r3, [r7, #4]
|
|
800625e: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8006260: f043 0220 orr.w r2, r3, #32
|
|
8006264: 687b ldr r3, [r7, #4]
|
|
8006266: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8006268: 687b ldr r3, [r7, #4]
|
|
800626a: 2200 movs r2, #0
|
|
800626c: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
return HAL_ERROR;
|
|
8006270: 2301 movs r3, #1
|
|
8006272: e085 b.n 8006380 <HAL_ADCEx_MultiModeConfigChannel+0x176>
|
|
/* Parameters update conditioned to ADC state: */
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Multimode DMA configuration */
|
|
/* - Multimode DMA mode */
|
|
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
|
|
8006274: 68bb ldr r3, [r7, #8]
|
|
8006276: 4618 mov r0, r3
|
|
8006278: f7ff ff54 bl 8006124 <LL_ADC_REG_IsConversionOngoing>
|
|
800627c: 6738 str r0, [r7, #112] ; 0x70
|
|
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
800627e: 687b ldr r3, [r7, #4]
|
|
8006280: 681b ldr r3, [r3, #0]
|
|
8006282: 4618 mov r0, r3
|
|
8006284: f7ff ff4e bl 8006124 <LL_ADC_REG_IsConversionOngoing>
|
|
8006288: 4603 mov r3, r0
|
|
800628a: 2b00 cmp r3, #0
|
|
800628c: d167 bne.n 800635e <HAL_ADCEx_MultiModeConfigChannel+0x154>
|
|
&& (tmphadcSlave_conversion_on_going == 0UL))
|
|
800628e: 6f3b ldr r3, [r7, #112] ; 0x70
|
|
8006290: 2b00 cmp r3, #0
|
|
8006292: d164 bne.n 800635e <HAL_ADCEx_MultiModeConfigChannel+0x154>
|
|
{
|
|
/* Pointer to the common control register */
|
|
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
|
|
8006294: f44f 7340 mov.w r3, #768 ; 0x300
|
|
8006298: f2c5 0304 movt r3, #20484 ; 0x5004
|
|
800629c: 66fb str r3, [r7, #108] ; 0x6c
|
|
|
|
/* If multimode is selected, configure all multimode parameters. */
|
|
/* Otherwise, reset multimode parameters (can be used in case of */
|
|
/* transition from multimode to independent mode). */
|
|
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
800629e: 683b ldr r3, [r7, #0]
|
|
80062a0: 681b ldr r3, [r3, #0]
|
|
80062a2: 2b00 cmp r3, #0
|
|
80062a4: d034 beq.n 8006310 <HAL_ADCEx_MultiModeConfigChannel+0x106>
|
|
{
|
|
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
|
|
80062a6: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
80062a8: 689b ldr r3, [r3, #8]
|
|
80062aa: f423 4260 bic.w r2, r3, #57344 ; 0xe000
|
|
80062ae: 683b ldr r3, [r7, #0]
|
|
80062b0: 6859 ldr r1, [r3, #4]
|
|
80062b2: 687b ldr r3, [r7, #4]
|
|
80062b4: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
80062b8: 035b lsls r3, r3, #13
|
|
80062ba: 430b orrs r3, r1
|
|
80062bc: 431a orrs r2, r3
|
|
80062be: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
80062c0: 609a str r2, [r3, #8]
|
|
/* from 1 to 10 clock cycles for 10 bits, */
|
|
/* from 1 to 8 clock cycles for 8 bits */
|
|
/* from 1 to 6 clock cycles for 6 bits */
|
|
/* If a higher delay is selected, it will be clipped to maximum delay */
|
|
/* range */
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
80062c2: 2000 movs r0, #0
|
|
80062c4: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
80062c8: f7ff feec bl 80060a4 <LL_ADC_IsEnabled>
|
|
80062cc: 4604 mov r4, r0
|
|
80062ce: f44f 7080 mov.w r0, #256 ; 0x100
|
|
80062d2: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
80062d6: f7ff fee5 bl 80060a4 <LL_ADC_IsEnabled>
|
|
80062da: 4603 mov r3, r0
|
|
80062dc: 431c orrs r4, r3
|
|
80062de: f44f 7000 mov.w r0, #512 ; 0x200
|
|
80062e2: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
80062e6: f7ff fedd bl 80060a4 <LL_ADC_IsEnabled>
|
|
80062ea: 4603 mov r3, r0
|
|
80062ec: 4323 orrs r3, r4
|
|
80062ee: 2b00 cmp r3, #0
|
|
80062f0: d13f bne.n 8006372 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
{
|
|
MODIFY_REG(tmpADC_Common->CCR,
|
|
80062f2: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
80062f4: 689b ldr r3, [r3, #8]
|
|
80062f6: f423 6371 bic.w r3, r3, #3856 ; 0xf10
|
|
80062fa: f023 030f bic.w r3, r3, #15
|
|
80062fe: 683a ldr r2, [r7, #0]
|
|
8006300: 6811 ldr r1, [r2, #0]
|
|
8006302: 683a ldr r2, [r7, #0]
|
|
8006304: 6892 ldr r2, [r2, #8]
|
|
8006306: 430a orrs r2, r1
|
|
8006308: 431a orrs r2, r3
|
|
800630a: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
800630c: 609a str r2, [r3, #8]
|
|
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
800630e: e030 b.n 8006372 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
);
|
|
}
|
|
}
|
|
else /* ADC_MODE_INDEPENDENT */
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
|
|
8006310: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
8006312: 689b ldr r3, [r3, #8]
|
|
8006314: f423 4260 bic.w r2, r3, #57344 ; 0xe000
|
|
8006318: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
800631a: 609a str r2, [r3, #8]
|
|
|
|
/* Parameters that can be updated only when ADC is disabled: */
|
|
/* - Multimode mode selection */
|
|
/* - Multimode delay */
|
|
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
|
|
800631c: 2000 movs r0, #0
|
|
800631e: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8006322: f7ff febf bl 80060a4 <LL_ADC_IsEnabled>
|
|
8006326: 4604 mov r4, r0
|
|
8006328: f44f 7080 mov.w r0, #256 ; 0x100
|
|
800632c: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8006330: f7ff feb8 bl 80060a4 <LL_ADC_IsEnabled>
|
|
8006334: 4603 mov r3, r0
|
|
8006336: 431c orrs r4, r3
|
|
8006338: f44f 7000 mov.w r0, #512 ; 0x200
|
|
800633c: f2c5 0004 movt r0, #20484 ; 0x5004
|
|
8006340: f7ff feb0 bl 80060a4 <LL_ADC_IsEnabled>
|
|
8006344: 4603 mov r3, r0
|
|
8006346: 4323 orrs r3, r4
|
|
8006348: 2b00 cmp r3, #0
|
|
800634a: d112 bne.n 8006372 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
{
|
|
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
|
|
800634c: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
800634e: 689b ldr r3, [r3, #8]
|
|
8006350: f423 6371 bic.w r3, r3, #3856 ; 0xf10
|
|
8006354: f023 030f bic.w r3, r3, #15
|
|
8006358: 6efa ldr r2, [r7, #108] ; 0x6c
|
|
800635a: 6093 str r3, [r2, #8]
|
|
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
800635c: e009 b.n 8006372 <HAL_ADCEx_MultiModeConfigChannel+0x168>
|
|
/* If one of the ADC sharing the same common group is enabled, no update */
|
|
/* could be done on neither of the multimode structure parameters. */
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
800635e: 687b ldr r3, [r7, #4]
|
|
8006360: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
8006362: f043 0220 orr.w r2, r3, #32
|
|
8006366: 687b ldr r3, [r7, #4]
|
|
8006368: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
800636a: 2301 movs r3, #1
|
|
800636c: f887 3077 strb.w r3, [r7, #119] ; 0x77
|
|
8006370: e000 b.n 8006374 <HAL_ADCEx_MultiModeConfigChannel+0x16a>
|
|
if (multimode->Mode != ADC_MODE_INDEPENDENT)
|
|
8006372: bf00 nop
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8006374: 687b ldr r3, [r7, #4]
|
|
8006376: 2200 movs r2, #0
|
|
8006378: f883 2050 strb.w r2, [r3, #80] ; 0x50
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
800637c: f897 3077 ldrb.w r3, [r7, #119] ; 0x77
|
|
}
|
|
8006380: 4618 mov r0, r3
|
|
8006382: 377c adds r7, #124 ; 0x7c
|
|
8006384: 46bd mov sp, r7
|
|
8006386: bd90 pop {r4, r7, pc}
|
|
|
|
08006388 <__NVIC_SetPriorityGrouping>:
|
|
{
|
|
8006388: b480 push {r7}
|
|
800638a: b085 sub sp, #20
|
|
800638c: af00 add r7, sp, #0
|
|
800638e: 6078 str r0, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8006390: 687b ldr r3, [r7, #4]
|
|
8006392: f003 0307 and.w r3, r3, #7
|
|
8006396: 60fb str r3, [r7, #12]
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8006398: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
800639c: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
80063a0: 68db ldr r3, [r3, #12]
|
|
80063a2: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80063a4: 68ba ldr r2, [r7, #8]
|
|
80063a6: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
80063aa: 4013 ands r3, r2
|
|
80063ac: 60bb str r3, [r7, #8]
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80063ae: 68fb ldr r3, [r7, #12]
|
|
80063b0: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80063b2: 68bb ldr r3, [r7, #8]
|
|
80063b4: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80063b6: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
|
|
80063ba: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
80063be: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80063c0: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
80063c4: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
80063c8: 68ba ldr r2, [r7, #8]
|
|
80063ca: 60da str r2, [r3, #12]
|
|
}
|
|
80063cc: bf00 nop
|
|
80063ce: 3714 adds r7, #20
|
|
80063d0: 46bd mov sp, r7
|
|
80063d2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063d6: 4770 bx lr
|
|
|
|
080063d8 <__NVIC_GetPriorityGrouping>:
|
|
{
|
|
80063d8: b480 push {r7}
|
|
80063da: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
80063dc: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
80063e0: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
80063e4: 68db ldr r3, [r3, #12]
|
|
80063e6: 0a1b lsrs r3, r3, #8
|
|
80063e8: f003 0307 and.w r3, r3, #7
|
|
}
|
|
80063ec: 4618 mov r0, r3
|
|
80063ee: 46bd mov sp, r7
|
|
80063f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063f4: 4770 bx lr
|
|
|
|
080063f6 <__NVIC_EnableIRQ>:
|
|
{
|
|
80063f6: b480 push {r7}
|
|
80063f8: b083 sub sp, #12
|
|
80063fa: af00 add r7, sp, #0
|
|
80063fc: 4603 mov r3, r0
|
|
80063fe: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8006400: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006404: 2b00 cmp r3, #0
|
|
8006406: db0e blt.n 8006426 <__NVIC_EnableIRQ+0x30>
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8006408: 79fb ldrb r3, [r7, #7]
|
|
800640a: f003 011f and.w r1, r3, #31
|
|
800640e: f44f 4361 mov.w r3, #57600 ; 0xe100
|
|
8006412: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8006416: f997 2007 ldrsb.w r2, [r7, #7]
|
|
800641a: 0952 lsrs r2, r2, #5
|
|
800641c: 2001 movs r0, #1
|
|
800641e: fa00 f101 lsl.w r1, r0, r1
|
|
8006422: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
8006426: bf00 nop
|
|
8006428: 370c adds r7, #12
|
|
800642a: 46bd mov sp, r7
|
|
800642c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006430: 4770 bx lr
|
|
|
|
08006432 <__NVIC_SetPriority>:
|
|
{
|
|
8006432: b480 push {r7}
|
|
8006434: b083 sub sp, #12
|
|
8006436: af00 add r7, sp, #0
|
|
8006438: 4603 mov r3, r0
|
|
800643a: 6039 str r1, [r7, #0]
|
|
800643c: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800643e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8006442: 2b00 cmp r3, #0
|
|
8006444: db0e blt.n 8006464 <__NVIC_SetPriority+0x32>
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8006446: 683b ldr r3, [r7, #0]
|
|
8006448: b2d9 uxtb r1, r3
|
|
800644a: f44f 4361 mov.w r3, #57600 ; 0xe100
|
|
800644e: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8006452: f997 2007 ldrsb.w r2, [r7, #7]
|
|
8006456: 0109 lsls r1, r1, #4
|
|
8006458: b2c9 uxtb r1, r1
|
|
800645a: 4413 add r3, r2
|
|
800645c: 460a mov r2, r1
|
|
800645e: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
}
|
|
8006462: e00e b.n 8006482 <__NVIC_SetPriority+0x50>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8006464: 683b ldr r3, [r7, #0]
|
|
8006466: b2d9 uxtb r1, r3
|
|
8006468: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
800646c: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8006470: 79fa ldrb r2, [r7, #7]
|
|
8006472: f002 020f and.w r2, r2, #15
|
|
8006476: 3a04 subs r2, #4
|
|
8006478: 0109 lsls r1, r1, #4
|
|
800647a: b2c9 uxtb r1, r1
|
|
800647c: 4413 add r3, r2
|
|
800647e: 460a mov r2, r1
|
|
8006480: 761a strb r2, [r3, #24]
|
|
}
|
|
8006482: bf00 nop
|
|
8006484: 370c adds r7, #12
|
|
8006486: 46bd mov sp, r7
|
|
8006488: f85d 7b04 ldr.w r7, [sp], #4
|
|
800648c: 4770 bx lr
|
|
|
|
0800648e <NVIC_EncodePriority>:
|
|
{
|
|
800648e: b480 push {r7}
|
|
8006490: b089 sub sp, #36 ; 0x24
|
|
8006492: af00 add r7, sp, #0
|
|
8006494: 60f8 str r0, [r7, #12]
|
|
8006496: 60b9 str r1, [r7, #8]
|
|
8006498: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
800649a: 68fb ldr r3, [r7, #12]
|
|
800649c: f003 0307 and.w r3, r3, #7
|
|
80064a0: 61fb str r3, [r7, #28]
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80064a2: 69fb ldr r3, [r7, #28]
|
|
80064a4: f1c3 0307 rsb r3, r3, #7
|
|
80064a8: 2b04 cmp r3, #4
|
|
80064aa: bf28 it cs
|
|
80064ac: 2304 movcs r3, #4
|
|
80064ae: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80064b0: 69fb ldr r3, [r7, #28]
|
|
80064b2: 3304 adds r3, #4
|
|
80064b4: 2b06 cmp r3, #6
|
|
80064b6: d902 bls.n 80064be <NVIC_EncodePriority+0x30>
|
|
80064b8: 69fb ldr r3, [r7, #28]
|
|
80064ba: 3b03 subs r3, #3
|
|
80064bc: e000 b.n 80064c0 <NVIC_EncodePriority+0x32>
|
|
80064be: 2300 movs r3, #0
|
|
80064c0: 617b str r3, [r7, #20]
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80064c2: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
80064c6: 69bb ldr r3, [r7, #24]
|
|
80064c8: fa02 f303 lsl.w r3, r2, r3
|
|
80064cc: 43da mvns r2, r3
|
|
80064ce: 68bb ldr r3, [r7, #8]
|
|
80064d0: 401a ands r2, r3
|
|
80064d2: 697b ldr r3, [r7, #20]
|
|
80064d4: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80064d6: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
|
|
80064da: 697b ldr r3, [r7, #20]
|
|
80064dc: fa01 f303 lsl.w r3, r1, r3
|
|
80064e0: 43d9 mvns r1, r3
|
|
80064e2: 687b ldr r3, [r7, #4]
|
|
80064e4: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80064e6: 4313 orrs r3, r2
|
|
}
|
|
80064e8: 4618 mov r0, r3
|
|
80064ea: 3724 adds r7, #36 ; 0x24
|
|
80064ec: 46bd mov sp, r7
|
|
80064ee: f85d 7b04 ldr.w r7, [sp], #4
|
|
80064f2: 4770 bx lr
|
|
|
|
080064f4 <SysTick_Config>:
|
|
{
|
|
80064f4: b580 push {r7, lr}
|
|
80064f6: b082 sub sp, #8
|
|
80064f8: af00 add r7, sp, #0
|
|
80064fa: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
80064fc: 687b ldr r3, [r7, #4]
|
|
80064fe: 3b01 subs r3, #1
|
|
8006500: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
8006504: d301 bcc.n 800650a <SysTick_Config+0x16>
|
|
return (1UL); /* Reload value impossible */
|
|
8006506: 2301 movs r3, #1
|
|
8006508: e018 b.n 800653c <SysTick_Config+0x48>
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
800650a: f24e 0310 movw r3, #57360 ; 0xe010
|
|
800650e: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8006512: 687a ldr r2, [r7, #4]
|
|
8006514: 3a01 subs r2, #1
|
|
8006516: 605a str r2, [r3, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8006518: 210f movs r1, #15
|
|
800651a: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800651e: f7ff ff88 bl 8006432 <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8006522: f24e 0310 movw r3, #57360 ; 0xe010
|
|
8006526: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
800652a: 2200 movs r2, #0
|
|
800652c: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
800652e: f24e 0310 movw r3, #57360 ; 0xe010
|
|
8006532: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8006536: 2207 movs r2, #7
|
|
8006538: 601a str r2, [r3, #0]
|
|
return (0UL); /* Function successful */
|
|
800653a: 2300 movs r3, #0
|
|
}
|
|
800653c: 4618 mov r0, r3
|
|
800653e: 3708 adds r7, #8
|
|
8006540: 46bd mov sp, r7
|
|
8006542: bd80 pop {r7, pc}
|
|
|
|
08006544 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8006544: b580 push {r7, lr}
|
|
8006546: b082 sub sp, #8
|
|
8006548: af00 add r7, sp, #0
|
|
800654a: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
800654c: 6878 ldr r0, [r7, #4]
|
|
800654e: f7ff ff1b bl 8006388 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8006552: bf00 nop
|
|
8006554: 3708 adds r7, #8
|
|
8006556: 46bd mov sp, r7
|
|
8006558: bd80 pop {r7, pc}
|
|
|
|
0800655a <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
800655a: b580 push {r7, lr}
|
|
800655c: b086 sub sp, #24
|
|
800655e: af00 add r7, sp, #0
|
|
8006560: 4603 mov r3, r0
|
|
8006562: 60b9 str r1, [r7, #8]
|
|
8006564: 607a str r2, [r7, #4]
|
|
8006566: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8006568: 2300 movs r3, #0
|
|
800656a: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
800656c: f7ff ff34 bl 80063d8 <__NVIC_GetPriorityGrouping>
|
|
8006570: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8006572: 687a ldr r2, [r7, #4]
|
|
8006574: 68b9 ldr r1, [r7, #8]
|
|
8006576: 6978 ldr r0, [r7, #20]
|
|
8006578: f7ff ff89 bl 800648e <NVIC_EncodePriority>
|
|
800657c: 4602 mov r2, r0
|
|
800657e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8006582: 4611 mov r1, r2
|
|
8006584: 4618 mov r0, r3
|
|
8006586: f7ff ff54 bl 8006432 <__NVIC_SetPriority>
|
|
}
|
|
800658a: bf00 nop
|
|
800658c: 3718 adds r7, #24
|
|
800658e: 46bd mov sp, r7
|
|
8006590: bd80 pop {r7, pc}
|
|
|
|
08006592 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8006592: b580 push {r7, lr}
|
|
8006594: b082 sub sp, #8
|
|
8006596: af00 add r7, sp, #0
|
|
8006598: 4603 mov r3, r0
|
|
800659a: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
800659c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80065a0: 4618 mov r0, r3
|
|
80065a2: f7ff ff28 bl 80063f6 <__NVIC_EnableIRQ>
|
|
}
|
|
80065a6: bf00 nop
|
|
80065a8: 3708 adds r7, #8
|
|
80065aa: 46bd mov sp, r7
|
|
80065ac: bd80 pop {r7, pc}
|
|
|
|
080065ae <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
80065ae: b580 push {r7, lr}
|
|
80065b0: b082 sub sp, #8
|
|
80065b2: af00 add r7, sp, #0
|
|
80065b4: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
80065b6: 6878 ldr r0, [r7, #4]
|
|
80065b8: f7ff ff9c bl 80064f4 <SysTick_Config>
|
|
80065bc: 4603 mov r3, r0
|
|
}
|
|
80065be: 4618 mov r0, r3
|
|
80065c0: 3708 adds r7, #8
|
|
80065c2: 46bd mov sp, r7
|
|
80065c4: bd80 pop {r7, pc}
|
|
|
|
080065c6 <HAL_DMA_Abort>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80065c6: b480 push {r7}
|
|
80065c8: b085 sub sp, #20
|
|
80065ca: af00 add r7, sp, #0
|
|
80065cc: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80065ce: 2300 movs r3, #0
|
|
80065d0: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the DMA peripheral state */
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
80065d2: 687b ldr r3, [r7, #4]
|
|
80065d4: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
|
|
80065d8: b2db uxtb r3, r3
|
|
80065da: 2b02 cmp r3, #2
|
|
80065dc: d008 beq.n 80065f0 <HAL_DMA_Abort+0x2a>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
80065de: 687b ldr r3, [r7, #4]
|
|
80065e0: 2204 movs r2, #4
|
|
80065e2: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80065e4: 687b ldr r3, [r7, #4]
|
|
80065e6: 2200 movs r2, #0
|
|
80065e8: f883 2024 strb.w r2, [r3, #36] ; 0x24
|
|
|
|
return HAL_ERROR;
|
|
80065ec: 2301 movs r3, #1
|
|
80065ee: e022 b.n 8006636 <HAL_DMA_Abort+0x70>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
80065f0: 687b ldr r3, [r7, #4]
|
|
80065f2: 681b ldr r3, [r3, #0]
|
|
80065f4: 681a ldr r2, [r3, #0]
|
|
80065f6: 687b ldr r3, [r7, #4]
|
|
80065f8: 681b ldr r3, [r3, #0]
|
|
80065fa: f022 020e bic.w r2, r2, #14
|
|
80065fe: 601a str r2, [r3, #0]
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8006600: 687b ldr r3, [r7, #4]
|
|
8006602: 681b ldr r3, [r3, #0]
|
|
8006604: 681a ldr r2, [r3, #0]
|
|
8006606: 687b ldr r3, [r7, #4]
|
|
8006608: 681b ldr r3, [r3, #0]
|
|
800660a: f022 0201 bic.w r2, r2, #1
|
|
800660e: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8006610: 687b ldr r3, [r7, #4]
|
|
8006612: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8006614: f003 021c and.w r2, r3, #28
|
|
8006618: 687b ldr r3, [r7, #4]
|
|
800661a: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800661c: 2101 movs r1, #1
|
|
800661e: fa01 f202 lsl.w r2, r1, r2
|
|
8006622: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8006624: 687b ldr r3, [r7, #4]
|
|
8006626: 2201 movs r2, #1
|
|
8006628: f883 2025 strb.w r2, [r3, #37] ; 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
800662c: 687b ldr r3, [r7, #4]
|
|
800662e: 2200 movs r2, #0
|
|
8006630: f883 2024 strb.w r2, [r3, #36] ; 0x24
|
|
|
|
return status;
|
|
8006634: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
}
|
|
8006636: 4618 mov r0, r3
|
|
8006638: 3714 adds r7, #20
|
|
800663a: 46bd mov sp, r7
|
|
800663c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006640: 4770 bx lr
|
|
|
|
08006642 <HAL_DMA_Abort_IT>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006642: b580 push {r7, lr}
|
|
8006644: b084 sub sp, #16
|
|
8006646: af00 add r7, sp, #0
|
|
8006648: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800664a: 2300 movs r3, #0
|
|
800664c: 73fb strb r3, [r7, #15]
|
|
|
|
if(HAL_DMA_STATE_BUSY != hdma->State)
|
|
800664e: 687b ldr r3, [r7, #4]
|
|
8006650: f893 3025 ldrb.w r3, [r3, #37] ; 0x25
|
|
8006654: b2db uxtb r3, r3
|
|
8006656: 2b02 cmp r3, #2
|
|
8006658: d005 beq.n 8006666 <HAL_DMA_Abort_IT+0x24>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
800665a: 687b ldr r3, [r7, #4]
|
|
800665c: 2204 movs r2, #4
|
|
800665e: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
status = HAL_ERROR;
|
|
8006660: 2301 movs r3, #1
|
|
8006662: 73fb strb r3, [r7, #15]
|
|
8006664: e029 b.n 80066ba <HAL_DMA_Abort_IT+0x78>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8006666: 687b ldr r3, [r7, #4]
|
|
8006668: 681b ldr r3, [r3, #0]
|
|
800666a: 681a ldr r2, [r3, #0]
|
|
800666c: 687b ldr r3, [r7, #4]
|
|
800666e: 681b ldr r3, [r3, #0]
|
|
8006670: f022 020e bic.w r2, r2, #14
|
|
8006674: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8006676: 687b ldr r3, [r7, #4]
|
|
8006678: 681b ldr r3, [r3, #0]
|
|
800667a: 681a ldr r2, [r3, #0]
|
|
800667c: 687b ldr r3, [r7, #4]
|
|
800667e: 681b ldr r3, [r3, #0]
|
|
8006680: f022 0201 bic.w r2, r2, #1
|
|
8006684: 601a str r2, [r3, #0]
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
}
|
|
|
|
#else
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8006686: 687b ldr r3, [r7, #4]
|
|
8006688: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800668a: f003 021c and.w r2, r3, #28
|
|
800668e: 687b ldr r3, [r7, #4]
|
|
8006690: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8006692: 2101 movs r1, #1
|
|
8006694: fa01 f202 lsl.w r2, r1, r2
|
|
8006698: 605a str r2, [r3, #4]
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800669a: 687b ldr r3, [r7, #4]
|
|
800669c: 2201 movs r2, #1
|
|
800669e: f883 2025 strb.w r2, [r3, #37] ; 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80066a2: 687b ldr r3, [r7, #4]
|
|
80066a4: 2200 movs r2, #0
|
|
80066a6: f883 2024 strb.w r2, [r3, #36] ; 0x24
|
|
|
|
/* Call User Abort callback */
|
|
if(hdma->XferAbortCallback != NULL)
|
|
80066aa: 687b ldr r3, [r7, #4]
|
|
80066ac: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
80066ae: 2b00 cmp r3, #0
|
|
80066b0: d003 beq.n 80066ba <HAL_DMA_Abort_IT+0x78>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
80066b2: 687b ldr r3, [r7, #4]
|
|
80066b4: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
80066b6: 6878 ldr r0, [r7, #4]
|
|
80066b8: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
80066ba: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80066bc: 4618 mov r0, r3
|
|
80066be: 3710 adds r7, #16
|
|
80066c0: 46bd mov sp, r7
|
|
80066c2: bd80 pop {r7, pc}
|
|
|
|
080066c4 <HAL_FLASH_Program>:
|
|
* are stored the data for the row fast program
|
|
*
|
|
* @retval HAL_StatusTypeDef HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
|
{
|
|
80066c4: b580 push {r7, lr}
|
|
80066c6: b086 sub sp, #24
|
|
80066c8: af00 add r7, sp, #0
|
|
80066ca: 60f8 str r0, [r7, #12]
|
|
80066cc: 60b9 str r1, [r7, #8]
|
|
80066ce: e9c7 2300 strd r2, r3, [r7]
|
|
HAL_StatusTypeDef status;
|
|
uint32_t prog_bit = 0;
|
|
80066d2: 2300 movs r3, #0
|
|
80066d4: 613b str r3, [r7, #16]
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(&pFlash);
|
|
80066d6: f240 2358 movw r3, #600 ; 0x258
|
|
80066da: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80066de: 781b ldrb r3, [r3, #0]
|
|
80066e0: 2b01 cmp r3, #1
|
|
80066e2: d101 bne.n 80066e8 <HAL_FLASH_Program+0x24>
|
|
80066e4: 2302 movs r3, #2
|
|
80066e6: e071 b.n 80067cc <HAL_FLASH_Program+0x108>
|
|
80066e8: f240 2358 movw r3, #600 ; 0x258
|
|
80066ec: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80066f0: 2201 movs r2, #1
|
|
80066f2: 701a strb r2, [r3, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
80066f4: f24c 3050 movw r0, #50000 ; 0xc350
|
|
80066f8: f000 f8ae bl 8006858 <FLASH_WaitForLastOperation>
|
|
80066fc: 4603 mov r3, r0
|
|
80066fe: 75fb strb r3, [r7, #23]
|
|
|
|
if(status == HAL_OK)
|
|
8006700: 7dfb ldrb r3, [r7, #23]
|
|
8006702: 2b00 cmp r3, #0
|
|
8006704: d15b bne.n 80067be <HAL_FLASH_Program+0xfa>
|
|
{
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|
8006706: f240 2358 movw r3, #600 ; 0x258
|
|
800670a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800670e: 2200 movs r2, #0
|
|
8006710: 605a str r2, [r3, #4]
|
|
|
|
/* Deactivate the data cache if they are activated to avoid data misbehavior */
|
|
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
|
|
8006712: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006716: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800671a: 681b ldr r3, [r3, #0]
|
|
800671c: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8006720: 2b00 cmp r3, #0
|
|
8006722: d012 beq.n 800674a <HAL_FLASH_Program+0x86>
|
|
{
|
|
/* Disable data cache */
|
|
__HAL_FLASH_DATA_CACHE_DISABLE();
|
|
8006724: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006728: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800672c: 681a ldr r2, [r3, #0]
|
|
800672e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006732: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006736: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
800673a: 601a str r2, [r3, #0]
|
|
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
|
|
800673c: f240 2358 movw r3, #600 ; 0x258
|
|
8006740: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006744: 2202 movs r2, #2
|
|
8006746: 771a strb r2, [r3, #28]
|
|
8006748: e005 b.n 8006756 <HAL_FLASH_Program+0x92>
|
|
}
|
|
else
|
|
{
|
|
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
|
|
800674a: f240 2358 movw r3, #600 ; 0x258
|
|
800674e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006752: 2200 movs r2, #0
|
|
8006754: 771a strb r2, [r3, #28]
|
|
}
|
|
|
|
if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
|
|
8006756: 68fb ldr r3, [r7, #12]
|
|
8006758: 2b00 cmp r3, #0
|
|
800675a: d107 bne.n 800676c <HAL_FLASH_Program+0xa8>
|
|
{
|
|
/* Program double-word (64-bit) at a specified address */
|
|
FLASH_Program_DoubleWord(Address, Data);
|
|
800675c: e9d7 2300 ldrd r2, r3, [r7]
|
|
8006760: 68b8 ldr r0, [r7, #8]
|
|
8006762: f000 f8e6 bl 8006932 <FLASH_Program_DoubleWord>
|
|
prog_bit = FLASH_CR_PG;
|
|
8006766: 2301 movs r3, #1
|
|
8006768: 613b str r3, [r7, #16]
|
|
800676a: e010 b.n 800678e <HAL_FLASH_Program+0xca>
|
|
}
|
|
else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
|
|
800676c: 68fb ldr r3, [r7, #12]
|
|
800676e: 2b01 cmp r3, #1
|
|
8006770: d002 beq.n 8006778 <HAL_FLASH_Program+0xb4>
|
|
8006772: 68fb ldr r3, [r7, #12]
|
|
8006774: 2b02 cmp r3, #2
|
|
8006776: d10a bne.n 800678e <HAL_FLASH_Program+0xca>
|
|
{
|
|
/* Fast program a 32 row double-word (64-bit) at a specified address */
|
|
FLASH_Program_Fast(Address, (uint32_t)Data);
|
|
8006778: 683b ldr r3, [r7, #0]
|
|
800677a: 4619 mov r1, r3
|
|
800677c: 68b8 ldr r0, [r7, #8]
|
|
800677e: f000 f902 bl 8006986 <FLASH_Program_Fast>
|
|
|
|
/* If it is the last row, the bit will be cleared at the end of the operation */
|
|
if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
|
|
8006782: 68fb ldr r3, [r7, #12]
|
|
8006784: 2b02 cmp r3, #2
|
|
8006786: d102 bne.n 800678e <HAL_FLASH_Program+0xca>
|
|
{
|
|
prog_bit = FLASH_CR_FSTPG;
|
|
8006788: f44f 2380 mov.w r3, #262144 ; 0x40000
|
|
800678c: 613b str r3, [r7, #16]
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
800678e: f24c 3050 movw r0, #50000 ; 0xc350
|
|
8006792: f000 f861 bl 8006858 <FLASH_WaitForLastOperation>
|
|
8006796: 4603 mov r3, r0
|
|
8006798: 75fb strb r3, [r7, #23]
|
|
|
|
/* If the program operation is completed, disable the PG or FSTPG Bit */
|
|
if (prog_bit != 0U)
|
|
800679a: 693b ldr r3, [r7, #16]
|
|
800679c: 2b00 cmp r3, #0
|
|
800679e: d00c beq.n 80067ba <HAL_FLASH_Program+0xf6>
|
|
{
|
|
CLEAR_BIT(FLASH->CR, prog_bit);
|
|
80067a0: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80067a4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80067a8: 6959 ldr r1, [r3, #20]
|
|
80067aa: 693b ldr r3, [r7, #16]
|
|
80067ac: 43da mvns r2, r3
|
|
80067ae: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80067b2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80067b6: 400a ands r2, r1
|
|
80067b8: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Flush the caches to be sure of the data consistency */
|
|
FLASH_FlushCaches();
|
|
80067ba: f000 fa85 bl 8006cc8 <FLASH_FlushCaches>
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(&pFlash);
|
|
80067be: f240 2358 movw r3, #600 ; 0x258
|
|
80067c2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80067c6: 2200 movs r2, #0
|
|
80067c8: 701a strb r2, [r3, #0]
|
|
|
|
return status;
|
|
80067ca: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80067cc: 4618 mov r0, r3
|
|
80067ce: 3718 adds r7, #24
|
|
80067d0: 46bd mov sp, r7
|
|
80067d2: bd80 pop {r7, pc}
|
|
|
|
080067d4 <HAL_FLASH_Unlock>:
|
|
/**
|
|
* @brief Unlock the FLASH control register access.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
|
{
|
|
80067d4: b480 push {r7}
|
|
80067d6: b083 sub sp, #12
|
|
80067d8: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80067da: 2300 movs r3, #0
|
|
80067dc: 71fb strb r3, [r7, #7]
|
|
|
|
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
|
|
80067de: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80067e2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80067e6: 695b ldr r3, [r3, #20]
|
|
80067e8: 2b00 cmp r3, #0
|
|
80067ea: da1a bge.n 8006822 <HAL_FLASH_Unlock+0x4e>
|
|
{
|
|
/* Authorize the FLASH Registers access */
|
|
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
|
80067ec: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80067f0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80067f4: f240 1223 movw r2, #291 ; 0x123
|
|
80067f8: f2c4 5267 movt r2, #17767 ; 0x4567
|
|
80067fc: 609a str r2, [r3, #8]
|
|
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
|
80067fe: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006802: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006806: f648 12ab movw r2, #35243 ; 0x89ab
|
|
800680a: f6cc 52ef movt r2, #52719 ; 0xcdef
|
|
800680e: 609a str r2, [r3, #8]
|
|
|
|
/* Verify Flash is unlocked */
|
|
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
|
|
8006810: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006814: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006818: 695b ldr r3, [r3, #20]
|
|
800681a: 2b00 cmp r3, #0
|
|
800681c: da01 bge.n 8006822 <HAL_FLASH_Unlock+0x4e>
|
|
{
|
|
status = HAL_ERROR;
|
|
800681e: 2301 movs r3, #1
|
|
8006820: 71fb strb r3, [r7, #7]
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8006822: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
8006824: 4618 mov r0, r3
|
|
8006826: 370c adds r7, #12
|
|
8006828: 46bd mov sp, r7
|
|
800682a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800682e: 4770 bx lr
|
|
|
|
08006830 <HAL_FLASH_Lock>:
|
|
/**
|
|
* @brief Lock the FLASH control register access.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
|
{
|
|
8006830: b480 push {r7}
|
|
8006832: af00 add r7, sp, #0
|
|
/* Set the LOCK Bit to lock the FLASH Registers access */
|
|
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
|
8006834: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006838: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800683c: 695a ldr r2, [r3, #20]
|
|
800683e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006842: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006846: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
|
|
800684a: 615a str r2, [r3, #20]
|
|
|
|
return HAL_OK;
|
|
800684c: 2300 movs r3, #0
|
|
}
|
|
800684e: 4618 mov r0, r3
|
|
8006850: 46bd mov sp, r7
|
|
8006852: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006856: 4770 bx lr
|
|
|
|
08006858 <FLASH_WaitForLastOperation>:
|
|
* @brief Wait for a FLASH operation to complete.
|
|
* @param Timeout maximum flash operation timeout
|
|
* @retval HAL_StatusTypeDef HAL Status
|
|
*/
|
|
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
|
{
|
|
8006858: b580 push {r7, lr}
|
|
800685a: b084 sub sp, #16
|
|
800685c: af00 add r7, sp, #0
|
|
800685e: 6078 str r0, [r7, #4]
|
|
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
|
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
|
flag will be set */
|
|
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8006860: f7fe f8d3 bl 8004a0a <HAL_GetTick>
|
|
8006864: 60f8 str r0, [r7, #12]
|
|
uint32_t error;
|
|
|
|
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
|
8006866: e00d b.n 8006884 <FLASH_WaitForLastOperation+0x2c>
|
|
{
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
8006868: 687b ldr r3, [r7, #4]
|
|
800686a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
|
|
800686e: d009 beq.n 8006884 <FLASH_WaitForLastOperation+0x2c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) >= Timeout)
|
|
8006870: f7fe f8cb bl 8004a0a <HAL_GetTick>
|
|
8006874: 4602 mov r2, r0
|
|
8006876: 68fb ldr r3, [r7, #12]
|
|
8006878: 1ad3 subs r3, r2, r3
|
|
800687a: 687a ldr r2, [r7, #4]
|
|
800687c: 429a cmp r2, r3
|
|
800687e: d801 bhi.n 8006884 <FLASH_WaitForLastOperation+0x2c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006880: 2303 movs r3, #3
|
|
8006882: e052 b.n 800692a <FLASH_WaitForLastOperation+0xd2>
|
|
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
|
8006884: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006888: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800688c: 691b ldr r3, [r3, #16]
|
|
800688e: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8006892: 2b00 cmp r3, #0
|
|
8006894: d1e8 bne.n 8006868 <FLASH_WaitForLastOperation+0x10>
|
|
}
|
|
}
|
|
}
|
|
|
|
error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
|
|
8006896: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
800689a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800689e: 691a ldr r2, [r3, #16]
|
|
80068a0: f24c 33fa movw r3, #50170 ; 0xc3fa
|
|
80068a4: 4013 ands r3, r2
|
|
80068a6: 60bb str r3, [r7, #8]
|
|
|
|
if(error != 0u)
|
|
80068a8: 68bb ldr r3, [r7, #8]
|
|
80068aa: 2b00 cmp r3, #0
|
|
80068ac: d02d beq.n 800690a <FLASH_WaitForLastOperation+0xb2>
|
|
{
|
|
/*Save the error code*/
|
|
pFlash.ErrorCode |= error;
|
|
80068ae: f240 2358 movw r3, #600 ; 0x258
|
|
80068b2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80068b6: 685a ldr r2, [r3, #4]
|
|
80068b8: 68bb ldr r3, [r7, #8]
|
|
80068ba: 431a orrs r2, r3
|
|
80068bc: f240 2358 movw r3, #600 ; 0x258
|
|
80068c0: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
80068c4: 605a str r2, [r3, #4]
|
|
|
|
/* Clear error programming flags */
|
|
__HAL_FLASH_CLEAR_FLAG(error);
|
|
80068c6: 68bb ldr r3, [r7, #8]
|
|
80068c8: f003 4340 and.w r3, r3, #3221225472 ; 0xc0000000
|
|
80068cc: 2b00 cmp r3, #0
|
|
80068ce: d00d beq.n 80068ec <FLASH_WaitForLastOperation+0x94>
|
|
80068d0: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80068d4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80068d8: 6999 ldr r1, [r3, #24]
|
|
80068da: 68bb ldr r3, [r7, #8]
|
|
80068dc: f003 4240 and.w r2, r3, #3221225472 ; 0xc0000000
|
|
80068e0: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80068e4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80068e8: 430a orrs r2, r1
|
|
80068ea: 619a str r2, [r3, #24]
|
|
80068ec: 68bb ldr r3, [r7, #8]
|
|
80068ee: f023 4340 bic.w r3, r3, #3221225472 ; 0xc0000000
|
|
80068f2: 2b00 cmp r3, #0
|
|
80068f4: d007 beq.n 8006906 <FLASH_WaitForLastOperation+0xae>
|
|
80068f6: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80068fa: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80068fe: 68ba ldr r2, [r7, #8]
|
|
8006900: f022 4240 bic.w r2, r2, #3221225472 ; 0xc0000000
|
|
8006904: 611a str r2, [r3, #16]
|
|
|
|
return HAL_ERROR;
|
|
8006906: 2301 movs r3, #1
|
|
8006908: e00f b.n 800692a <FLASH_WaitForLastOperation+0xd2>
|
|
}
|
|
|
|
/* Check FLASH End of Operation flag */
|
|
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
|
800690a: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
800690e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006912: 691b ldr r3, [r3, #16]
|
|
8006914: f003 0301 and.w r3, r3, #1
|
|
8006918: 2b00 cmp r3, #0
|
|
800691a: d005 beq.n 8006928 <FLASH_WaitForLastOperation+0xd0>
|
|
{
|
|
/* Clear FLASH End of Operation pending bit */
|
|
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
|
800691c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006920: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006924: 2201 movs r2, #1
|
|
8006926: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* If there is an error flag set */
|
|
return HAL_OK;
|
|
8006928: 2300 movs r3, #0
|
|
}
|
|
800692a: 4618 mov r0, r3
|
|
800692c: 3710 adds r7, #16
|
|
800692e: 46bd mov sp, r7
|
|
8006930: bd80 pop {r7, pc}
|
|
|
|
08006932 <FLASH_Program_DoubleWord>:
|
|
* @param Address specifies the address to be programmed.
|
|
* @param Data specifies the data to be programmed.
|
|
* @retval None
|
|
*/
|
|
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
|
{
|
|
8006932: b480 push {r7}
|
|
8006934: b085 sub sp, #20
|
|
8006936: af00 add r7, sp, #0
|
|
8006938: 60f8 str r0, [r7, #12]
|
|
800693a: e9c7 2300 strd r2, r3, [r7]
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
|
|
|
/* Set PG bit */
|
|
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
|
800693e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006942: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006946: 695a ldr r2, [r3, #20]
|
|
8006948: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
800694c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006950: f042 0201 orr.w r2, r2, #1
|
|
8006954: 615a str r2, [r3, #20]
|
|
|
|
/* Program first word */
|
|
*(__IO uint32_t*)Address = (uint32_t)Data;
|
|
8006956: 68fb ldr r3, [r7, #12]
|
|
8006958: 683a ldr r2, [r7, #0]
|
|
800695a: 601a str r2, [r3, #0]
|
|
__ASM volatile ("isb 0xF":::"memory");
|
|
800695c: f3bf 8f6f isb sy
|
|
}
|
|
8006960: bf00 nop
|
|
/* Barrier to ensure programming is performed in 2 steps, in right order
|
|
(independently of compiler optimization behavior) */
|
|
__ISB();
|
|
|
|
/* Program second word */
|
|
*(__IO uint32_t*)(Address+4U) = (uint32_t)(Data >> 32);
|
|
8006962: e9d7 0100 ldrd r0, r1, [r7]
|
|
8006966: f04f 0200 mov.w r2, #0
|
|
800696a: f04f 0300 mov.w r3, #0
|
|
800696e: 000a movs r2, r1
|
|
8006970: 2300 movs r3, #0
|
|
8006972: 68f9 ldr r1, [r7, #12]
|
|
8006974: 3104 adds r1, #4
|
|
8006976: 4613 mov r3, r2
|
|
8006978: 600b str r3, [r1, #0]
|
|
}
|
|
800697a: bf00 nop
|
|
800697c: 3714 adds r7, #20
|
|
800697e: 46bd mov sp, r7
|
|
8006980: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006984: 4770 bx lr
|
|
|
|
08006986 <FLASH_Program_Fast>:
|
|
* @param Address specifies the address to be programmed.
|
|
* @param DataAddress specifies the address where the data are stored.
|
|
* @retval None
|
|
*/
|
|
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
|
|
{
|
|
8006986: b480 push {r7}
|
|
8006988: b089 sub sp, #36 ; 0x24
|
|
800698a: af00 add r7, sp, #0
|
|
800698c: 6078 str r0, [r7, #4]
|
|
800698e: 6039 str r1, [r7, #0]
|
|
uint32_t primask_bit;
|
|
uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW);
|
|
8006990: 2340 movs r3, #64 ; 0x40
|
|
8006992: 77fb strb r3, [r7, #31]
|
|
__IO uint32_t *dest_addr = (__IO uint32_t*)Address;
|
|
8006994: 687b ldr r3, [r7, #4]
|
|
8006996: 61bb str r3, [r7, #24]
|
|
__IO uint32_t *src_addr = (__IO uint32_t*)DataAddress;
|
|
8006998: 683b ldr r3, [r7, #0]
|
|
800699a: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
|
|
|
|
/* Set FSTPG bit */
|
|
SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
|
|
800699c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80069a0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80069a4: 695a ldr r2, [r3, #20]
|
|
80069a6: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80069aa: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80069ae: f442 2280 orr.w r2, r2, #262144 ; 0x40000
|
|
80069b2: 615a str r2, [r3, #20]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
|
|
80069b4: f3ef 8310 mrs r3, PRIMASK
|
|
80069b8: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
80069ba: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Disable interrupts to avoid any interruption during the loop */
|
|
primask_bit = __get_PRIMASK();
|
|
80069bc: 613b str r3, [r7, #16]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80069be: b672 cpsid i
|
|
}
|
|
80069c0: bf00 nop
|
|
__disable_irq();
|
|
|
|
/* Program the double word of the row */
|
|
do
|
|
{
|
|
*dest_addr = *src_addr;
|
|
80069c2: 697b ldr r3, [r7, #20]
|
|
80069c4: 681a ldr r2, [r3, #0]
|
|
80069c6: 69bb ldr r3, [r7, #24]
|
|
80069c8: 601a str r2, [r3, #0]
|
|
dest_addr++;
|
|
80069ca: 69bb ldr r3, [r7, #24]
|
|
80069cc: 3304 adds r3, #4
|
|
80069ce: 61bb str r3, [r7, #24]
|
|
src_addr++;
|
|
80069d0: 697b ldr r3, [r7, #20]
|
|
80069d2: 3304 adds r3, #4
|
|
80069d4: 617b str r3, [r7, #20]
|
|
row_index--;
|
|
80069d6: 7ffb ldrb r3, [r7, #31]
|
|
80069d8: 3b01 subs r3, #1
|
|
80069da: 77fb strb r3, [r7, #31]
|
|
} while (row_index != 0U);
|
|
80069dc: 7ffb ldrb r3, [r7, #31]
|
|
80069de: 2b00 cmp r3, #0
|
|
80069e0: d1ef bne.n 80069c2 <FLASH_Program_Fast+0x3c>
|
|
80069e2: 693b ldr r3, [r7, #16]
|
|
80069e4: 60bb str r3, [r7, #8]
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80069e6: 68bb ldr r3, [r7, #8]
|
|
80069e8: f383 8810 msr PRIMASK, r3
|
|
}
|
|
80069ec: bf00 nop
|
|
|
|
/* Re-enable the interrupts */
|
|
__set_PRIMASK(primask_bit);
|
|
}
|
|
80069ee: bf00 nop
|
|
80069f0: 3724 adds r7, #36 ; 0x24
|
|
80069f2: 46bd mov sp, r7
|
|
80069f4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80069f8: 4770 bx lr
|
|
|
|
080069fa <HAL_FLASHEx_Erase>:
|
|
* the pages have been correctly erased)
|
|
*
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
|
{
|
|
80069fa: b580 push {r7, lr}
|
|
80069fc: b084 sub sp, #16
|
|
80069fe: af00 add r7, sp, #0
|
|
8006a00: 6078 str r0, [r7, #4]
|
|
8006a02: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status;
|
|
uint32_t page_index;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(&pFlash);
|
|
8006a04: f240 2358 movw r3, #600 ; 0x258
|
|
8006a08: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006a0c: 781b ldrb r3, [r3, #0]
|
|
8006a0e: 2b01 cmp r3, #1
|
|
8006a10: d101 bne.n 8006a16 <HAL_FLASHEx_Erase+0x1c>
|
|
8006a12: 2302 movs r3, #2
|
|
8006a14: e0ca b.n 8006bac <HAL_FLASHEx_Erase+0x1b2>
|
|
8006a16: f240 2358 movw r3, #600 ; 0x258
|
|
8006a1a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006a1e: 2201 movs r2, #1
|
|
8006a20: 701a strb r2, [r3, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
8006a22: f24c 3050 movw r0, #50000 ; 0xc350
|
|
8006a26: f7ff ff17 bl 8006858 <FLASH_WaitForLastOperation>
|
|
8006a2a: 4603 mov r3, r0
|
|
8006a2c: 73fb strb r3, [r7, #15]
|
|
|
|
if (status == HAL_OK)
|
|
8006a2e: 7bfb ldrb r3, [r7, #15]
|
|
8006a30: 2b00 cmp r3, #0
|
|
8006a32: f040 80b4 bne.w 8006b9e <HAL_FLASHEx_Erase+0x1a4>
|
|
{
|
|
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
|
8006a36: f240 2358 movw r3, #600 ; 0x258
|
|
8006a3a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006a3e: 2200 movs r2, #0
|
|
8006a40: 605a str r2, [r3, #4]
|
|
|
|
/* Deactivate the cache if they are activated to avoid data misbehavior */
|
|
if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
|
|
8006a42: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006a46: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006a4a: 681b ldr r3, [r3, #0]
|
|
8006a4c: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
8006a50: 2b00 cmp r3, #0
|
|
8006a52: d02e beq.n 8006ab2 <HAL_FLASHEx_Erase+0xb8>
|
|
{
|
|
/* Disable instruction cache */
|
|
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
|
|
8006a54: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006a58: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006a5c: 681a ldr r2, [r3, #0]
|
|
8006a5e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006a62: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006a66: f422 7200 bic.w r2, r2, #512 ; 0x200
|
|
8006a6a: 601a str r2, [r3, #0]
|
|
|
|
if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
|
|
8006a6c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006a70: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006a74: 681b ldr r3, [r3, #0]
|
|
8006a76: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8006a7a: 2b00 cmp r3, #0
|
|
8006a7c: d012 beq.n 8006aa4 <HAL_FLASHEx_Erase+0xaa>
|
|
{
|
|
/* Disable data cache */
|
|
__HAL_FLASH_DATA_CACHE_DISABLE();
|
|
8006a7e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006a82: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006a86: 681a ldr r2, [r3, #0]
|
|
8006a88: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006a8c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006a90: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
8006a94: 601a str r2, [r3, #0]
|
|
pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
|
|
8006a96: f240 2358 movw r3, #600 ; 0x258
|
|
8006a9a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006a9e: 2203 movs r2, #3
|
|
8006aa0: 771a strb r2, [r3, #28]
|
|
8006aa2: e028 b.n 8006af6 <HAL_FLASHEx_Erase+0xfc>
|
|
}
|
|
else
|
|
{
|
|
pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
|
|
8006aa4: f240 2358 movw r3, #600 ; 0x258
|
|
8006aa8: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006aac: 2201 movs r2, #1
|
|
8006aae: 771a strb r2, [r3, #28]
|
|
8006ab0: e021 b.n 8006af6 <HAL_FLASHEx_Erase+0xfc>
|
|
}
|
|
}
|
|
else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
|
|
8006ab2: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006ab6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006aba: 681b ldr r3, [r3, #0]
|
|
8006abc: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8006ac0: 2b00 cmp r3, #0
|
|
8006ac2: d012 beq.n 8006aea <HAL_FLASHEx_Erase+0xf0>
|
|
{
|
|
/* Disable data cache */
|
|
__HAL_FLASH_DATA_CACHE_DISABLE();
|
|
8006ac4: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006ac8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006acc: 681a ldr r2, [r3, #0]
|
|
8006ace: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006ad2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006ad6: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
8006ada: 601a str r2, [r3, #0]
|
|
pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
|
|
8006adc: f240 2358 movw r3, #600 ; 0x258
|
|
8006ae0: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006ae4: 2202 movs r2, #2
|
|
8006ae6: 771a strb r2, [r3, #28]
|
|
8006ae8: e005 b.n 8006af6 <HAL_FLASHEx_Erase+0xfc>
|
|
}
|
|
else
|
|
{
|
|
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
|
|
8006aea: f240 2358 movw r3, #600 ; 0x258
|
|
8006aee: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006af2: 2200 movs r2, #0
|
|
8006af4: 771a strb r2, [r3, #28]
|
|
}
|
|
|
|
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
|
|
8006af6: 687b ldr r3, [r7, #4]
|
|
8006af8: 681b ldr r3, [r3, #0]
|
|
8006afa: 2b01 cmp r3, #1
|
|
8006afc: d119 bne.n 8006b32 <HAL_FLASHEx_Erase+0x138>
|
|
{
|
|
/* Mass erase to be done */
|
|
FLASH_MassErase(pEraseInit->Banks);
|
|
8006afe: 687b ldr r3, [r7, #4]
|
|
8006b00: 685b ldr r3, [r3, #4]
|
|
8006b02: 4618 mov r0, r3
|
|
8006b04: f000 f856 bl 8006bb4 <FLASH_MassErase>
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
8006b08: f24c 3050 movw r0, #50000 ; 0xc350
|
|
8006b0c: f7ff fea4 bl 8006858 <FLASH_WaitForLastOperation>
|
|
8006b10: 4603 mov r3, r0
|
|
8006b12: 73fb strb r3, [r7, #15]
|
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
|
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \
|
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
|
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
|
|
/* If the erase operation is completed, disable the MER1 and MER2 Bits */
|
|
CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
|
|
8006b14: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006b18: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006b1c: 695b ldr r3, [r3, #20]
|
|
8006b1e: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
8006b22: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
8006b26: f423 4300 bic.w r3, r3, #32768 ; 0x8000
|
|
8006b2a: f023 0304 bic.w r3, r3, #4
|
|
8006b2e: 6153 str r3, [r2, #20]
|
|
8006b30: e033 b.n 8006b9a <HAL_FLASHEx_Erase+0x1a0>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/*Initialization of PageError variable*/
|
|
*PageError = 0xFFFFFFFFU;
|
|
8006b32: 683b ldr r3, [r7, #0]
|
|
8006b34: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
8006b38: 601a str r2, [r3, #0]
|
|
|
|
for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
|
|
8006b3a: 687b ldr r3, [r7, #4]
|
|
8006b3c: 689b ldr r3, [r3, #8]
|
|
8006b3e: 60bb str r3, [r7, #8]
|
|
8006b40: e023 b.n 8006b8a <HAL_FLASHEx_Erase+0x190>
|
|
{
|
|
FLASH_PageErase(page_index, pEraseInit->Banks);
|
|
8006b42: 687b ldr r3, [r7, #4]
|
|
8006b44: 685b ldr r3, [r3, #4]
|
|
8006b46: 4619 mov r1, r3
|
|
8006b48: 68b8 ldr r0, [r7, #8]
|
|
8006b4a: f000 f86b bl 8006c24 <FLASH_PageErase>
|
|
|
|
/* Wait for last operation to be completed */
|
|
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
|
8006b4e: f24c 3050 movw r0, #50000 ; 0xc350
|
|
8006b52: f7ff fe81 bl 8006858 <FLASH_WaitForLastOperation>
|
|
8006b56: 4603 mov r3, r0
|
|
8006b58: 73fb strb r3, [r7, #15]
|
|
|
|
/* If the erase operation is completed, disable the PER Bit */
|
|
CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
|
|
8006b5a: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006b5e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006b62: 695b ldr r3, [r3, #20]
|
|
8006b64: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
8006b68: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
8006b6c: f423 63ff bic.w r3, r3, #2040 ; 0x7f8
|
|
8006b70: f023 0302 bic.w r3, r3, #2
|
|
8006b74: 6153 str r3, [r2, #20]
|
|
|
|
if (status != HAL_OK)
|
|
8006b76: 7bfb ldrb r3, [r7, #15]
|
|
8006b78: 2b00 cmp r3, #0
|
|
8006b7a: d003 beq.n 8006b84 <HAL_FLASHEx_Erase+0x18a>
|
|
{
|
|
/* In case of error, stop erase procedure and return the faulty address */
|
|
*PageError = page_index;
|
|
8006b7c: 683b ldr r3, [r7, #0]
|
|
8006b7e: 68ba ldr r2, [r7, #8]
|
|
8006b80: 601a str r2, [r3, #0]
|
|
break;
|
|
8006b82: e00a b.n 8006b9a <HAL_FLASHEx_Erase+0x1a0>
|
|
for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
|
|
8006b84: 68bb ldr r3, [r7, #8]
|
|
8006b86: 3301 adds r3, #1
|
|
8006b88: 60bb str r3, [r7, #8]
|
|
8006b8a: 687b ldr r3, [r7, #4]
|
|
8006b8c: 689a ldr r2, [r3, #8]
|
|
8006b8e: 687b ldr r3, [r7, #4]
|
|
8006b90: 68db ldr r3, [r3, #12]
|
|
8006b92: 4413 add r3, r2
|
|
8006b94: 68ba ldr r2, [r7, #8]
|
|
8006b96: 429a cmp r2, r3
|
|
8006b98: d3d3 bcc.n 8006b42 <HAL_FLASHEx_Erase+0x148>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Flush the caches to be sure of the data consistency */
|
|
FLASH_FlushCaches();
|
|
8006b9a: f000 f895 bl 8006cc8 <FLASH_FlushCaches>
|
|
}
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(&pFlash);
|
|
8006b9e: f240 2358 movw r3, #600 ; 0x258
|
|
8006ba2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006ba6: 2200 movs r2, #0
|
|
8006ba8: 701a strb r2, [r3, #0]
|
|
|
|
return status;
|
|
8006baa: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006bac: 4618 mov r0, r3
|
|
8006bae: 3710 adds r7, #16
|
|
8006bb0: 46bd mov sp, r7
|
|
8006bb2: bd80 pop {r7, pc}
|
|
|
|
08006bb4 <FLASH_MassErase>:
|
|
* @arg FLASH_BANK_2: Bank2 to be erased
|
|
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
|
|
* @retval None
|
|
*/
|
|
static void FLASH_MassErase(uint32_t Banks)
|
|
{
|
|
8006bb4: b480 push {r7}
|
|
8006bb6: b083 sub sp, #12
|
|
8006bb8: af00 add r7, sp, #0
|
|
8006bba: 6078 str r0, [r7, #4]
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_FLASH_BANK(Banks));
|
|
|
|
/* Set the Mass Erase Bit for the bank 1 if requested */
|
|
if((Banks & FLASH_BANK_1) != 0U)
|
|
8006bbc: 687b ldr r3, [r7, #4]
|
|
8006bbe: f003 0301 and.w r3, r3, #1
|
|
8006bc2: 2b00 cmp r3, #0
|
|
8006bc4: d00b beq.n 8006bde <FLASH_MassErase+0x2a>
|
|
{
|
|
SET_BIT(FLASH->CR, FLASH_CR_MER1);
|
|
8006bc6: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006bca: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006bce: 695a ldr r2, [r3, #20]
|
|
8006bd0: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006bd4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006bd8: f042 0204 orr.w r2, r2, #4
|
|
8006bdc: 615a str r2, [r3, #20]
|
|
#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
|
|
defined (STM32L496xx) || defined (STM32L4A6xx) || \
|
|
defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
|
|
defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
|
|
/* Set the Mass Erase Bit for the bank 2 if requested */
|
|
if((Banks & FLASH_BANK_2) != 0U)
|
|
8006bde: 687b ldr r3, [r7, #4]
|
|
8006be0: f003 0302 and.w r3, r3, #2
|
|
8006be4: 2b00 cmp r3, #0
|
|
8006be6: d00b beq.n 8006c00 <FLASH_MassErase+0x4c>
|
|
{
|
|
SET_BIT(FLASH->CR, FLASH_CR_MER2);
|
|
8006be8: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006bec: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006bf0: 695a ldr r2, [r3, #20]
|
|
8006bf2: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006bf6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006bfa: f442 4200 orr.w r2, r2, #32768 ; 0x8000
|
|
8006bfe: 615a str r2, [r3, #20]
|
|
SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
|
|
}
|
|
#endif
|
|
|
|
/* Proceed to erase all sectors */
|
|
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
|
8006c00: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c04: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c08: 695a ldr r2, [r3, #20]
|
|
8006c0a: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c0e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c12: f442 3280 orr.w r2, r2, #65536 ; 0x10000
|
|
8006c16: 615a str r2, [r3, #20]
|
|
}
|
|
8006c18: bf00 nop
|
|
8006c1a: 370c adds r7, #12
|
|
8006c1c: 46bd mov sp, r7
|
|
8006c1e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006c22: 4770 bx lr
|
|
|
|
08006c24 <FLASH_PageErase>:
|
|
* @arg FLASH_BANK_1: Page in bank 1 to be erased
|
|
* @arg FLASH_BANK_2: Page in bank 2 to be erased
|
|
* @retval None
|
|
*/
|
|
void FLASH_PageErase(uint32_t Page, uint32_t Banks)
|
|
{
|
|
8006c24: b480 push {r7}
|
|
8006c26: b083 sub sp, #12
|
|
8006c28: af00 add r7, sp, #0
|
|
8006c2a: 6078 str r0, [r7, #4]
|
|
8006c2c: 6039 str r1, [r7, #0]
|
|
else
|
|
#endif
|
|
{
|
|
assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
|
|
|
|
if((Banks & FLASH_BANK_1) != 0U)
|
|
8006c2e: 683b ldr r3, [r7, #0]
|
|
8006c30: f003 0301 and.w r3, r3, #1
|
|
8006c34: 2b00 cmp r3, #0
|
|
8006c36: d00c beq.n 8006c52 <FLASH_PageErase+0x2e>
|
|
{
|
|
CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
|
|
8006c38: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c3c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c40: 695a ldr r2, [r3, #20]
|
|
8006c42: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c46: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c4a: f422 6200 bic.w r2, r2, #2048 ; 0x800
|
|
8006c4e: 615a str r2, [r3, #20]
|
|
8006c50: e00b b.n 8006c6a <FLASH_PageErase+0x46>
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(FLASH->CR, FLASH_CR_BKER);
|
|
8006c52: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c56: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c5a: 695a ldr r2, [r3, #20]
|
|
8006c5c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c60: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c64: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
8006c68: 615a str r2, [r3, #20]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(Banks);
|
|
#endif
|
|
|
|
/* Proceed to erase the page */
|
|
MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
|
|
8006c6a: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c6e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c72: 695b ldr r3, [r3, #20]
|
|
8006c74: f423 61ff bic.w r1, r3, #2040 ; 0x7f8
|
|
8006c78: 687b ldr r3, [r7, #4]
|
|
8006c7a: 00db lsls r3, r3, #3
|
|
8006c7c: f403 62ff and.w r2, r3, #2040 ; 0x7f8
|
|
8006c80: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c84: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c88: 430a orrs r2, r1
|
|
8006c8a: 615a str r2, [r3, #20]
|
|
SET_BIT(FLASH->CR, FLASH_CR_PER);
|
|
8006c8c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c90: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c94: 695a ldr r2, [r3, #20]
|
|
8006c96: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006c9a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006c9e: f042 0202 orr.w r2, r2, #2
|
|
8006ca2: 615a str r2, [r3, #20]
|
|
SET_BIT(FLASH->CR, FLASH_CR_STRT);
|
|
8006ca4: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006ca8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006cac: 695a ldr r2, [r3, #20]
|
|
8006cae: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006cb2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006cb6: f442 3280 orr.w r2, r2, #65536 ; 0x10000
|
|
8006cba: 615a str r2, [r3, #20]
|
|
}
|
|
8006cbc: bf00 nop
|
|
8006cbe: 370c adds r7, #12
|
|
8006cc0: 46bd mov sp, r7
|
|
8006cc2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006cc6: 4770 bx lr
|
|
|
|
08006cc8 <FLASH_FlushCaches>:
|
|
/**
|
|
* @brief Flush the instruction and data caches.
|
|
* @retval None
|
|
*/
|
|
void FLASH_FlushCaches(void)
|
|
{
|
|
8006cc8: b480 push {r7}
|
|
8006cca: b083 sub sp, #12
|
|
8006ccc: af00 add r7, sp, #0
|
|
FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
|
|
8006cce: f240 2358 movw r3, #600 ; 0x258
|
|
8006cd2: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006cd6: 7f1b ldrb r3, [r3, #28]
|
|
8006cd8: 71fb strb r3, [r7, #7]
|
|
|
|
/* Flush instruction cache */
|
|
if((cache == FLASH_CACHE_ICACHE_ENABLED) ||
|
|
8006cda: 79fb ldrb r3, [r7, #7]
|
|
8006cdc: 2b01 cmp r3, #1
|
|
8006cde: d002 beq.n 8006ce6 <FLASH_FlushCaches+0x1e>
|
|
8006ce0: 79fb ldrb r3, [r7, #7]
|
|
8006ce2: 2b03 cmp r3, #3
|
|
8006ce4: d123 bne.n 8006d2e <FLASH_FlushCaches+0x66>
|
|
(cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
|
|
{
|
|
/* Reset instruction cache */
|
|
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
|
|
8006ce6: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006cea: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006cee: 681a ldr r2, [r3, #0]
|
|
8006cf0: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006cf4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006cf8: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
8006cfc: 601a str r2, [r3, #0]
|
|
8006cfe: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d02: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d06: 681a ldr r2, [r3, #0]
|
|
8006d08: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d0c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d10: f422 6200 bic.w r2, r2, #2048 ; 0x800
|
|
8006d14: 601a str r2, [r3, #0]
|
|
/* Enable instruction cache */
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
8006d16: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d1a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d1e: 681a ldr r2, [r3, #0]
|
|
8006d20: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d24: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d28: f442 7200 orr.w r2, r2, #512 ; 0x200
|
|
8006d2c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Flush data cache */
|
|
if((cache == FLASH_CACHE_DCACHE_ENABLED) ||
|
|
8006d2e: 79fb ldrb r3, [r7, #7]
|
|
8006d30: 2b02 cmp r3, #2
|
|
8006d32: d002 beq.n 8006d3a <FLASH_FlushCaches+0x72>
|
|
8006d34: 79fb ldrb r3, [r7, #7]
|
|
8006d36: 2b03 cmp r3, #3
|
|
8006d38: d123 bne.n 8006d82 <FLASH_FlushCaches+0xba>
|
|
(cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
|
|
{
|
|
/* Reset data cache */
|
|
__HAL_FLASH_DATA_CACHE_RESET();
|
|
8006d3a: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d3e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d42: 681a ldr r2, [r3, #0]
|
|
8006d44: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d48: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d4c: f442 5280 orr.w r2, r2, #4096 ; 0x1000
|
|
8006d50: 601a str r2, [r3, #0]
|
|
8006d52: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d56: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d5a: 681a ldr r2, [r3, #0]
|
|
8006d5c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d60: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d64: f422 5280 bic.w r2, r2, #4096 ; 0x1000
|
|
8006d68: 601a str r2, [r3, #0]
|
|
/* Enable data cache */
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
8006d6a: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d6e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d72: 681a ldr r2, [r3, #0]
|
|
8006d74: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8006d78: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006d7c: f442 6280 orr.w r2, r2, #1024 ; 0x400
|
|
8006d80: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Reset internal variable */
|
|
pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
|
|
8006d82: f240 2358 movw r3, #600 ; 0x258
|
|
8006d86: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8006d8a: 2200 movs r2, #0
|
|
8006d8c: 771a strb r2, [r3, #28]
|
|
}
|
|
8006d8e: bf00 nop
|
|
8006d90: 370c adds r7, #12
|
|
8006d92: 46bd mov sp, r7
|
|
8006d94: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d98: 4770 bx lr
|
|
|
|
08006d9a <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8006d9a: b480 push {r7}
|
|
8006d9c: b087 sub sp, #28
|
|
8006d9e: af00 add r7, sp, #0
|
|
8006da0: 6078 str r0, [r7, #4]
|
|
8006da2: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
8006da4: 2300 movs r3, #0
|
|
8006da6: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8006da8: e1b6 b.n 8007118 <HAL_GPIO_Init+0x37e>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
8006daa: 683b ldr r3, [r7, #0]
|
|
8006dac: 681a ldr r2, [r3, #0]
|
|
8006dae: 2101 movs r1, #1
|
|
8006db0: 697b ldr r3, [r7, #20]
|
|
8006db2: fa01 f303 lsl.w r3, r1, r3
|
|
8006db6: 4013 ands r3, r2
|
|
8006db8: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
8006dba: 68fb ldr r3, [r7, #12]
|
|
8006dbc: 2b00 cmp r3, #0
|
|
8006dbe: f000 81a8 beq.w 8007112 <HAL_GPIO_Init+0x378>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8006dc2: 683b ldr r3, [r7, #0]
|
|
8006dc4: 685b ldr r3, [r3, #4]
|
|
8006dc6: 2b01 cmp r3, #1
|
|
8006dc8: d00b beq.n 8006de2 <HAL_GPIO_Init+0x48>
|
|
8006dca: 683b ldr r3, [r7, #0]
|
|
8006dcc: 685b ldr r3, [r3, #4]
|
|
8006dce: 2b02 cmp r3, #2
|
|
8006dd0: d007 beq.n 8006de2 <HAL_GPIO_Init+0x48>
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8006dd2: 683b ldr r3, [r7, #0]
|
|
8006dd4: 685b ldr r3, [r3, #4]
|
|
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8006dd6: 2b11 cmp r3, #17
|
|
8006dd8: d003 beq.n 8006de2 <HAL_GPIO_Init+0x48>
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8006dda: 683b ldr r3, [r7, #0]
|
|
8006ddc: 685b ldr r3, [r3, #4]
|
|
8006dde: 2b12 cmp r3, #18
|
|
8006de0: d130 bne.n 8006e44 <HAL_GPIO_Init+0xaa>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8006de2: 687b ldr r3, [r7, #4]
|
|
8006de4: 689b ldr r3, [r3, #8]
|
|
8006de6: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
8006de8: 697b ldr r3, [r7, #20]
|
|
8006dea: 005b lsls r3, r3, #1
|
|
8006dec: 2203 movs r2, #3
|
|
8006dee: fa02 f303 lsl.w r3, r2, r3
|
|
8006df2: 43db mvns r3, r3
|
|
8006df4: 693a ldr r2, [r7, #16]
|
|
8006df6: 4013 ands r3, r2
|
|
8006df8: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
8006dfa: 683b ldr r3, [r7, #0]
|
|
8006dfc: 68da ldr r2, [r3, #12]
|
|
8006dfe: 697b ldr r3, [r7, #20]
|
|
8006e00: 005b lsls r3, r3, #1
|
|
8006e02: fa02 f303 lsl.w r3, r2, r3
|
|
8006e06: 693a ldr r2, [r7, #16]
|
|
8006e08: 4313 orrs r3, r2
|
|
8006e0a: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8006e0c: 687b ldr r3, [r7, #4]
|
|
8006e0e: 693a ldr r2, [r7, #16]
|
|
8006e10: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8006e12: 687b ldr r3, [r7, #4]
|
|
8006e14: 685b ldr r3, [r3, #4]
|
|
8006e16: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8006e18: 2201 movs r2, #1
|
|
8006e1a: 697b ldr r3, [r7, #20]
|
|
8006e1c: fa02 f303 lsl.w r3, r2, r3
|
|
8006e20: 43db mvns r3, r3
|
|
8006e22: 693a ldr r2, [r7, #16]
|
|
8006e24: 4013 ands r3, r2
|
|
8006e26: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
|
|
8006e28: 683b ldr r3, [r7, #0]
|
|
8006e2a: 685b ldr r3, [r3, #4]
|
|
8006e2c: 091b lsrs r3, r3, #4
|
|
8006e2e: f003 0201 and.w r2, r3, #1
|
|
8006e32: 697b ldr r3, [r7, #20]
|
|
8006e34: fa02 f303 lsl.w r3, r2, r3
|
|
8006e38: 693a ldr r2, [r7, #16]
|
|
8006e3a: 4313 orrs r3, r2
|
|
8006e3c: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8006e3e: 687b ldr r3, [r7, #4]
|
|
8006e40: 693a ldr r2, [r7, #16]
|
|
8006e42: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
|
/* In case of Analog mode, check if ADC control mode is selected */
|
|
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
|
|
8006e44: 683b ldr r3, [r7, #0]
|
|
8006e46: 685b ldr r3, [r3, #4]
|
|
8006e48: f003 0303 and.w r3, r3, #3
|
|
8006e4c: 2b03 cmp r3, #3
|
|
8006e4e: d118 bne.n 8006e82 <HAL_GPIO_Init+0xe8>
|
|
{
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->ASCR;
|
|
8006e50: 687b ldr r3, [r7, #4]
|
|
8006e52: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e54: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_ASCR_ASC0 << position) ;
|
|
8006e56: 2201 movs r2, #1
|
|
8006e58: 697b ldr r3, [r7, #20]
|
|
8006e5a: fa02 f303 lsl.w r3, r2, r3
|
|
8006e5e: 43db mvns r3, r3
|
|
8006e60: 693a ldr r2, [r7, #16]
|
|
8006e62: 4013 ands r3, r2
|
|
8006e64: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);
|
|
8006e66: 683b ldr r3, [r7, #0]
|
|
8006e68: 685b ldr r3, [r3, #4]
|
|
8006e6a: 08db lsrs r3, r3, #3
|
|
8006e6c: f003 0201 and.w r2, r3, #1
|
|
8006e70: 697b ldr r3, [r7, #20]
|
|
8006e72: fa02 f303 lsl.w r3, r2, r3
|
|
8006e76: 693a ldr r2, [r7, #16]
|
|
8006e78: 4313 orrs r3, r2
|
|
8006e7a: 613b str r3, [r7, #16]
|
|
GPIOx->ASCR = temp;
|
|
8006e7c: 687b ldr r3, [r7, #4]
|
|
8006e7e: 693a ldr r2, [r7, #16]
|
|
8006e80: 62da str r2, [r3, #44] ; 0x2c
|
|
}
|
|
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8006e82: 687b ldr r3, [r7, #4]
|
|
8006e84: 68db ldr r3, [r3, #12]
|
|
8006e86: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
|
8006e88: 697b ldr r3, [r7, #20]
|
|
8006e8a: 005b lsls r3, r3, #1
|
|
8006e8c: 2203 movs r2, #3
|
|
8006e8e: fa02 f303 lsl.w r3, r2, r3
|
|
8006e92: 43db mvns r3, r3
|
|
8006e94: 693a ldr r2, [r7, #16]
|
|
8006e96: 4013 ands r3, r2
|
|
8006e98: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
|
8006e9a: 683b ldr r3, [r7, #0]
|
|
8006e9c: 689a ldr r2, [r3, #8]
|
|
8006e9e: 697b ldr r3, [r7, #20]
|
|
8006ea0: 005b lsls r3, r3, #1
|
|
8006ea2: fa02 f303 lsl.w r3, r2, r3
|
|
8006ea6: 693a ldr r2, [r7, #16]
|
|
8006ea8: 4313 orrs r3, r2
|
|
8006eaa: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
8006eac: 687b ldr r3, [r7, #4]
|
|
8006eae: 693a ldr r2, [r7, #16]
|
|
8006eb0: 60da str r2, [r3, #12]
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8006eb2: 683b ldr r3, [r7, #0]
|
|
8006eb4: 685b ldr r3, [r3, #4]
|
|
8006eb6: 2b02 cmp r3, #2
|
|
8006eb8: d003 beq.n 8006ec2 <HAL_GPIO_Init+0x128>
|
|
8006eba: 683b ldr r3, [r7, #0]
|
|
8006ebc: 685b ldr r3, [r3, #4]
|
|
8006ebe: 2b12 cmp r3, #18
|
|
8006ec0: d123 bne.n 8006f0a <HAL_GPIO_Init+0x170>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8006ec2: 697b ldr r3, [r7, #20]
|
|
8006ec4: 08da lsrs r2, r3, #3
|
|
8006ec6: 687b ldr r3, [r7, #4]
|
|
8006ec8: 3208 adds r2, #8
|
|
8006eca: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006ece: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8006ed0: 697b ldr r3, [r7, #20]
|
|
8006ed2: f003 0307 and.w r3, r3, #7
|
|
8006ed6: 009b lsls r3, r3, #2
|
|
8006ed8: 220f movs r2, #15
|
|
8006eda: fa02 f303 lsl.w r3, r2, r3
|
|
8006ede: 43db mvns r3, r3
|
|
8006ee0: 693a ldr r2, [r7, #16]
|
|
8006ee2: 4013 ands r3, r2
|
|
8006ee4: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
8006ee6: 683b ldr r3, [r7, #0]
|
|
8006ee8: 691a ldr r2, [r3, #16]
|
|
8006eea: 697b ldr r3, [r7, #20]
|
|
8006eec: f003 0307 and.w r3, r3, #7
|
|
8006ef0: 009b lsls r3, r3, #2
|
|
8006ef2: fa02 f303 lsl.w r3, r2, r3
|
|
8006ef6: 693a ldr r2, [r7, #16]
|
|
8006ef8: 4313 orrs r3, r2
|
|
8006efa: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
8006efc: 697b ldr r3, [r7, #20]
|
|
8006efe: 08da lsrs r2, r3, #3
|
|
8006f00: 687b ldr r3, [r7, #4]
|
|
8006f02: 3208 adds r2, #8
|
|
8006f04: 6939 ldr r1, [r7, #16]
|
|
8006f06: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8006f0a: 687b ldr r3, [r7, #4]
|
|
8006f0c: 681b ldr r3, [r3, #0]
|
|
8006f0e: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
8006f10: 697b ldr r3, [r7, #20]
|
|
8006f12: 005b lsls r3, r3, #1
|
|
8006f14: 2203 movs r2, #3
|
|
8006f16: fa02 f303 lsl.w r3, r2, r3
|
|
8006f1a: 43db mvns r3, r3
|
|
8006f1c: 693a ldr r2, [r7, #16]
|
|
8006f1e: 4013 ands r3, r2
|
|
8006f20: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
8006f22: 683b ldr r3, [r7, #0]
|
|
8006f24: 685b ldr r3, [r3, #4]
|
|
8006f26: f003 0203 and.w r2, r3, #3
|
|
8006f2a: 697b ldr r3, [r7, #20]
|
|
8006f2c: 005b lsls r3, r3, #1
|
|
8006f2e: fa02 f303 lsl.w r3, r2, r3
|
|
8006f32: 693a ldr r2, [r7, #16]
|
|
8006f34: 4313 orrs r3, r2
|
|
8006f36: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
8006f38: 687b ldr r3, [r7, #4]
|
|
8006f3a: 693a ldr r2, [r7, #16]
|
|
8006f3c: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
8006f3e: 683b ldr r3, [r7, #0]
|
|
8006f40: 685b ldr r3, [r3, #4]
|
|
8006f42: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8006f46: 2b00 cmp r3, #0
|
|
8006f48: f000 80e3 beq.w 8007112 <HAL_GPIO_Init+0x378>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8006f4c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8006f50: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006f54: 6e1a ldr r2, [r3, #96] ; 0x60
|
|
8006f56: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8006f5a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006f5e: f042 0201 orr.w r2, r2, #1
|
|
8006f62: 661a str r2, [r3, #96] ; 0x60
|
|
8006f64: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8006f68: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8006f6c: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
8006f6e: f003 0301 and.w r3, r3, #1
|
|
8006f72: 60bb str r3, [r7, #8]
|
|
8006f74: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
8006f76: 2300 movs r3, #0
|
|
8006f78: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8006f7c: 697a ldr r2, [r7, #20]
|
|
8006f7e: 0892 lsrs r2, r2, #2
|
|
8006f80: 3202 adds r2, #2
|
|
8006f82: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8006f86: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
8006f88: 697b ldr r3, [r7, #20]
|
|
8006f8a: f003 0303 and.w r3, r3, #3
|
|
8006f8e: 009b lsls r3, r3, #2
|
|
8006f90: 220f movs r2, #15
|
|
8006f92: fa02 f303 lsl.w r3, r2, r3
|
|
8006f96: 43db mvns r3, r3
|
|
8006f98: 693a ldr r2, [r7, #16]
|
|
8006f9a: 4013 ands r3, r2
|
|
8006f9c: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
8006f9e: 687b ldr r3, [r7, #4]
|
|
8006fa0: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
|
|
8006fa4: d037 beq.n 8007016 <HAL_GPIO_Init+0x27c>
|
|
8006fa6: 687a ldr r2, [r7, #4]
|
|
8006fa8: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8006fac: f6c4 0300 movt r3, #18432 ; 0x4800
|
|
8006fb0: 429a cmp r2, r3
|
|
8006fb2: d02e beq.n 8007012 <HAL_GPIO_Init+0x278>
|
|
8006fb4: 687a ldr r2, [r7, #4]
|
|
8006fb6: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
8006fba: f6c4 0300 movt r3, #18432 ; 0x4800
|
|
8006fbe: 429a cmp r2, r3
|
|
8006fc0: d025 beq.n 800700e <HAL_GPIO_Init+0x274>
|
|
8006fc2: 687a ldr r2, [r7, #4]
|
|
8006fc4: f44f 6340 mov.w r3, #3072 ; 0xc00
|
|
8006fc8: f6c4 0300 movt r3, #18432 ; 0x4800
|
|
8006fcc: 429a cmp r2, r3
|
|
8006fce: d01c beq.n 800700a <HAL_GPIO_Init+0x270>
|
|
8006fd0: 687a ldr r2, [r7, #4]
|
|
8006fd2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8006fd6: f6c4 0300 movt r3, #18432 ; 0x4800
|
|
8006fda: 429a cmp r2, r3
|
|
8006fdc: d013 beq.n 8007006 <HAL_GPIO_Init+0x26c>
|
|
8006fde: 687a ldr r2, [r7, #4]
|
|
8006fe0: f44f 53a0 mov.w r3, #5120 ; 0x1400
|
|
8006fe4: f6c4 0300 movt r3, #18432 ; 0x4800
|
|
8006fe8: 429a cmp r2, r3
|
|
8006fea: d00a beq.n 8007002 <HAL_GPIO_Init+0x268>
|
|
8006fec: 687a ldr r2, [r7, #4]
|
|
8006fee: f44f 53c0 mov.w r3, #6144 ; 0x1800
|
|
8006ff2: f6c4 0300 movt r3, #18432 ; 0x4800
|
|
8006ff6: 429a cmp r2, r3
|
|
8006ff8: d101 bne.n 8006ffe <HAL_GPIO_Init+0x264>
|
|
8006ffa: 2306 movs r3, #6
|
|
8006ffc: e00c b.n 8007018 <HAL_GPIO_Init+0x27e>
|
|
8006ffe: 2307 movs r3, #7
|
|
8007000: e00a b.n 8007018 <HAL_GPIO_Init+0x27e>
|
|
8007002: 2305 movs r3, #5
|
|
8007004: e008 b.n 8007018 <HAL_GPIO_Init+0x27e>
|
|
8007006: 2304 movs r3, #4
|
|
8007008: e006 b.n 8007018 <HAL_GPIO_Init+0x27e>
|
|
800700a: 2303 movs r3, #3
|
|
800700c: e004 b.n 8007018 <HAL_GPIO_Init+0x27e>
|
|
800700e: 2302 movs r3, #2
|
|
8007010: e002 b.n 8007018 <HAL_GPIO_Init+0x27e>
|
|
8007012: 2301 movs r3, #1
|
|
8007014: e000 b.n 8007018 <HAL_GPIO_Init+0x27e>
|
|
8007016: 2300 movs r3, #0
|
|
8007018: 697a ldr r2, [r7, #20]
|
|
800701a: f002 0203 and.w r2, r2, #3
|
|
800701e: 0092 lsls r2, r2, #2
|
|
8007020: 4093 lsls r3, r2
|
|
8007022: 693a ldr r2, [r7, #16]
|
|
8007024: 4313 orrs r3, r2
|
|
8007026: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8007028: 2300 movs r3, #0
|
|
800702a: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
800702e: 697a ldr r2, [r7, #20]
|
|
8007030: 0892 lsrs r2, r2, #2
|
|
8007032: 3202 adds r2, #2
|
|
8007034: 6939 ldr r1, [r7, #16]
|
|
8007036: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR1;
|
|
800703a: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
800703e: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8007042: 681b ldr r3, [r3, #0]
|
|
8007044: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8007046: 68fb ldr r3, [r7, #12]
|
|
8007048: 43db mvns r3, r3
|
|
800704a: 693a ldr r2, [r7, #16]
|
|
800704c: 4013 ands r3, r2
|
|
800704e: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
8007050: 683b ldr r3, [r7, #0]
|
|
8007052: 685b ldr r3, [r3, #4]
|
|
8007054: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8007058: 2b00 cmp r3, #0
|
|
800705a: d003 beq.n 8007064 <HAL_GPIO_Init+0x2ca>
|
|
{
|
|
temp |= iocurrent;
|
|
800705c: 693a ldr r2, [r7, #16]
|
|
800705e: 68fb ldr r3, [r7, #12]
|
|
8007060: 4313 orrs r3, r2
|
|
8007062: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
8007064: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8007068: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
800706c: 693a ldr r2, [r7, #16]
|
|
800706e: 601a str r2, [r3, #0]
|
|
|
|
temp = EXTI->EMR1;
|
|
8007070: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8007074: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8007078: 685b ldr r3, [r3, #4]
|
|
800707a: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
800707c: 68fb ldr r3, [r7, #12]
|
|
800707e: 43db mvns r3, r3
|
|
8007080: 693a ldr r2, [r7, #16]
|
|
8007082: 4013 ands r3, r2
|
|
8007084: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
8007086: 683b ldr r3, [r7, #0]
|
|
8007088: 685b ldr r3, [r3, #4]
|
|
800708a: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
800708e: 2b00 cmp r3, #0
|
|
8007090: d003 beq.n 800709a <HAL_GPIO_Init+0x300>
|
|
{
|
|
temp |= iocurrent;
|
|
8007092: 693a ldr r2, [r7, #16]
|
|
8007094: 68fb ldr r3, [r7, #12]
|
|
8007096: 4313 orrs r3, r2
|
|
8007098: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
800709a: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
800709e: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
80070a2: 693a ldr r2, [r7, #16]
|
|
80070a4: 605a str r2, [r3, #4]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
80070a6: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
80070aa: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
80070ae: 689b ldr r3, [r3, #8]
|
|
80070b0: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80070b2: 68fb ldr r3, [r7, #12]
|
|
80070b4: 43db mvns r3, r3
|
|
80070b6: 693a ldr r2, [r7, #16]
|
|
80070b8: 4013 ands r3, r2
|
|
80070ba: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
80070bc: 683b ldr r3, [r7, #0]
|
|
80070be: 685b ldr r3, [r3, #4]
|
|
80070c0: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
80070c4: 2b00 cmp r3, #0
|
|
80070c6: d003 beq.n 80070d0 <HAL_GPIO_Init+0x336>
|
|
{
|
|
temp |= iocurrent;
|
|
80070c8: 693a ldr r2, [r7, #16]
|
|
80070ca: 68fb ldr r3, [r7, #12]
|
|
80070cc: 4313 orrs r3, r2
|
|
80070ce: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
80070d0: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
80070d4: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
80070d8: 693a ldr r2, [r7, #16]
|
|
80070da: 609a str r2, [r3, #8]
|
|
|
|
temp = EXTI->FTSR1;
|
|
80070dc: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
80070e0: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
80070e4: 68db ldr r3, [r3, #12]
|
|
80070e6: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
80070e8: 68fb ldr r3, [r7, #12]
|
|
80070ea: 43db mvns r3, r3
|
|
80070ec: 693a ldr r2, [r7, #16]
|
|
80070ee: 4013 ands r3, r2
|
|
80070f0: 613b str r3, [r7, #16]
|
|
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
80070f2: 683b ldr r3, [r7, #0]
|
|
80070f4: 685b ldr r3, [r3, #4]
|
|
80070f6: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
80070fa: 2b00 cmp r3, #0
|
|
80070fc: d003 beq.n 8007106 <HAL_GPIO_Init+0x36c>
|
|
{
|
|
temp |= iocurrent;
|
|
80070fe: 693a ldr r2, [r7, #16]
|
|
8007100: 68fb ldr r3, [r7, #12]
|
|
8007102: 4313 orrs r3, r2
|
|
8007104: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8007106: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
800710a: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
800710e: 693a ldr r2, [r7, #16]
|
|
8007110: 60da str r2, [r3, #12]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8007112: 697b ldr r3, [r7, #20]
|
|
8007114: 3301 adds r3, #1
|
|
8007116: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8007118: 683b ldr r3, [r7, #0]
|
|
800711a: 681a ldr r2, [r3, #0]
|
|
800711c: 697b ldr r3, [r7, #20]
|
|
800711e: fa22 f303 lsr.w r3, r2, r3
|
|
8007122: 2b00 cmp r3, #0
|
|
8007124: f47f ae41 bne.w 8006daa <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8007128: bf00 nop
|
|
800712a: bf00 nop
|
|
800712c: 371c adds r7, #28
|
|
800712e: 46bd mov sp, r7
|
|
8007130: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007134: 4770 bx lr
|
|
|
|
08007136 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8007136: b480 push {r7}
|
|
8007138: b083 sub sp, #12
|
|
800713a: af00 add r7, sp, #0
|
|
800713c: 6078 str r0, [r7, #4]
|
|
800713e: 460b mov r3, r1
|
|
8007140: 807b strh r3, [r7, #2]
|
|
8007142: 4613 mov r3, r2
|
|
8007144: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8007146: 787b ldrb r3, [r7, #1]
|
|
8007148: 2b00 cmp r3, #0
|
|
800714a: d003 beq.n 8007154 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
800714c: 887a ldrh r2, [r7, #2]
|
|
800714e: 687b ldr r3, [r7, #4]
|
|
8007150: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8007152: e002 b.n 800715a <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8007154: 887a ldrh r2, [r7, #2]
|
|
8007156: 687b ldr r3, [r7, #4]
|
|
8007158: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
800715a: bf00 nop
|
|
800715c: 370c adds r7, #12
|
|
800715e: 46bd mov sp, r7
|
|
8007160: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007164: 4770 bx lr
|
|
|
|
08007166 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8007166: b580 push {r7, lr}
|
|
8007168: b082 sub sp, #8
|
|
800716a: af00 add r7, sp, #0
|
|
800716c: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
800716e: 687b ldr r3, [r7, #4]
|
|
8007170: 2b00 cmp r3, #0
|
|
8007172: d101 bne.n 8007178 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8007174: 2301 movs r3, #1
|
|
8007176: e081 b.n 800727c <HAL_I2C_Init+0x116>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8007178: 687b ldr r3, [r7, #4]
|
|
800717a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
800717e: b2db uxtb r3, r3
|
|
8007180: 2b00 cmp r3, #0
|
|
8007182: d106 bne.n 8007192 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8007184: 687b ldr r3, [r7, #4]
|
|
8007186: 2200 movs r2, #0
|
|
8007188: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
800718c: 6878 ldr r0, [r7, #4]
|
|
800718e: f7fb fb55 bl 800283c <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8007192: 687b ldr r3, [r7, #4]
|
|
8007194: 2224 movs r2, #36 ; 0x24
|
|
8007196: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
800719a: 687b ldr r3, [r7, #4]
|
|
800719c: 681b ldr r3, [r3, #0]
|
|
800719e: 681a ldr r2, [r3, #0]
|
|
80071a0: 687b ldr r3, [r7, #4]
|
|
80071a2: 681b ldr r3, [r3, #0]
|
|
80071a4: f022 0201 bic.w r2, r2, #1
|
|
80071a8: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
80071aa: 687b ldr r3, [r7, #4]
|
|
80071ac: 685a ldr r2, [r3, #4]
|
|
80071ae: 687b ldr r3, [r7, #4]
|
|
80071b0: 681b ldr r3, [r3, #0]
|
|
80071b2: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
|
|
80071b6: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
80071b8: 687b ldr r3, [r7, #4]
|
|
80071ba: 681b ldr r3, [r3, #0]
|
|
80071bc: 689a ldr r2, [r3, #8]
|
|
80071be: 687b ldr r3, [r7, #4]
|
|
80071c0: 681b ldr r3, [r3, #0]
|
|
80071c2: f422 4200 bic.w r2, r2, #32768 ; 0x8000
|
|
80071c6: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
80071c8: 687b ldr r3, [r7, #4]
|
|
80071ca: 68db ldr r3, [r3, #12]
|
|
80071cc: 2b01 cmp r3, #1
|
|
80071ce: d107 bne.n 80071e0 <HAL_I2C_Init+0x7a>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
80071d0: 687b ldr r3, [r7, #4]
|
|
80071d2: 689a ldr r2, [r3, #8]
|
|
80071d4: 687b ldr r3, [r7, #4]
|
|
80071d6: 681b ldr r3, [r3, #0]
|
|
80071d8: f442 4200 orr.w r2, r2, #32768 ; 0x8000
|
|
80071dc: 609a str r2, [r3, #8]
|
|
80071de: e006 b.n 80071ee <HAL_I2C_Init+0x88>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
80071e0: 687b ldr r3, [r7, #4]
|
|
80071e2: 689a ldr r2, [r3, #8]
|
|
80071e4: 687b ldr r3, [r7, #4]
|
|
80071e6: 681b ldr r3, [r3, #0]
|
|
80071e8: f442 4204 orr.w r2, r2, #33792 ; 0x8400
|
|
80071ec: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
80071ee: 687b ldr r3, [r7, #4]
|
|
80071f0: 68db ldr r3, [r3, #12]
|
|
80071f2: 2b02 cmp r3, #2
|
|
80071f4: d104 bne.n 8007200 <HAL_I2C_Init+0x9a>
|
|
{
|
|
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
|
|
80071f6: 687b ldr r3, [r7, #4]
|
|
80071f8: 681b ldr r3, [r3, #0]
|
|
80071fa: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
80071fe: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
8007200: 687b ldr r3, [r7, #4]
|
|
8007202: 681b ldr r3, [r3, #0]
|
|
8007204: 685b ldr r3, [r3, #4]
|
|
8007206: 687a ldr r2, [r7, #4]
|
|
8007208: 6812 ldr r2, [r2, #0]
|
|
800720a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
|
|
800720e: f443 4300 orr.w r3, r3, #32768 ; 0x8000
|
|
8007212: 6053 str r3, [r2, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
8007214: 687b ldr r3, [r7, #4]
|
|
8007216: 681b ldr r3, [r3, #0]
|
|
8007218: 68da ldr r2, [r3, #12]
|
|
800721a: 687b ldr r3, [r7, #4]
|
|
800721c: 681b ldr r3, [r3, #0]
|
|
800721e: f422 4200 bic.w r2, r2, #32768 ; 0x8000
|
|
8007222: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
|
|
8007224: 687b ldr r3, [r7, #4]
|
|
8007226: 691a ldr r2, [r3, #16]
|
|
8007228: 687b ldr r3, [r7, #4]
|
|
800722a: 695b ldr r3, [r3, #20]
|
|
800722c: ea42 0103 orr.w r1, r2, r3
|
|
8007230: 687b ldr r3, [r7, #4]
|
|
8007232: 699b ldr r3, [r3, #24]
|
|
8007234: 021a lsls r2, r3, #8
|
|
8007236: 687b ldr r3, [r7, #4]
|
|
8007238: 681b ldr r3, [r3, #0]
|
|
800723a: 430a orrs r2, r1
|
|
800723c: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
800723e: 687b ldr r3, [r7, #4]
|
|
8007240: 69d9 ldr r1, [r3, #28]
|
|
8007242: 687b ldr r3, [r7, #4]
|
|
8007244: 6a1a ldr r2, [r3, #32]
|
|
8007246: 687b ldr r3, [r7, #4]
|
|
8007248: 681b ldr r3, [r3, #0]
|
|
800724a: 430a orrs r2, r1
|
|
800724c: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
800724e: 687b ldr r3, [r7, #4]
|
|
8007250: 681b ldr r3, [r3, #0]
|
|
8007252: 681a ldr r2, [r3, #0]
|
|
8007254: 687b ldr r3, [r7, #4]
|
|
8007256: 681b ldr r3, [r3, #0]
|
|
8007258: f042 0201 orr.w r2, r2, #1
|
|
800725c: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
800725e: 687b ldr r3, [r7, #4]
|
|
8007260: 2200 movs r2, #0
|
|
8007262: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007264: 687b ldr r3, [r7, #4]
|
|
8007266: 2220 movs r2, #32
|
|
8007268: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
800726c: 687b ldr r3, [r7, #4]
|
|
800726e: 2200 movs r2, #0
|
|
8007270: 631a str r2, [r3, #48] ; 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8007272: 687b ldr r3, [r7, #4]
|
|
8007274: 2200 movs r2, #0
|
|
8007276: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
return HAL_OK;
|
|
800727a: 2300 movs r3, #0
|
|
}
|
|
800727c: 4618 mov r0, r3
|
|
800727e: 3708 adds r7, #8
|
|
8007280: 46bd mov sp, r7
|
|
8007282: bd80 pop {r7, pc}
|
|
|
|
08007284 <HAL_I2C_Mem_Write>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8007284: b580 push {r7, lr}
|
|
8007286: b088 sub sp, #32
|
|
8007288: af02 add r7, sp, #8
|
|
800728a: 60f8 str r0, [r7, #12]
|
|
800728c: 4608 mov r0, r1
|
|
800728e: 4611 mov r1, r2
|
|
8007290: 461a mov r2, r3
|
|
8007292: 4603 mov r3, r0
|
|
8007294: 817b strh r3, [r7, #10]
|
|
8007296: 460b mov r3, r1
|
|
8007298: 813b strh r3, [r7, #8]
|
|
800729a: 4613 mov r3, r2
|
|
800729c: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
800729e: 68fb ldr r3, [r7, #12]
|
|
80072a0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
80072a4: b2db uxtb r3, r3
|
|
80072a6: 2b20 cmp r3, #32
|
|
80072a8: f040 80fc bne.w 80074a4 <HAL_I2C_Mem_Write+0x220>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80072ac: 6a3b ldr r3, [r7, #32]
|
|
80072ae: 2b00 cmp r3, #0
|
|
80072b0: d002 beq.n 80072b8 <HAL_I2C_Mem_Write+0x34>
|
|
80072b2: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
80072b4: 2b00 cmp r3, #0
|
|
80072b6: d105 bne.n 80072c4 <HAL_I2C_Mem_Write+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
80072b8: 68fb ldr r3, [r7, #12]
|
|
80072ba: f44f 7200 mov.w r2, #512 ; 0x200
|
|
80072be: 645a str r2, [r3, #68] ; 0x44
|
|
return HAL_ERROR;
|
|
80072c0: 2301 movs r3, #1
|
|
80072c2: e0f0 b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80072c4: 68fb ldr r3, [r7, #12]
|
|
80072c6: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
80072ca: 2b01 cmp r3, #1
|
|
80072cc: d101 bne.n 80072d2 <HAL_I2C_Mem_Write+0x4e>
|
|
80072ce: 2302 movs r3, #2
|
|
80072d0: e0e9 b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
80072d2: 68fb ldr r3, [r7, #12]
|
|
80072d4: 2201 movs r2, #1
|
|
80072d6: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
80072da: f7fd fb96 bl 8004a0a <HAL_GetTick>
|
|
80072de: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
80072e0: 697b ldr r3, [r7, #20]
|
|
80072e2: 9300 str r3, [sp, #0]
|
|
80072e4: 2319 movs r3, #25
|
|
80072e6: 2201 movs r2, #1
|
|
80072e8: f44f 4100 mov.w r1, #32768 ; 0x8000
|
|
80072ec: 68f8 ldr r0, [r7, #12]
|
|
80072ee: f000 faca bl 8007886 <I2C_WaitOnFlagUntilTimeout>
|
|
80072f2: 4603 mov r3, r0
|
|
80072f4: 2b00 cmp r3, #0
|
|
80072f6: d001 beq.n 80072fc <HAL_I2C_Mem_Write+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
80072f8: 2301 movs r3, #1
|
|
80072fa: e0d4 b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
80072fc: 68fb ldr r3, [r7, #12]
|
|
80072fe: 2221 movs r2, #33 ; 0x21
|
|
8007300: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8007304: 68fb ldr r3, [r7, #12]
|
|
8007306: 2240 movs r2, #64 ; 0x40
|
|
8007308: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
800730c: 68fb ldr r3, [r7, #12]
|
|
800730e: 2200 movs r2, #0
|
|
8007310: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8007312: 68fb ldr r3, [r7, #12]
|
|
8007314: 6a3a ldr r2, [r7, #32]
|
|
8007316: 625a str r2, [r3, #36] ; 0x24
|
|
hi2c->XferCount = Size;
|
|
8007318: 68fb ldr r3, [r7, #12]
|
|
800731a: 8cba ldrh r2, [r7, #36] ; 0x24
|
|
800731c: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferISR = NULL;
|
|
800731e: 68fb ldr r3, [r7, #12]
|
|
8007320: 2200 movs r2, #0
|
|
8007322: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8007324: 88f8 ldrh r0, [r7, #6]
|
|
8007326: 893a ldrh r2, [r7, #8]
|
|
8007328: 8979 ldrh r1, [r7, #10]
|
|
800732a: 697b ldr r3, [r7, #20]
|
|
800732c: 9301 str r3, [sp, #4]
|
|
800732e: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8007330: 9300 str r3, [sp, #0]
|
|
8007332: 4603 mov r3, r0
|
|
8007334: 68f8 ldr r0, [r7, #12]
|
|
8007336: f000 f9d9 bl 80076ec <I2C_RequestMemoryWrite>
|
|
800733a: 4603 mov r3, r0
|
|
800733c: 2b00 cmp r3, #0
|
|
800733e: d005 beq.n 800734c <HAL_I2C_Mem_Write+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007340: 68fb ldr r3, [r7, #12]
|
|
8007342: 2200 movs r2, #0
|
|
8007344: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
return HAL_ERROR;
|
|
8007348: 2301 movs r3, #1
|
|
800734a: e0ac b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
}
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
800734c: 68fb ldr r3, [r7, #12]
|
|
800734e: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8007350: b29b uxth r3, r3
|
|
8007352: 2bff cmp r3, #255 ; 0xff
|
|
8007354: d90e bls.n 8007374 <HAL_I2C_Mem_Write+0xf0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8007356: 68fb ldr r3, [r7, #12]
|
|
8007358: 22ff movs r2, #255 ; 0xff
|
|
800735a: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
800735c: 68fb ldr r3, [r7, #12]
|
|
800735e: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8007360: b2da uxtb r2, r3
|
|
8007362: 8979 ldrh r1, [r7, #10]
|
|
8007364: 2300 movs r3, #0
|
|
8007366: 9300 str r3, [sp, #0]
|
|
8007368: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
800736c: 68f8 ldr r0, [r7, #12]
|
|
800736e: f000 fbad bl 8007acc <I2C_TransferConfig>
|
|
8007372: e00f b.n 8007394 <HAL_I2C_Mem_Write+0x110>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8007374: 68fb ldr r3, [r7, #12]
|
|
8007376: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8007378: b29a uxth r2, r3
|
|
800737a: 68fb ldr r3, [r7, #12]
|
|
800737c: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
800737e: 68fb ldr r3, [r7, #12]
|
|
8007380: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8007382: b2da uxtb r2, r3
|
|
8007384: 8979 ldrh r1, [r7, #10]
|
|
8007386: 2300 movs r3, #0
|
|
8007388: 9300 str r3, [sp, #0]
|
|
800738a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
800738e: 68f8 ldr r0, [r7, #12]
|
|
8007390: f000 fb9c bl 8007acc <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8007394: 697a ldr r2, [r7, #20]
|
|
8007396: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
8007398: 68f8 ldr r0, [r7, #12]
|
|
800739a: f000 fab4 bl 8007906 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800739e: 4603 mov r3, r0
|
|
80073a0: 2b00 cmp r3, #0
|
|
80073a2: d001 beq.n 80073a8 <HAL_I2C_Mem_Write+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
80073a4: 2301 movs r3, #1
|
|
80073a6: e07e b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
}
|
|
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
80073a8: 68fb ldr r3, [r7, #12]
|
|
80073aa: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80073ac: 781a ldrb r2, [r3, #0]
|
|
80073ae: 68fb ldr r3, [r7, #12]
|
|
80073b0: 681b ldr r3, [r3, #0]
|
|
80073b2: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
80073b4: 68fb ldr r3, [r7, #12]
|
|
80073b6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80073b8: 1c5a adds r2, r3, #1
|
|
80073ba: 68fb ldr r3, [r7, #12]
|
|
80073bc: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hi2c->XferCount--;
|
|
80073be: 68fb ldr r3, [r7, #12]
|
|
80073c0: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80073c2: b29b uxth r3, r3
|
|
80073c4: 3b01 subs r3, #1
|
|
80073c6: b29a uxth r2, r3
|
|
80073c8: 68fb ldr r3, [r7, #12]
|
|
80073ca: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferSize--;
|
|
80073cc: 68fb ldr r3, [r7, #12]
|
|
80073ce: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80073d0: 3b01 subs r3, #1
|
|
80073d2: b29a uxth r2, r3
|
|
80073d4: 68fb ldr r3, [r7, #12]
|
|
80073d6: 851a strh r2, [r3, #40] ; 0x28
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
80073d8: 68fb ldr r3, [r7, #12]
|
|
80073da: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80073dc: b29b uxth r3, r3
|
|
80073de: 2b00 cmp r3, #0
|
|
80073e0: d034 beq.n 800744c <HAL_I2C_Mem_Write+0x1c8>
|
|
80073e2: 68fb ldr r3, [r7, #12]
|
|
80073e4: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80073e6: 2b00 cmp r3, #0
|
|
80073e8: d130 bne.n 800744c <HAL_I2C_Mem_Write+0x1c8>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
80073ea: 697b ldr r3, [r7, #20]
|
|
80073ec: 9300 str r3, [sp, #0]
|
|
80073ee: 6abb ldr r3, [r7, #40] ; 0x28
|
|
80073f0: 2200 movs r2, #0
|
|
80073f2: 2180 movs r1, #128 ; 0x80
|
|
80073f4: 68f8 ldr r0, [r7, #12]
|
|
80073f6: f000 fa46 bl 8007886 <I2C_WaitOnFlagUntilTimeout>
|
|
80073fa: 4603 mov r3, r0
|
|
80073fc: 2b00 cmp r3, #0
|
|
80073fe: d001 beq.n 8007404 <HAL_I2C_Mem_Write+0x180>
|
|
{
|
|
return HAL_ERROR;
|
|
8007400: 2301 movs r3, #1
|
|
8007402: e050 b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8007404: 68fb ldr r3, [r7, #12]
|
|
8007406: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8007408: b29b uxth r3, r3
|
|
800740a: 2bff cmp r3, #255 ; 0xff
|
|
800740c: d90e bls.n 800742c <HAL_I2C_Mem_Write+0x1a8>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
800740e: 68fb ldr r3, [r7, #12]
|
|
8007410: 22ff movs r2, #255 ; 0xff
|
|
8007412: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
8007414: 68fb ldr r3, [r7, #12]
|
|
8007416: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8007418: b2da uxtb r2, r3
|
|
800741a: 8979 ldrh r1, [r7, #10]
|
|
800741c: 2300 movs r3, #0
|
|
800741e: 9300 str r3, [sp, #0]
|
|
8007420: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
8007424: 68f8 ldr r0, [r7, #12]
|
|
8007426: f000 fb51 bl 8007acc <I2C_TransferConfig>
|
|
800742a: e00f b.n 800744c <HAL_I2C_Mem_Write+0x1c8>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
800742c: 68fb ldr r3, [r7, #12]
|
|
800742e: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8007430: b29a uxth r2, r3
|
|
8007432: 68fb ldr r3, [r7, #12]
|
|
8007434: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8007436: 68fb ldr r3, [r7, #12]
|
|
8007438: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
800743a: b2da uxtb r2, r3
|
|
800743c: 8979 ldrh r1, [r7, #10]
|
|
800743e: 2300 movs r3, #0
|
|
8007440: 9300 str r3, [sp, #0]
|
|
8007442: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8007446: 68f8 ldr r0, [r7, #12]
|
|
8007448: f000 fb40 bl 8007acc <I2C_TransferConfig>
|
|
}
|
|
}
|
|
|
|
} while (hi2c->XferCount > 0U);
|
|
800744c: 68fb ldr r3, [r7, #12]
|
|
800744e: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8007450: b29b uxth r3, r3
|
|
8007452: 2b00 cmp r3, #0
|
|
8007454: d19e bne.n 8007394 <HAL_I2C_Mem_Write+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8007456: 697a ldr r2, [r7, #20]
|
|
8007458: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
800745a: 68f8 ldr r0, [r7, #12]
|
|
800745c: f000 fa93 bl 8007986 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8007460: 4603 mov r3, r0
|
|
8007462: 2b00 cmp r3, #0
|
|
8007464: d001 beq.n 800746a <HAL_I2C_Mem_Write+0x1e6>
|
|
{
|
|
return HAL_ERROR;
|
|
8007466: 2301 movs r3, #1
|
|
8007468: e01d b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
800746a: 68fb ldr r3, [r7, #12]
|
|
800746c: 681b ldr r3, [r3, #0]
|
|
800746e: 2220 movs r2, #32
|
|
8007470: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8007472: 68fb ldr r3, [r7, #12]
|
|
8007474: 681b ldr r3, [r3, #0]
|
|
8007476: 6859 ldr r1, [r3, #4]
|
|
8007478: 68fb ldr r3, [r7, #12]
|
|
800747a: 681a ldr r2, [r3, #0]
|
|
800747c: f44f 4368 mov.w r3, #59392 ; 0xe800
|
|
8007480: f6cf 6300 movt r3, #65024 ; 0xfe00
|
|
8007484: 400b ands r3, r1
|
|
8007486: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007488: 68fb ldr r3, [r7, #12]
|
|
800748a: 2220 movs r2, #32
|
|
800748c: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8007490: 68fb ldr r3, [r7, #12]
|
|
8007492: 2200 movs r2, #0
|
|
8007494: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007498: 68fb ldr r3, [r7, #12]
|
|
800749a: 2200 movs r2, #0
|
|
800749c: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
80074a0: 2300 movs r3, #0
|
|
80074a2: e000 b.n 80074a6 <HAL_I2C_Mem_Write+0x222>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80074a4: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80074a6: 4618 mov r0, r3
|
|
80074a8: 3718 adds r7, #24
|
|
80074aa: 46bd mov sp, r7
|
|
80074ac: bd80 pop {r7, pc}
|
|
|
|
080074ae <HAL_I2C_Mem_Read>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
80074ae: b580 push {r7, lr}
|
|
80074b0: b088 sub sp, #32
|
|
80074b2: af02 add r7, sp, #8
|
|
80074b4: 60f8 str r0, [r7, #12]
|
|
80074b6: 4608 mov r0, r1
|
|
80074b8: 4611 mov r1, r2
|
|
80074ba: 461a mov r2, r3
|
|
80074bc: 4603 mov r3, r0
|
|
80074be: 817b strh r3, [r7, #10]
|
|
80074c0: 460b mov r3, r1
|
|
80074c2: 813b strh r3, [r7, #8]
|
|
80074c4: 4613 mov r3, r2
|
|
80074c6: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
80074c8: 68fb ldr r3, [r7, #12]
|
|
80074ca: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
80074ce: b2db uxtb r3, r3
|
|
80074d0: 2b20 cmp r3, #32
|
|
80074d2: f040 8106 bne.w 80076e2 <HAL_I2C_Mem_Read+0x234>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
80074d6: 6a3b ldr r3, [r7, #32]
|
|
80074d8: 2b00 cmp r3, #0
|
|
80074da: d002 beq.n 80074e2 <HAL_I2C_Mem_Read+0x34>
|
|
80074dc: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
80074de: 2b00 cmp r3, #0
|
|
80074e0: d105 bne.n 80074ee <HAL_I2C_Mem_Read+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
80074e2: 68fb ldr r3, [r7, #12]
|
|
80074e4: f44f 7200 mov.w r2, #512 ; 0x200
|
|
80074e8: 645a str r2, [r3, #68] ; 0x44
|
|
return HAL_ERROR;
|
|
80074ea: 2301 movs r3, #1
|
|
80074ec: e0fa b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
80074ee: 68fb ldr r3, [r7, #12]
|
|
80074f0: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
80074f4: 2b01 cmp r3, #1
|
|
80074f6: d101 bne.n 80074fc <HAL_I2C_Mem_Read+0x4e>
|
|
80074f8: 2302 movs r3, #2
|
|
80074fa: e0f3 b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
80074fc: 68fb ldr r3, [r7, #12]
|
|
80074fe: 2201 movs r2, #1
|
|
8007500: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8007504: f7fd fa81 bl 8004a0a <HAL_GetTick>
|
|
8007508: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
800750a: 697b ldr r3, [r7, #20]
|
|
800750c: 9300 str r3, [sp, #0]
|
|
800750e: 2319 movs r3, #25
|
|
8007510: 2201 movs r2, #1
|
|
8007512: f44f 4100 mov.w r1, #32768 ; 0x8000
|
|
8007516: 68f8 ldr r0, [r7, #12]
|
|
8007518: f000 f9b5 bl 8007886 <I2C_WaitOnFlagUntilTimeout>
|
|
800751c: 4603 mov r3, r0
|
|
800751e: 2b00 cmp r3, #0
|
|
8007520: d001 beq.n 8007526 <HAL_I2C_Mem_Read+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8007522: 2301 movs r3, #1
|
|
8007524: e0de b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
8007526: 68fb ldr r3, [r7, #12]
|
|
8007528: 2222 movs r2, #34 ; 0x22
|
|
800752a: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
800752e: 68fb ldr r3, [r7, #12]
|
|
8007530: 2240 movs r2, #64 ; 0x40
|
|
8007532: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8007536: 68fb ldr r3, [r7, #12]
|
|
8007538: 2200 movs r2, #0
|
|
800753a: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
800753c: 68fb ldr r3, [r7, #12]
|
|
800753e: 6a3a ldr r2, [r7, #32]
|
|
8007540: 625a str r2, [r3, #36] ; 0x24
|
|
hi2c->XferCount = Size;
|
|
8007542: 68fb ldr r3, [r7, #12]
|
|
8007544: 8cba ldrh r2, [r7, #36] ; 0x24
|
|
8007546: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8007548: 68fb ldr r3, [r7, #12]
|
|
800754a: 2200 movs r2, #0
|
|
800754c: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
800754e: 88f8 ldrh r0, [r7, #6]
|
|
8007550: 893a ldrh r2, [r7, #8]
|
|
8007552: 8979 ldrh r1, [r7, #10]
|
|
8007554: 697b ldr r3, [r7, #20]
|
|
8007556: 9301 str r3, [sp, #4]
|
|
8007558: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800755a: 9300 str r3, [sp, #0]
|
|
800755c: 4603 mov r3, r0
|
|
800755e: 68f8 ldr r0, [r7, #12]
|
|
8007560: f000 f919 bl 8007796 <I2C_RequestMemoryRead>
|
|
8007564: 4603 mov r3, r0
|
|
8007566: 2b00 cmp r3, #0
|
|
8007568: d005 beq.n 8007576 <HAL_I2C_Mem_Read+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800756a: 68fb ldr r3, [r7, #12]
|
|
800756c: 2200 movs r2, #0
|
|
800756e: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
return HAL_ERROR;
|
|
8007572: 2301 movs r3, #1
|
|
8007574: e0b6 b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
}
|
|
|
|
/* Send Slave Address */
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8007576: 68fb ldr r3, [r7, #12]
|
|
8007578: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
800757a: b29b uxth r3, r3
|
|
800757c: 2bff cmp r3, #255 ; 0xff
|
|
800757e: d911 bls.n 80075a4 <HAL_I2C_Mem_Read+0xf6>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8007580: 68fb ldr r3, [r7, #12]
|
|
8007582: 22ff movs r2, #255 ; 0xff
|
|
8007584: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
|
|
8007586: 68fb ldr r3, [r7, #12]
|
|
8007588: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
800758a: b2da uxtb r2, r3
|
|
800758c: 8979 ldrh r1, [r7, #10]
|
|
800758e: f44f 5310 mov.w r3, #9216 ; 0x2400
|
|
8007592: f2c8 0300 movt r3, #32768 ; 0x8000
|
|
8007596: 9300 str r3, [sp, #0]
|
|
8007598: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
800759c: 68f8 ldr r0, [r7, #12]
|
|
800759e: f000 fa95 bl 8007acc <I2C_TransferConfig>
|
|
80075a2: e012 b.n 80075ca <HAL_I2C_Mem_Read+0x11c>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
80075a4: 68fb ldr r3, [r7, #12]
|
|
80075a6: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80075a8: b29a uxth r2, r3
|
|
80075aa: 68fb ldr r3, [r7, #12]
|
|
80075ac: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
|
|
80075ae: 68fb ldr r3, [r7, #12]
|
|
80075b0: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80075b2: b2da uxtb r2, r3
|
|
80075b4: 8979 ldrh r1, [r7, #10]
|
|
80075b6: f44f 5310 mov.w r3, #9216 ; 0x2400
|
|
80075ba: f2c8 0300 movt r3, #32768 ; 0x8000
|
|
80075be: 9300 str r3, [sp, #0]
|
|
80075c0: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
80075c4: 68f8 ldr r0, [r7, #12]
|
|
80075c6: f000 fa81 bl 8007acc <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
|
|
80075ca: 697b ldr r3, [r7, #20]
|
|
80075cc: 9300 str r3, [sp, #0]
|
|
80075ce: 6abb ldr r3, [r7, #40] ; 0x28
|
|
80075d0: 2200 movs r2, #0
|
|
80075d2: 2104 movs r1, #4
|
|
80075d4: 68f8 ldr r0, [r7, #12]
|
|
80075d6: f000 f956 bl 8007886 <I2C_WaitOnFlagUntilTimeout>
|
|
80075da: 4603 mov r3, r0
|
|
80075dc: 2b00 cmp r3, #0
|
|
80075de: d001 beq.n 80075e4 <HAL_I2C_Mem_Read+0x136>
|
|
{
|
|
return HAL_ERROR;
|
|
80075e0: 2301 movs r3, #1
|
|
80075e2: e07f b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
}
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
80075e4: 68fb ldr r3, [r7, #12]
|
|
80075e6: 681b ldr r3, [r3, #0]
|
|
80075e8: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
80075ea: 68fb ldr r3, [r7, #12]
|
|
80075ec: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80075ee: b2d2 uxtb r2, r2
|
|
80075f0: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
80075f2: 68fb ldr r3, [r7, #12]
|
|
80075f4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80075f6: 1c5a adds r2, r3, #1
|
|
80075f8: 68fb ldr r3, [r7, #12]
|
|
80075fa: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hi2c->XferSize--;
|
|
80075fc: 68fb ldr r3, [r7, #12]
|
|
80075fe: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8007600: 3b01 subs r3, #1
|
|
8007602: b29a uxth r2, r3
|
|
8007604: 68fb ldr r3, [r7, #12]
|
|
8007606: 851a strh r2, [r3, #40] ; 0x28
|
|
hi2c->XferCount--;
|
|
8007608: 68fb ldr r3, [r7, #12]
|
|
800760a: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
800760c: b29b uxth r3, r3
|
|
800760e: 3b01 subs r3, #1
|
|
8007610: b29a uxth r2, r3
|
|
8007612: 68fb ldr r3, [r7, #12]
|
|
8007614: 855a strh r2, [r3, #42] ; 0x2a
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8007616: 68fb ldr r3, [r7, #12]
|
|
8007618: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
800761a: b29b uxth r3, r3
|
|
800761c: 2b00 cmp r3, #0
|
|
800761e: d034 beq.n 800768a <HAL_I2C_Mem_Read+0x1dc>
|
|
8007620: 68fb ldr r3, [r7, #12]
|
|
8007622: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8007624: 2b00 cmp r3, #0
|
|
8007626: d130 bne.n 800768a <HAL_I2C_Mem_Read+0x1dc>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8007628: 697b ldr r3, [r7, #20]
|
|
800762a: 9300 str r3, [sp, #0]
|
|
800762c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800762e: 2200 movs r2, #0
|
|
8007630: 2180 movs r1, #128 ; 0x80
|
|
8007632: 68f8 ldr r0, [r7, #12]
|
|
8007634: f000 f927 bl 8007886 <I2C_WaitOnFlagUntilTimeout>
|
|
8007638: 4603 mov r3, r0
|
|
800763a: 2b00 cmp r3, #0
|
|
800763c: d001 beq.n 8007642 <HAL_I2C_Mem_Read+0x194>
|
|
{
|
|
return HAL_ERROR;
|
|
800763e: 2301 movs r3, #1
|
|
8007640: e050 b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8007642: 68fb ldr r3, [r7, #12]
|
|
8007644: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8007646: b29b uxth r3, r3
|
|
8007648: 2bff cmp r3, #255 ; 0xff
|
|
800764a: d90e bls.n 800766a <HAL_I2C_Mem_Read+0x1bc>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
800764c: 68fb ldr r3, [r7, #12]
|
|
800764e: 22ff movs r2, #255 ; 0xff
|
|
8007650: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
8007652: 68fb ldr r3, [r7, #12]
|
|
8007654: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8007656: b2da uxtb r2, r3
|
|
8007658: 8979 ldrh r1, [r7, #10]
|
|
800765a: 2300 movs r3, #0
|
|
800765c: 9300 str r3, [sp, #0]
|
|
800765e: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
8007662: 68f8 ldr r0, [r7, #12]
|
|
8007664: f000 fa32 bl 8007acc <I2C_TransferConfig>
|
|
8007668: e00f b.n 800768a <HAL_I2C_Mem_Read+0x1dc>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
800766a: 68fb ldr r3, [r7, #12]
|
|
800766c: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
800766e: b29a uxth r2, r3
|
|
8007670: 68fb ldr r3, [r7, #12]
|
|
8007672: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8007674: 68fb ldr r3, [r7, #12]
|
|
8007676: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8007678: b2da uxtb r2, r3
|
|
800767a: 8979 ldrh r1, [r7, #10]
|
|
800767c: 2300 movs r3, #0
|
|
800767e: 9300 str r3, [sp, #0]
|
|
8007680: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8007684: 68f8 ldr r0, [r7, #12]
|
|
8007686: f000 fa21 bl 8007acc <I2C_TransferConfig>
|
|
}
|
|
}
|
|
} while (hi2c->XferCount > 0U);
|
|
800768a: 68fb ldr r3, [r7, #12]
|
|
800768c: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
800768e: b29b uxth r3, r3
|
|
8007690: 2b00 cmp r3, #0
|
|
8007692: d19a bne.n 80075ca <HAL_I2C_Mem_Read+0x11c>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8007694: 697a ldr r2, [r7, #20]
|
|
8007696: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
8007698: 68f8 ldr r0, [r7, #12]
|
|
800769a: f000 f974 bl 8007986 <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
800769e: 4603 mov r3, r0
|
|
80076a0: 2b00 cmp r3, #0
|
|
80076a2: d001 beq.n 80076a8 <HAL_I2C_Mem_Read+0x1fa>
|
|
{
|
|
return HAL_ERROR;
|
|
80076a4: 2301 movs r3, #1
|
|
80076a6: e01d b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
80076a8: 68fb ldr r3, [r7, #12]
|
|
80076aa: 681b ldr r3, [r3, #0]
|
|
80076ac: 2220 movs r2, #32
|
|
80076ae: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
80076b0: 68fb ldr r3, [r7, #12]
|
|
80076b2: 681b ldr r3, [r3, #0]
|
|
80076b4: 6859 ldr r1, [r3, #4]
|
|
80076b6: 68fb ldr r3, [r7, #12]
|
|
80076b8: 681a ldr r2, [r3, #0]
|
|
80076ba: f44f 4368 mov.w r3, #59392 ; 0xe800
|
|
80076be: f6cf 6300 movt r3, #65024 ; 0xfe00
|
|
80076c2: 400b ands r3, r1
|
|
80076c4: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80076c6: 68fb ldr r3, [r7, #12]
|
|
80076c8: 2220 movs r2, #32
|
|
80076ca: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80076ce: 68fb ldr r3, [r7, #12]
|
|
80076d0: 2200 movs r2, #0
|
|
80076d2: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80076d6: 68fb ldr r3, [r7, #12]
|
|
80076d8: 2200 movs r2, #0
|
|
80076da: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
80076de: 2300 movs r3, #0
|
|
80076e0: e000 b.n 80076e4 <HAL_I2C_Mem_Read+0x236>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80076e2: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80076e4: 4618 mov r0, r3
|
|
80076e6: 3718 adds r7, #24
|
|
80076e8: 46bd mov sp, r7
|
|
80076ea: bd80 pop {r7, pc}
|
|
|
|
080076ec <I2C_RequestMemoryWrite>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80076ec: b580 push {r7, lr}
|
|
80076ee: b086 sub sp, #24
|
|
80076f0: af02 add r7, sp, #8
|
|
80076f2: 60f8 str r0, [r7, #12]
|
|
80076f4: 4608 mov r0, r1
|
|
80076f6: 4611 mov r1, r2
|
|
80076f8: 461a mov r2, r3
|
|
80076fa: 4603 mov r3, r0
|
|
80076fc: 817b strh r3, [r7, #10]
|
|
80076fe: 460b mov r3, r1
|
|
8007700: 813b strh r3, [r7, #8]
|
|
8007702: 4613 mov r3, r2
|
|
8007704: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
8007706: 88fb ldrh r3, [r7, #6]
|
|
8007708: b2da uxtb r2, r3
|
|
800770a: 8979 ldrh r1, [r7, #10]
|
|
800770c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8007710: f2c8 0300 movt r3, #32768 ; 0x8000
|
|
8007714: 9300 str r3, [sp, #0]
|
|
8007716: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
800771a: 68f8 ldr r0, [r7, #12]
|
|
800771c: f000 f9d6 bl 8007acc <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8007720: 69fa ldr r2, [r7, #28]
|
|
8007722: 69b9 ldr r1, [r7, #24]
|
|
8007724: 68f8 ldr r0, [r7, #12]
|
|
8007726: f000 f8ee bl 8007906 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800772a: 4603 mov r3, r0
|
|
800772c: 2b00 cmp r3, #0
|
|
800772e: d001 beq.n 8007734 <I2C_RequestMemoryWrite+0x48>
|
|
{
|
|
return HAL_ERROR;
|
|
8007730: 2301 movs r3, #1
|
|
8007732: e02c b.n 800778e <I2C_RequestMemoryWrite+0xa2>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8007734: 88fb ldrh r3, [r7, #6]
|
|
8007736: 2b01 cmp r3, #1
|
|
8007738: d105 bne.n 8007746 <I2C_RequestMemoryWrite+0x5a>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
800773a: 893b ldrh r3, [r7, #8]
|
|
800773c: b2da uxtb r2, r3
|
|
800773e: 68fb ldr r3, [r7, #12]
|
|
8007740: 681b ldr r3, [r3, #0]
|
|
8007742: 629a str r2, [r3, #40] ; 0x28
|
|
8007744: e015 b.n 8007772 <I2C_RequestMemoryWrite+0x86>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
8007746: 893b ldrh r3, [r7, #8]
|
|
8007748: 0a1b lsrs r3, r3, #8
|
|
800774a: b29b uxth r3, r3
|
|
800774c: b2da uxtb r2, r3
|
|
800774e: 68fb ldr r3, [r7, #12]
|
|
8007750: 681b ldr r3, [r3, #0]
|
|
8007752: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8007754: 69fa ldr r2, [r7, #28]
|
|
8007756: 69b9 ldr r1, [r7, #24]
|
|
8007758: 68f8 ldr r0, [r7, #12]
|
|
800775a: f000 f8d4 bl 8007906 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800775e: 4603 mov r3, r0
|
|
8007760: 2b00 cmp r3, #0
|
|
8007762: d001 beq.n 8007768 <I2C_RequestMemoryWrite+0x7c>
|
|
{
|
|
return HAL_ERROR;
|
|
8007764: 2301 movs r3, #1
|
|
8007766: e012 b.n 800778e <I2C_RequestMemoryWrite+0xa2>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8007768: 893b ldrh r3, [r7, #8]
|
|
800776a: b2da uxtb r2, r3
|
|
800776c: 68fb ldr r3, [r7, #12]
|
|
800776e: 681b ldr r3, [r3, #0]
|
|
8007770: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8007772: 69fb ldr r3, [r7, #28]
|
|
8007774: 9300 str r3, [sp, #0]
|
|
8007776: 69bb ldr r3, [r7, #24]
|
|
8007778: 2200 movs r2, #0
|
|
800777a: 2180 movs r1, #128 ; 0x80
|
|
800777c: 68f8 ldr r0, [r7, #12]
|
|
800777e: f000 f882 bl 8007886 <I2C_WaitOnFlagUntilTimeout>
|
|
8007782: 4603 mov r3, r0
|
|
8007784: 2b00 cmp r3, #0
|
|
8007786: d001 beq.n 800778c <I2C_RequestMemoryWrite+0xa0>
|
|
{
|
|
return HAL_ERROR;
|
|
8007788: 2301 movs r3, #1
|
|
800778a: e000 b.n 800778e <I2C_RequestMemoryWrite+0xa2>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800778c: 2300 movs r3, #0
|
|
}
|
|
800778e: 4618 mov r0, r3
|
|
8007790: 3710 adds r7, #16
|
|
8007792: 46bd mov sp, r7
|
|
8007794: bd80 pop {r7, pc}
|
|
|
|
08007796 <I2C_RequestMemoryRead>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8007796: b580 push {r7, lr}
|
|
8007798: b086 sub sp, #24
|
|
800779a: af02 add r7, sp, #8
|
|
800779c: 60f8 str r0, [r7, #12]
|
|
800779e: 4608 mov r0, r1
|
|
80077a0: 4611 mov r1, r2
|
|
80077a2: 461a mov r2, r3
|
|
80077a4: 4603 mov r3, r0
|
|
80077a6: 817b strh r3, [r7, #10]
|
|
80077a8: 460b mov r3, r1
|
|
80077aa: 813b strh r3, [r7, #8]
|
|
80077ac: 4613 mov r3, r2
|
|
80077ae: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
80077b0: 88fb ldrh r3, [r7, #6]
|
|
80077b2: b2da uxtb r2, r3
|
|
80077b4: 8979 ldrh r1, [r7, #10]
|
|
80077b6: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
80077ba: f2c8 0300 movt r3, #32768 ; 0x8000
|
|
80077be: 9300 str r3, [sp, #0]
|
|
80077c0: 2300 movs r3, #0
|
|
80077c2: 68f8 ldr r0, [r7, #12]
|
|
80077c4: f000 f982 bl 8007acc <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80077c8: 69fa ldr r2, [r7, #28]
|
|
80077ca: 69b9 ldr r1, [r7, #24]
|
|
80077cc: 68f8 ldr r0, [r7, #12]
|
|
80077ce: f000 f89a bl 8007906 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80077d2: 4603 mov r3, r0
|
|
80077d4: 2b00 cmp r3, #0
|
|
80077d6: d001 beq.n 80077dc <I2C_RequestMemoryRead+0x46>
|
|
{
|
|
return HAL_ERROR;
|
|
80077d8: 2301 movs r3, #1
|
|
80077da: e02c b.n 8007836 <I2C_RequestMemoryRead+0xa0>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
80077dc: 88fb ldrh r3, [r7, #6]
|
|
80077de: 2b01 cmp r3, #1
|
|
80077e0: d105 bne.n 80077ee <I2C_RequestMemoryRead+0x58>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80077e2: 893b ldrh r3, [r7, #8]
|
|
80077e4: b2da uxtb r2, r3
|
|
80077e6: 68fb ldr r3, [r7, #12]
|
|
80077e8: 681b ldr r3, [r3, #0]
|
|
80077ea: 629a str r2, [r3, #40] ; 0x28
|
|
80077ec: e015 b.n 800781a <I2C_RequestMemoryRead+0x84>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
80077ee: 893b ldrh r3, [r7, #8]
|
|
80077f0: 0a1b lsrs r3, r3, #8
|
|
80077f2: b29b uxth r3, r3
|
|
80077f4: b2da uxtb r2, r3
|
|
80077f6: 68fb ldr r3, [r7, #12]
|
|
80077f8: 681b ldr r3, [r3, #0]
|
|
80077fa: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80077fc: 69fa ldr r2, [r7, #28]
|
|
80077fe: 69b9 ldr r1, [r7, #24]
|
|
8007800: 68f8 ldr r0, [r7, #12]
|
|
8007802: f000 f880 bl 8007906 <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8007806: 4603 mov r3, r0
|
|
8007808: 2b00 cmp r3, #0
|
|
800780a: d001 beq.n 8007810 <I2C_RequestMemoryRead+0x7a>
|
|
{
|
|
return HAL_ERROR;
|
|
800780c: 2301 movs r3, #1
|
|
800780e: e012 b.n 8007836 <I2C_RequestMemoryRead+0xa0>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8007810: 893b ldrh r3, [r7, #8]
|
|
8007812: b2da uxtb r2, r3
|
|
8007814: 68fb ldr r3, [r7, #12]
|
|
8007816: 681b ldr r3, [r3, #0]
|
|
8007818: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Wait until TC flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
|
|
800781a: 69fb ldr r3, [r7, #28]
|
|
800781c: 9300 str r3, [sp, #0]
|
|
800781e: 69bb ldr r3, [r7, #24]
|
|
8007820: 2200 movs r2, #0
|
|
8007822: 2140 movs r1, #64 ; 0x40
|
|
8007824: 68f8 ldr r0, [r7, #12]
|
|
8007826: f000 f82e bl 8007886 <I2C_WaitOnFlagUntilTimeout>
|
|
800782a: 4603 mov r3, r0
|
|
800782c: 2b00 cmp r3, #0
|
|
800782e: d001 beq.n 8007834 <I2C_RequestMemoryRead+0x9e>
|
|
{
|
|
return HAL_ERROR;
|
|
8007830: 2301 movs r3, #1
|
|
8007832: e000 b.n 8007836 <I2C_RequestMemoryRead+0xa0>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007834: 2300 movs r3, #0
|
|
}
|
|
8007836: 4618 mov r0, r3
|
|
8007838: 3710 adds r7, #16
|
|
800783a: 46bd mov sp, r7
|
|
800783c: bd80 pop {r7, pc}
|
|
|
|
0800783e <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
800783e: b480 push {r7}
|
|
8007840: b083 sub sp, #12
|
|
8007842: af00 add r7, sp, #0
|
|
8007844: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
8007846: 687b ldr r3, [r7, #4]
|
|
8007848: 681b ldr r3, [r3, #0]
|
|
800784a: 699b ldr r3, [r3, #24]
|
|
800784c: f003 0302 and.w r3, r3, #2
|
|
8007850: 2b02 cmp r3, #2
|
|
8007852: d103 bne.n 800785c <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
8007854: 687b ldr r3, [r7, #4]
|
|
8007856: 681b ldr r3, [r3, #0]
|
|
8007858: 2200 movs r2, #0
|
|
800785a: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
800785c: 687b ldr r3, [r7, #4]
|
|
800785e: 681b ldr r3, [r3, #0]
|
|
8007860: 699b ldr r3, [r3, #24]
|
|
8007862: f003 0301 and.w r3, r3, #1
|
|
8007866: 2b01 cmp r3, #1
|
|
8007868: d007 beq.n 800787a <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
800786a: 687b ldr r3, [r7, #4]
|
|
800786c: 681b ldr r3, [r3, #0]
|
|
800786e: 699a ldr r2, [r3, #24]
|
|
8007870: 687b ldr r3, [r7, #4]
|
|
8007872: 681b ldr r3, [r3, #0]
|
|
8007874: f042 0201 orr.w r2, r2, #1
|
|
8007878: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
800787a: bf00 nop
|
|
800787c: 370c adds r7, #12
|
|
800787e: 46bd mov sp, r7
|
|
8007880: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007884: 4770 bx lr
|
|
|
|
08007886 <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8007886: b580 push {r7, lr}
|
|
8007888: b084 sub sp, #16
|
|
800788a: af00 add r7, sp, #0
|
|
800788c: 60f8 str r0, [r7, #12]
|
|
800788e: 60b9 str r1, [r7, #8]
|
|
8007890: 603b str r3, [r7, #0]
|
|
8007892: 4613 mov r3, r2
|
|
8007894: 71fb strb r3, [r7, #7]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8007896: e022 b.n 80078de <I2C_WaitOnFlagUntilTimeout+0x58>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8007898: 683b ldr r3, [r7, #0]
|
|
800789a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
|
|
800789e: d01e beq.n 80078de <I2C_WaitOnFlagUntilTimeout+0x58>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80078a0: f7fd f8b3 bl 8004a0a <HAL_GetTick>
|
|
80078a4: 4602 mov r2, r0
|
|
80078a6: 69bb ldr r3, [r7, #24]
|
|
80078a8: 1ad3 subs r3, r2, r3
|
|
80078aa: 683a ldr r2, [r7, #0]
|
|
80078ac: 429a cmp r2, r3
|
|
80078ae: d302 bcc.n 80078b6 <I2C_WaitOnFlagUntilTimeout+0x30>
|
|
80078b0: 683b ldr r3, [r7, #0]
|
|
80078b2: 2b00 cmp r3, #0
|
|
80078b4: d113 bne.n 80078de <I2C_WaitOnFlagUntilTimeout+0x58>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80078b6: 68fb ldr r3, [r7, #12]
|
|
80078b8: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80078ba: f043 0220 orr.w r2, r3, #32
|
|
80078be: 68fb ldr r3, [r7, #12]
|
|
80078c0: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80078c2: 68fb ldr r3, [r7, #12]
|
|
80078c4: 2220 movs r2, #32
|
|
80078c6: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80078ca: 68fb ldr r3, [r7, #12]
|
|
80078cc: 2200 movs r2, #0
|
|
80078ce: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80078d2: 68fb ldr r3, [r7, #12]
|
|
80078d4: 2200 movs r2, #0
|
|
80078d6: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
return HAL_ERROR;
|
|
80078da: 2301 movs r3, #1
|
|
80078dc: e00f b.n 80078fe <I2C_WaitOnFlagUntilTimeout+0x78>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
80078de: 68fb ldr r3, [r7, #12]
|
|
80078e0: 681b ldr r3, [r3, #0]
|
|
80078e2: 699a ldr r2, [r3, #24]
|
|
80078e4: 68bb ldr r3, [r7, #8]
|
|
80078e6: 4013 ands r3, r2
|
|
80078e8: 68ba ldr r2, [r7, #8]
|
|
80078ea: 429a cmp r2, r3
|
|
80078ec: bf0c ite eq
|
|
80078ee: 2301 moveq r3, #1
|
|
80078f0: 2300 movne r3, #0
|
|
80078f2: b2db uxtb r3, r3
|
|
80078f4: 461a mov r2, r3
|
|
80078f6: 79fb ldrb r3, [r7, #7]
|
|
80078f8: 429a cmp r2, r3
|
|
80078fa: d0cd beq.n 8007898 <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80078fc: 2300 movs r3, #0
|
|
}
|
|
80078fe: 4618 mov r0, r3
|
|
8007900: 3710 adds r7, #16
|
|
8007902: 46bd mov sp, r7
|
|
8007904: bd80 pop {r7, pc}
|
|
|
|
08007906 <I2C_WaitOnTXISFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8007906: b580 push {r7, lr}
|
|
8007908: b084 sub sp, #16
|
|
800790a: af00 add r7, sp, #0
|
|
800790c: 60f8 str r0, [r7, #12]
|
|
800790e: 60b9 str r1, [r7, #8]
|
|
8007910: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
8007912: e02c b.n 800796e <I2C_WaitOnTXISFlagUntilTimeout+0x68>
|
|
{
|
|
/* Check if a NACK is detected */
|
|
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8007914: 687a ldr r2, [r7, #4]
|
|
8007916: 68b9 ldr r1, [r7, #8]
|
|
8007918: 68f8 ldr r0, [r7, #12]
|
|
800791a: f000 f870 bl 80079fe <I2C_IsAcknowledgeFailed>
|
|
800791e: 4603 mov r3, r0
|
|
8007920: 2b00 cmp r3, #0
|
|
8007922: d001 beq.n 8007928 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
8007924: 2301 movs r3, #1
|
|
8007926: e02a b.n 800797e <I2C_WaitOnTXISFlagUntilTimeout+0x78>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8007928: 68bb ldr r3, [r7, #8]
|
|
800792a: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
|
|
800792e: d01e beq.n 800796e <I2C_WaitOnTXISFlagUntilTimeout+0x68>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8007930: f7fd f86b bl 8004a0a <HAL_GetTick>
|
|
8007934: 4602 mov r2, r0
|
|
8007936: 687b ldr r3, [r7, #4]
|
|
8007938: 1ad3 subs r3, r2, r3
|
|
800793a: 68ba ldr r2, [r7, #8]
|
|
800793c: 429a cmp r2, r3
|
|
800793e: d302 bcc.n 8007946 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
|
|
8007940: 68bb ldr r3, [r7, #8]
|
|
8007942: 2b00 cmp r3, #0
|
|
8007944: d113 bne.n 800796e <I2C_WaitOnTXISFlagUntilTimeout+0x68>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8007946: 68fb ldr r3, [r7, #12]
|
|
8007948: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800794a: f043 0220 orr.w r2, r3, #32
|
|
800794e: 68fb ldr r3, [r7, #12]
|
|
8007950: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007952: 68fb ldr r3, [r7, #12]
|
|
8007954: 2220 movs r2, #32
|
|
8007956: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
800795a: 68fb ldr r3, [r7, #12]
|
|
800795c: 2200 movs r2, #0
|
|
800795e: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007962: 68fb ldr r3, [r7, #12]
|
|
8007964: 2200 movs r2, #0
|
|
8007966: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
800796a: 2301 movs r3, #1
|
|
800796c: e007 b.n 800797e <I2C_WaitOnTXISFlagUntilTimeout+0x78>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
800796e: 68fb ldr r3, [r7, #12]
|
|
8007970: 681b ldr r3, [r3, #0]
|
|
8007972: 699b ldr r3, [r3, #24]
|
|
8007974: f003 0302 and.w r3, r3, #2
|
|
8007978: 2b02 cmp r3, #2
|
|
800797a: d1cb bne.n 8007914 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800797c: 2300 movs r3, #0
|
|
}
|
|
800797e: 4618 mov r0, r3
|
|
8007980: 3710 adds r7, #16
|
|
8007982: 46bd mov sp, r7
|
|
8007984: bd80 pop {r7, pc}
|
|
|
|
08007986 <I2C_WaitOnSTOPFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8007986: b580 push {r7, lr}
|
|
8007988: b084 sub sp, #16
|
|
800798a: af00 add r7, sp, #0
|
|
800798c: 60f8 str r0, [r7, #12]
|
|
800798e: 60b9 str r1, [r7, #8]
|
|
8007990: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8007992: e028 b.n 80079e6 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
|
|
{
|
|
/* Check if a NACK is detected */
|
|
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8007994: 687a ldr r2, [r7, #4]
|
|
8007996: 68b9 ldr r1, [r7, #8]
|
|
8007998: 68f8 ldr r0, [r7, #12]
|
|
800799a: f000 f830 bl 80079fe <I2C_IsAcknowledgeFailed>
|
|
800799e: 4603 mov r3, r0
|
|
80079a0: 2b00 cmp r3, #0
|
|
80079a2: d001 beq.n 80079a8 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80079a4: 2301 movs r3, #1
|
|
80079a6: e026 b.n 80079f6 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80079a8: f7fd f82f bl 8004a0a <HAL_GetTick>
|
|
80079ac: 4602 mov r2, r0
|
|
80079ae: 687b ldr r3, [r7, #4]
|
|
80079b0: 1ad3 subs r3, r2, r3
|
|
80079b2: 68ba ldr r2, [r7, #8]
|
|
80079b4: 429a cmp r2, r3
|
|
80079b6: d302 bcc.n 80079be <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
|
|
80079b8: 68bb ldr r3, [r7, #8]
|
|
80079ba: 2b00 cmp r3, #0
|
|
80079bc: d113 bne.n 80079e6 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80079be: 68fb ldr r3, [r7, #12]
|
|
80079c0: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80079c2: f043 0220 orr.w r2, r3, #32
|
|
80079c6: 68fb ldr r3, [r7, #12]
|
|
80079c8: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80079ca: 68fb ldr r3, [r7, #12]
|
|
80079cc: 2220 movs r2, #32
|
|
80079ce: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80079d2: 68fb ldr r3, [r7, #12]
|
|
80079d4: 2200 movs r2, #0
|
|
80079d6: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80079da: 68fb ldr r3, [r7, #12]
|
|
80079dc: 2200 movs r2, #0
|
|
80079de: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
80079e2: 2301 movs r3, #1
|
|
80079e4: e007 b.n 80079f6 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80079e6: 68fb ldr r3, [r7, #12]
|
|
80079e8: 681b ldr r3, [r3, #0]
|
|
80079ea: 699b ldr r3, [r3, #24]
|
|
80079ec: f003 0320 and.w r3, r3, #32
|
|
80079f0: 2b20 cmp r3, #32
|
|
80079f2: d1cf bne.n 8007994 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80079f4: 2300 movs r3, #0
|
|
}
|
|
80079f6: 4618 mov r0, r3
|
|
80079f8: 3710 adds r7, #16
|
|
80079fa: 46bd mov sp, r7
|
|
80079fc: bd80 pop {r7, pc}
|
|
|
|
080079fe <I2C_IsAcknowledgeFailed>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
80079fe: b580 push {r7, lr}
|
|
8007a00: b084 sub sp, #16
|
|
8007a02: af00 add r7, sp, #0
|
|
8007a04: 60f8 str r0, [r7, #12]
|
|
8007a06: 60b9 str r1, [r7, #8]
|
|
8007a08: 607a str r2, [r7, #4]
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
|
8007a0a: 68fb ldr r3, [r7, #12]
|
|
8007a0c: 681b ldr r3, [r3, #0]
|
|
8007a0e: 699b ldr r3, [r3, #24]
|
|
8007a10: f003 0310 and.w r3, r3, #16
|
|
8007a14: 2b10 cmp r3, #16
|
|
8007a16: d154 bne.n 8007ac2 <I2C_IsAcknowledgeFailed+0xc4>
|
|
{
|
|
/* Wait until STOP Flag is reset */
|
|
/* AutoEnd should be initiate after AF */
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8007a18: e022 b.n 8007a60 <I2C_IsAcknowledgeFailed+0x62>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8007a1a: 68bb ldr r3, [r7, #8]
|
|
8007a1c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
|
|
8007a20: d01e beq.n 8007a60 <I2C_IsAcknowledgeFailed+0x62>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8007a22: f7fc fff2 bl 8004a0a <HAL_GetTick>
|
|
8007a26: 4602 mov r2, r0
|
|
8007a28: 687b ldr r3, [r7, #4]
|
|
8007a2a: 1ad3 subs r3, r2, r3
|
|
8007a2c: 68ba ldr r2, [r7, #8]
|
|
8007a2e: 429a cmp r2, r3
|
|
8007a30: d302 bcc.n 8007a38 <I2C_IsAcknowledgeFailed+0x3a>
|
|
8007a32: 68bb ldr r3, [r7, #8]
|
|
8007a34: 2b00 cmp r3, #0
|
|
8007a36: d113 bne.n 8007a60 <I2C_IsAcknowledgeFailed+0x62>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8007a38: 68fb ldr r3, [r7, #12]
|
|
8007a3a: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8007a3c: f043 0220 orr.w r2, r3, #32
|
|
8007a40: 68fb ldr r3, [r7, #12]
|
|
8007a42: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007a44: 68fb ldr r3, [r7, #12]
|
|
8007a46: 2220 movs r2, #32
|
|
8007a48: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8007a4c: 68fb ldr r3, [r7, #12]
|
|
8007a4e: 2200 movs r2, #0
|
|
8007a50: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007a54: 68fb ldr r3, [r7, #12]
|
|
8007a56: 2200 movs r2, #0
|
|
8007a58: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
8007a5c: 2301 movs r3, #1
|
|
8007a5e: e031 b.n 8007ac4 <I2C_IsAcknowledgeFailed+0xc6>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8007a60: 68fb ldr r3, [r7, #12]
|
|
8007a62: 681b ldr r3, [r3, #0]
|
|
8007a64: 699b ldr r3, [r3, #24]
|
|
8007a66: f003 0320 and.w r3, r3, #32
|
|
8007a6a: 2b20 cmp r3, #32
|
|
8007a6c: d1d5 bne.n 8007a1a <I2C_IsAcknowledgeFailed+0x1c>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8007a6e: 68fb ldr r3, [r7, #12]
|
|
8007a70: 681b ldr r3, [r3, #0]
|
|
8007a72: 2210 movs r2, #16
|
|
8007a74: 61da str r2, [r3, #28]
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8007a76: 68fb ldr r3, [r7, #12]
|
|
8007a78: 681b ldr r3, [r3, #0]
|
|
8007a7a: 2220 movs r2, #32
|
|
8007a7c: 61da str r2, [r3, #28]
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8007a7e: 68f8 ldr r0, [r7, #12]
|
|
8007a80: f7ff fedd bl 800783e <I2C_Flush_TXDR>
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8007a84: 68fb ldr r3, [r7, #12]
|
|
8007a86: 681b ldr r3, [r3, #0]
|
|
8007a88: 6859 ldr r1, [r3, #4]
|
|
8007a8a: 68fb ldr r3, [r7, #12]
|
|
8007a8c: 681a ldr r2, [r3, #0]
|
|
8007a8e: f44f 4368 mov.w r3, #59392 ; 0xe800
|
|
8007a92: f6cf 6300 movt r3, #65024 ; 0xfe00
|
|
8007a96: 400b ands r3, r1
|
|
8007a98: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8007a9a: 68fb ldr r3, [r7, #12]
|
|
8007a9c: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8007a9e: f043 0204 orr.w r2, r3, #4
|
|
8007aa2: 68fb ldr r3, [r7, #12]
|
|
8007aa4: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007aa6: 68fb ldr r3, [r7, #12]
|
|
8007aa8: 2220 movs r2, #32
|
|
8007aaa: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8007aae: 68fb ldr r3, [r7, #12]
|
|
8007ab0: 2200 movs r2, #0
|
|
8007ab2: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007ab6: 68fb ldr r3, [r7, #12]
|
|
8007ab8: 2200 movs r2, #0
|
|
8007aba: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
8007abe: 2301 movs r3, #1
|
|
8007ac0: e000 b.n 8007ac4 <I2C_IsAcknowledgeFailed+0xc6>
|
|
}
|
|
return HAL_OK;
|
|
8007ac2: 2300 movs r3, #0
|
|
}
|
|
8007ac4: 4618 mov r0, r3
|
|
8007ac6: 3710 adds r7, #16
|
|
8007ac8: 46bd mov sp, r7
|
|
8007aca: bd80 pop {r7, pc}
|
|
|
|
08007acc <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
|
uint32_t Request)
|
|
{
|
|
8007acc: b480 push {r7}
|
|
8007ace: b085 sub sp, #20
|
|
8007ad0: af00 add r7, sp, #0
|
|
8007ad2: 60f8 str r0, [r7, #12]
|
|
8007ad4: 607b str r3, [r7, #4]
|
|
8007ad6: 460b mov r3, r1
|
|
8007ad8: 817b strh r3, [r7, #10]
|
|
8007ada: 4613 mov r3, r2
|
|
8007adc: 727b strb r3, [r7, #9]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2,
|
|
8007ade: 68fb ldr r3, [r7, #12]
|
|
8007ae0: 681b ldr r3, [r3, #0]
|
|
8007ae2: 685a ldr r2, [r3, #4]
|
|
8007ae4: 69bb ldr r3, [r7, #24]
|
|
8007ae6: 0d5b lsrs r3, r3, #21
|
|
8007ae8: f403 6180 and.w r1, r3, #1024 ; 0x400
|
|
8007aec: f246 33ff movw r3, #25599 ; 0x63ff
|
|
8007af0: f2c0 33ff movt r3, #1023 ; 0x3ff
|
|
8007af4: 430b orrs r3, r1
|
|
8007af6: 43db mvns r3, r3
|
|
8007af8: ea02 0103 and.w r1, r2, r3
|
|
8007afc: 897b ldrh r3, [r7, #10]
|
|
8007afe: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8007b02: 7a7b ldrb r3, [r7, #9]
|
|
8007b04: 041b lsls r3, r3, #16
|
|
8007b06: f403 037f and.w r3, r3, #16711680 ; 0xff0000
|
|
8007b0a: 431a orrs r2, r3
|
|
8007b0c: 687b ldr r3, [r7, #4]
|
|
8007b0e: 431a orrs r2, r3
|
|
8007b10: 69bb ldr r3, [r7, #24]
|
|
8007b12: 431a orrs r2, r3
|
|
8007b14: 68fb ldr r3, [r7, #12]
|
|
8007b16: 681b ldr r3, [r3, #0]
|
|
8007b18: 430a orrs r2, r1
|
|
8007b1a: 605a str r2, [r3, #4]
|
|
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
|
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
|
|
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
|
}
|
|
8007b1c: bf00 nop
|
|
8007b1e: 3714 adds r7, #20
|
|
8007b20: 46bd mov sp, r7
|
|
8007b22: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007b26: 4770 bx lr
|
|
|
|
08007b28 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8007b28: b480 push {r7}
|
|
8007b2a: b083 sub sp, #12
|
|
8007b2c: af00 add r7, sp, #0
|
|
8007b2e: 6078 str r0, [r7, #4]
|
|
8007b30: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8007b32: 687b ldr r3, [r7, #4]
|
|
8007b34: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
8007b38: b2db uxtb r3, r3
|
|
8007b3a: 2b20 cmp r3, #32
|
|
8007b3c: d138 bne.n 8007bb0 <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8007b3e: 687b ldr r3, [r7, #4]
|
|
8007b40: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
8007b44: 2b01 cmp r3, #1
|
|
8007b46: d101 bne.n 8007b4c <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
8007b48: 2302 movs r3, #2
|
|
8007b4a: e032 b.n 8007bb2 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
8007b4c: 687b ldr r3, [r7, #4]
|
|
8007b4e: 2201 movs r2, #1
|
|
8007b50: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8007b54: 687b ldr r3, [r7, #4]
|
|
8007b56: 2224 movs r2, #36 ; 0x24
|
|
8007b58: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8007b5c: 687b ldr r3, [r7, #4]
|
|
8007b5e: 681b ldr r3, [r3, #0]
|
|
8007b60: 681a ldr r2, [r3, #0]
|
|
8007b62: 687b ldr r3, [r7, #4]
|
|
8007b64: 681b ldr r3, [r3, #0]
|
|
8007b66: f022 0201 bic.w r2, r2, #1
|
|
8007b6a: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
8007b6c: 687b ldr r3, [r7, #4]
|
|
8007b6e: 681b ldr r3, [r3, #0]
|
|
8007b70: 681a ldr r2, [r3, #0]
|
|
8007b72: 687b ldr r3, [r7, #4]
|
|
8007b74: 681b ldr r3, [r3, #0]
|
|
8007b76: f422 5280 bic.w r2, r2, #4096 ; 0x1000
|
|
8007b7a: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
8007b7c: 687b ldr r3, [r7, #4]
|
|
8007b7e: 681b ldr r3, [r3, #0]
|
|
8007b80: 6819 ldr r1, [r3, #0]
|
|
8007b82: 687b ldr r3, [r7, #4]
|
|
8007b84: 681b ldr r3, [r3, #0]
|
|
8007b86: 683a ldr r2, [r7, #0]
|
|
8007b88: 430a orrs r2, r1
|
|
8007b8a: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8007b8c: 687b ldr r3, [r7, #4]
|
|
8007b8e: 681b ldr r3, [r3, #0]
|
|
8007b90: 681a ldr r2, [r3, #0]
|
|
8007b92: 687b ldr r3, [r7, #4]
|
|
8007b94: 681b ldr r3, [r3, #0]
|
|
8007b96: f042 0201 orr.w r2, r2, #1
|
|
8007b9a: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007b9c: 687b ldr r3, [r7, #4]
|
|
8007b9e: 2220 movs r2, #32
|
|
8007ba0: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007ba4: 687b ldr r3, [r7, #4]
|
|
8007ba6: 2200 movs r2, #0
|
|
8007ba8: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
8007bac: 2300 movs r3, #0
|
|
8007bae: e000 b.n 8007bb2 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8007bb0: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007bb2: 4618 mov r0, r3
|
|
8007bb4: 370c adds r7, #12
|
|
8007bb6: 46bd mov sp, r7
|
|
8007bb8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007bbc: 4770 bx lr
|
|
|
|
08007bbe <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
8007bbe: b480 push {r7}
|
|
8007bc0: b085 sub sp, #20
|
|
8007bc2: af00 add r7, sp, #0
|
|
8007bc4: 6078 str r0, [r7, #4]
|
|
8007bc6: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8007bc8: 687b ldr r3, [r7, #4]
|
|
8007bca: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
8007bce: b2db uxtb r3, r3
|
|
8007bd0: 2b20 cmp r3, #32
|
|
8007bd2: d139 bne.n 8007c48 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8007bd4: 687b ldr r3, [r7, #4]
|
|
8007bd6: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
8007bda: 2b01 cmp r3, #1
|
|
8007bdc: d101 bne.n 8007be2 <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
8007bde: 2302 movs r3, #2
|
|
8007be0: e033 b.n 8007c4a <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
8007be2: 687b ldr r3, [r7, #4]
|
|
8007be4: 2201 movs r2, #1
|
|
8007be6: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8007bea: 687b ldr r3, [r7, #4]
|
|
8007bec: 2224 movs r2, #36 ; 0x24
|
|
8007bee: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8007bf2: 687b ldr r3, [r7, #4]
|
|
8007bf4: 681b ldr r3, [r3, #0]
|
|
8007bf6: 681a ldr r2, [r3, #0]
|
|
8007bf8: 687b ldr r3, [r7, #4]
|
|
8007bfa: 681b ldr r3, [r3, #0]
|
|
8007bfc: f022 0201 bic.w r2, r2, #1
|
|
8007c00: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
8007c02: 687b ldr r3, [r7, #4]
|
|
8007c04: 681b ldr r3, [r3, #0]
|
|
8007c06: 681b ldr r3, [r3, #0]
|
|
8007c08: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
8007c0a: 68fb ldr r3, [r7, #12]
|
|
8007c0c: f423 6370 bic.w r3, r3, #3840 ; 0xf00
|
|
8007c10: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
8007c12: 683b ldr r3, [r7, #0]
|
|
8007c14: 021b lsls r3, r3, #8
|
|
8007c16: 68fa ldr r2, [r7, #12]
|
|
8007c18: 4313 orrs r3, r2
|
|
8007c1a: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
8007c1c: 687b ldr r3, [r7, #4]
|
|
8007c1e: 681b ldr r3, [r3, #0]
|
|
8007c20: 68fa ldr r2, [r7, #12]
|
|
8007c22: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8007c24: 687b ldr r3, [r7, #4]
|
|
8007c26: 681b ldr r3, [r3, #0]
|
|
8007c28: 681a ldr r2, [r3, #0]
|
|
8007c2a: 687b ldr r3, [r7, #4]
|
|
8007c2c: 681b ldr r3, [r3, #0]
|
|
8007c2e: f042 0201 orr.w r2, r2, #1
|
|
8007c32: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8007c34: 687b ldr r3, [r7, #4]
|
|
8007c36: 2220 movs r2, #32
|
|
8007c38: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8007c3c: 687b ldr r3, [r7, #4]
|
|
8007c3e: 2200 movs r2, #0
|
|
8007c40: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
8007c44: 2300 movs r3, #0
|
|
8007c46: e000 b.n 8007c4a <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8007c48: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8007c4a: 4618 mov r0, r3
|
|
8007c4c: 3714 adds r7, #20
|
|
8007c4e: 46bd mov sp, r7
|
|
8007c50: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c54: 4770 bx lr
|
|
|
|
08007c56 <HAL_PWR_EnableBkUpAccess>:
|
|
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
|
|
* back-up domain.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
8007c56: b480 push {r7}
|
|
8007c58: af00 add r7, sp, #0
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8007c5a: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007c5e: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007c62: 681a ldr r2, [r3, #0]
|
|
8007c64: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007c68: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007c6c: f442 7280 orr.w r2, r2, #256 ; 0x100
|
|
8007c70: 601a str r2, [r3, #0]
|
|
}
|
|
8007c72: bf00 nop
|
|
8007c74: 46bd mov sp, r7
|
|
8007c76: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c7a: 4770 bx lr
|
|
|
|
08007c7c <HAL_PWR_EnterSTOPMode>:
|
|
* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
|
|
* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
|
{
|
|
8007c7c: b580 push {r7, lr}
|
|
8007c7e: b082 sub sp, #8
|
|
8007c80: af00 add r7, sp, #0
|
|
8007c82: 6078 str r0, [r7, #4]
|
|
8007c84: 460b mov r3, r1
|
|
8007c86: 70fb strb r3, [r7, #3]
|
|
/* Check the parameters */
|
|
assert_param(IS_PWR_REGULATOR(Regulator));
|
|
|
|
if(Regulator == PWR_LOWPOWERREGULATOR_ON)
|
|
8007c88: 687b ldr r3, [r7, #4]
|
|
8007c8a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
|
|
8007c8e: d104 bne.n 8007c9a <HAL_PWR_EnterSTOPMode+0x1e>
|
|
{
|
|
HAL_PWREx_EnterSTOP1Mode(STOPEntry);
|
|
8007c90: 78fb ldrb r3, [r7, #3]
|
|
8007c92: 4618 mov r0, r3
|
|
8007c94: f000 f8bb bl 8007e0e <HAL_PWREx_EnterSTOP1Mode>
|
|
}
|
|
else
|
|
{
|
|
HAL_PWREx_EnterSTOP0Mode(STOPEntry);
|
|
}
|
|
}
|
|
8007c98: e003 b.n 8007ca2 <HAL_PWR_EnterSTOPMode+0x26>
|
|
HAL_PWREx_EnterSTOP0Mode(STOPEntry);
|
|
8007c9a: 78fb ldrb r3, [r7, #3]
|
|
8007c9c: 4618 mov r0, r3
|
|
8007c9e: f000 f87f bl 8007da0 <HAL_PWREx_EnterSTOP0Mode>
|
|
}
|
|
8007ca2: bf00 nop
|
|
8007ca4: 3708 adds r7, #8
|
|
8007ca6: 46bd mov sp, r7
|
|
8007ca8: bd80 pop {r7, pc}
|
|
|
|
08007caa <HAL_PWREx_GetVoltageRange>:
|
|
* @brief Return Voltage Scaling Range.
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
|
|
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
|
|
*/
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
{
|
|
8007caa: b480 push {r7}
|
|
8007cac: af00 add r7, sp, #0
|
|
else
|
|
{
|
|
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
|
|
}
|
|
#else
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
8007cae: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007cb2: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007cb6: 681b ldr r3, [r3, #0]
|
|
8007cb8: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
|
#endif
|
|
}
|
|
8007cbc: 4618 mov r0, r3
|
|
8007cbe: 46bd mov sp, r7
|
|
8007cc0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007cc4: 4770 bx lr
|
|
|
|
08007cc6 <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
8007cc6: b480 push {r7}
|
|
8007cc8: b085 sub sp, #20
|
|
8007cca: af00 add r7, sp, #0
|
|
8007ccc: 6078 str r0, [r7, #4]
|
|
}
|
|
|
|
#else
|
|
|
|
/* If Set Range 1 */
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8007cce: 687b ldr r3, [r7, #4]
|
|
8007cd0: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
8007cd4: d145 bne.n 8007d62 <HAL_PWREx_ControlVoltageScaling+0x9c>
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8007cd6: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007cda: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007cde: 681b ldr r3, [r3, #0]
|
|
8007ce0: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
|
8007ce4: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
8007ce8: d053 beq.n 8007d92 <HAL_PWREx_ControlVoltageScaling+0xcc>
|
|
{
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8007cea: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007cee: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007cf2: 681b ldr r3, [r3, #0]
|
|
8007cf4: f423 62c0 bic.w r2, r3, #1536 ; 0x600
|
|
8007cf8: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007cfc: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007d00: f442 7200 orr.w r2, r2, #512 ; 0x200
|
|
8007d04: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
8007d06: f240 234c movw r3, #588 ; 0x24c
|
|
8007d0a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8007d0e: 681b ldr r3, [r3, #0]
|
|
8007d10: 2232 movs r2, #50 ; 0x32
|
|
8007d12: fb02 f203 mul.w r2, r2, r3
|
|
8007d16: f64d 6383 movw r3, #56963 ; 0xde83
|
|
8007d1a: f2c4 331b movt r3, #17179 ; 0x431b
|
|
8007d1e: fba3 2302 umull r2, r3, r3, r2
|
|
8007d22: 0c9b lsrs r3, r3, #18
|
|
8007d24: 3301 adds r3, #1
|
|
8007d26: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8007d28: e002 b.n 8007d30 <HAL_PWREx_ControlVoltageScaling+0x6a>
|
|
{
|
|
wait_loop_index--;
|
|
8007d2a: 68fb ldr r3, [r7, #12]
|
|
8007d2c: 3b01 subs r3, #1
|
|
8007d2e: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8007d30: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007d34: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007d38: 695b ldr r3, [r3, #20]
|
|
8007d3a: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8007d3e: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
8007d42: d102 bne.n 8007d4a <HAL_PWREx_ControlVoltageScaling+0x84>
|
|
8007d44: 68fb ldr r3, [r7, #12]
|
|
8007d46: 2b00 cmp r3, #0
|
|
8007d48: d1ef bne.n 8007d2a <HAL_PWREx_ControlVoltageScaling+0x64>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
8007d4a: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007d4e: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007d52: 695b ldr r3, [r3, #20]
|
|
8007d54: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8007d58: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
8007d5c: d119 bne.n 8007d92 <HAL_PWREx_ControlVoltageScaling+0xcc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8007d5e: 2303 movs r3, #3
|
|
8007d60: e018 b.n 8007d94 <HAL_PWREx_ControlVoltageScaling+0xce>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
8007d62: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007d66: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007d6a: 681b ldr r3, [r3, #0]
|
|
8007d6c: f403 63c0 and.w r3, r3, #1536 ; 0x600
|
|
8007d70: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
8007d74: d00d beq.n 8007d92 <HAL_PWREx_ControlVoltageScaling+0xcc>
|
|
{
|
|
/* Set Range 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
8007d76: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007d7a: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007d7e: 681b ldr r3, [r3, #0]
|
|
8007d80: f423 62c0 bic.w r2, r3, #1536 ; 0x600
|
|
8007d84: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007d88: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007d8c: f442 6280 orr.w r2, r2, #1024 ; 0x400
|
|
8007d90: 601a str r2, [r3, #0]
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return HAL_OK;
|
|
8007d92: 2300 movs r3, #0
|
|
}
|
|
8007d94: 4618 mov r0, r3
|
|
8007d96: 3714 adds r7, #20
|
|
8007d98: 46bd mov sp, r7
|
|
8007d9a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007d9e: 4770 bx lr
|
|
|
|
08007da0 <HAL_PWREx_EnterSTOP0Mode>:
|
|
* @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
|
|
* @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
|
|
{
|
|
8007da0: b480 push {r7}
|
|
8007da2: b083 sub sp, #12
|
|
8007da4: af00 add r7, sp, #0
|
|
8007da6: 4603 mov r3, r0
|
|
8007da8: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
|
|
|
/* Stop 0 mode with Main Regulator */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
|
|
8007daa: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007dae: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007db2: 681a ldr r2, [r3, #0]
|
|
8007db4: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007db8: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007dbc: f022 0207 bic.w r2, r2, #7
|
|
8007dc0: 601a str r2, [r3, #0]
|
|
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
8007dc2: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007dc6: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007dca: 691a ldr r2, [r3, #16]
|
|
8007dcc: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007dd0: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007dd4: f042 0204 orr.w r2, r2, #4
|
|
8007dd8: 611a str r2, [r3, #16]
|
|
|
|
/* Select Stop mode entry --------------------------------------------------*/
|
|
if(STOPEntry == PWR_STOPENTRY_WFI)
|
|
8007dda: 79fb ldrb r3, [r7, #7]
|
|
8007ddc: 2b01 cmp r3, #1
|
|
8007dde: d101 bne.n 8007de4 <HAL_PWREx_EnterSTOP0Mode+0x44>
|
|
{
|
|
/* Request Wait For Interrupt */
|
|
__WFI();
|
|
8007de0: bf30 wfi
|
|
8007de2: e002 b.n 8007dea <HAL_PWREx_EnterSTOP0Mode+0x4a>
|
|
}
|
|
else
|
|
{
|
|
/* Request Wait For Event */
|
|
__SEV();
|
|
8007de4: bf40 sev
|
|
__WFE();
|
|
8007de6: bf20 wfe
|
|
__WFE();
|
|
8007de8: bf20 wfe
|
|
}
|
|
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
8007dea: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007dee: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007df2: 691a ldr r2, [r3, #16]
|
|
8007df4: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007df8: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007dfc: f022 0204 bic.w r2, r2, #4
|
|
8007e00: 611a str r2, [r3, #16]
|
|
}
|
|
8007e02: bf00 nop
|
|
8007e04: 370c adds r7, #12
|
|
8007e06: 46bd mov sp, r7
|
|
8007e08: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e0c: 4770 bx lr
|
|
|
|
08007e0e <HAL_PWREx_EnterSTOP1Mode>:
|
|
* @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
|
|
* @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
|
|
* @retval None
|
|
*/
|
|
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
|
|
{
|
|
8007e0e: b480 push {r7}
|
|
8007e10: b083 sub sp, #12
|
|
8007e12: af00 add r7, sp, #0
|
|
8007e14: 4603 mov r3, r0
|
|
8007e16: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
|
|
|
/* Stop 1 mode with Low-Power Regulator */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
|
|
8007e18: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007e1c: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007e20: 681b ldr r3, [r3, #0]
|
|
8007e22: f023 0207 bic.w r2, r3, #7
|
|
8007e26: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8007e2a: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8007e2e: f042 0201 orr.w r2, r2, #1
|
|
8007e32: 601a str r2, [r3, #0]
|
|
|
|
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
8007e34: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007e38: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007e3c: 691a ldr r2, [r3, #16]
|
|
8007e3e: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007e42: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007e46: f042 0204 orr.w r2, r2, #4
|
|
8007e4a: 611a str r2, [r3, #16]
|
|
|
|
/* Select Stop mode entry --------------------------------------------------*/
|
|
if(STOPEntry == PWR_STOPENTRY_WFI)
|
|
8007e4c: 79fb ldrb r3, [r7, #7]
|
|
8007e4e: 2b01 cmp r3, #1
|
|
8007e50: d101 bne.n 8007e56 <HAL_PWREx_EnterSTOP1Mode+0x48>
|
|
{
|
|
/* Request Wait For Interrupt */
|
|
__WFI();
|
|
8007e52: bf30 wfi
|
|
8007e54: e002 b.n 8007e5c <HAL_PWREx_EnterSTOP1Mode+0x4e>
|
|
}
|
|
else
|
|
{
|
|
/* Request Wait For Event */
|
|
__SEV();
|
|
8007e56: bf40 sev
|
|
__WFE();
|
|
8007e58: bf20 wfe
|
|
__WFE();
|
|
8007e5a: bf20 wfe
|
|
}
|
|
|
|
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
|
8007e5c: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007e60: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007e64: 691a ldr r2, [r3, #16]
|
|
8007e66: f44f 436d mov.w r3, #60672 ; 0xed00
|
|
8007e6a: f2ce 0300 movt r3, #57344 ; 0xe000
|
|
8007e6e: f022 0204 bic.w r2, r2, #4
|
|
8007e72: 611a str r2, [r3, #16]
|
|
}
|
|
8007e74: bf00 nop
|
|
8007e76: 370c adds r7, #12
|
|
8007e78: 46bd mov sp, r7
|
|
8007e7a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e7e: 4770 bx lr
|
|
|
|
08007e80 <HAL_RCC_OscConfig>:
|
|
* supported by this macro. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8007e80: b580 push {r7, lr}
|
|
8007e82: b088 sub sp, #32
|
|
8007e84: af00 add r7, sp, #0
|
|
8007e86: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status;
|
|
uint32_t sysclk_source, pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8007e88: 687b ldr r3, [r7, #4]
|
|
8007e8a: 2b00 cmp r3, #0
|
|
8007e8c: d102 bne.n 8007e94 <HAL_RCC_OscConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8007e8e: 2301 movs r3, #1
|
|
8007e90: f000 bd26 b.w 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8007e94: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007e98: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007e9c: 689b ldr r3, [r3, #8]
|
|
8007e9e: f003 030c and.w r3, r3, #12
|
|
8007ea2: 61bb str r3, [r7, #24]
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8007ea4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007ea8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007eac: 68db ldr r3, [r3, #12]
|
|
8007eae: f003 0303 and.w r3, r3, #3
|
|
8007eb2: 617b str r3, [r7, #20]
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
8007eb4: 687b ldr r3, [r7, #4]
|
|
8007eb6: 681b ldr r3, [r3, #0]
|
|
8007eb8: f003 0310 and.w r3, r3, #16
|
|
8007ebc: 2b00 cmp r3, #0
|
|
8007ebe: f000 8149 beq.w 8008154 <HAL_RCC_OscConfig+0x2d4>
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
8007ec2: 69bb ldr r3, [r7, #24]
|
|
8007ec4: 2b00 cmp r3, #0
|
|
8007ec6: d007 beq.n 8007ed8 <HAL_RCC_OscConfig+0x58>
|
|
8007ec8: 69bb ldr r3, [r7, #24]
|
|
8007eca: 2b0c cmp r3, #12
|
|
8007ecc: f040 80cb bne.w 8008066 <HAL_RCC_OscConfig+0x1e6>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
|
|
8007ed0: 697b ldr r3, [r7, #20]
|
|
8007ed2: 2b01 cmp r3, #1
|
|
8007ed4: f040 80c7 bne.w 8008066 <HAL_RCC_OscConfig+0x1e6>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8007ed8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007edc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007ee0: 681b ldr r3, [r3, #0]
|
|
8007ee2: f003 0302 and.w r3, r3, #2
|
|
8007ee6: 2b00 cmp r3, #0
|
|
8007ee8: d006 beq.n 8007ef8 <HAL_RCC_OscConfig+0x78>
|
|
8007eea: 687b ldr r3, [r7, #4]
|
|
8007eec: 699b ldr r3, [r3, #24]
|
|
8007eee: 2b00 cmp r3, #0
|
|
8007ef0: d102 bne.n 8007ef8 <HAL_RCC_OscConfig+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8007ef2: 2301 movs r3, #1
|
|
8007ef4: f000 bcf4 b.w 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
else
|
|
{
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
8007ef8: 687b ldr r3, [r7, #4]
|
|
8007efa: 6a1a ldr r2, [r3, #32]
|
|
8007efc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f00: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f04: 681b ldr r3, [r3, #0]
|
|
8007f06: f003 0308 and.w r3, r3, #8
|
|
8007f0a: 2b00 cmp r3, #0
|
|
8007f0c: d007 beq.n 8007f1e <HAL_RCC_OscConfig+0x9e>
|
|
8007f0e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f12: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f16: 681b ldr r3, [r3, #0]
|
|
8007f18: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
8007f1c: e008 b.n 8007f30 <HAL_RCC_OscConfig+0xb0>
|
|
8007f1e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f22: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f26: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
8007f2a: 091b lsrs r3, r3, #4
|
|
8007f2c: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
8007f30: 4293 cmp r3, r2
|
|
8007f32: d236 bcs.n 8007fa2 <HAL_RCC_OscConfig+0x122>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8007f34: 687b ldr r3, [r7, #4]
|
|
8007f36: 6a1b ldr r3, [r3, #32]
|
|
8007f38: 4618 mov r0, r3
|
|
8007f3a: f000 fee0 bl 8008cfe <RCC_SetFlashLatencyFromMSIRange>
|
|
8007f3e: 4603 mov r3, r0
|
|
8007f40: 2b00 cmp r3, #0
|
|
8007f42: d002 beq.n 8007f4a <HAL_RCC_OscConfig+0xca>
|
|
{
|
|
return HAL_ERROR;
|
|
8007f44: 2301 movs r3, #1
|
|
8007f46: f000 bccb b.w 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8007f4a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f4e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f52: 681a ldr r2, [r3, #0]
|
|
8007f54: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f58: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f5c: f042 0208 orr.w r2, r2, #8
|
|
8007f60: 601a str r2, [r3, #0]
|
|
8007f62: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f66: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f6a: 681b ldr r3, [r3, #0]
|
|
8007f6c: f023 01f0 bic.w r1, r3, #240 ; 0xf0
|
|
8007f70: 687b ldr r3, [r7, #4]
|
|
8007f72: 6a1a ldr r2, [r3, #32]
|
|
8007f74: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f78: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f7c: 430a orrs r2, r1
|
|
8007f7e: 601a str r2, [r3, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8007f80: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f84: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f88: 685b ldr r3, [r3, #4]
|
|
8007f8a: f423 417f bic.w r1, r3, #65280 ; 0xff00
|
|
8007f8e: 687b ldr r3, [r7, #4]
|
|
8007f90: 69db ldr r3, [r3, #28]
|
|
8007f92: 021a lsls r2, r3, #8
|
|
8007f94: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007f98: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007f9c: 430a orrs r2, r1
|
|
8007f9e: 605a str r2, [r3, #4]
|
|
8007fa0: e038 b.n 8008014 <HAL_RCC_OscConfig+0x194>
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8007fa2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007fa6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007faa: 681a ldr r2, [r3, #0]
|
|
8007fac: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007fb0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007fb4: f042 0208 orr.w r2, r2, #8
|
|
8007fb8: 601a str r2, [r3, #0]
|
|
8007fba: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007fbe: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007fc2: 681b ldr r3, [r3, #0]
|
|
8007fc4: f023 01f0 bic.w r1, r3, #240 ; 0xf0
|
|
8007fc8: 687b ldr r3, [r7, #4]
|
|
8007fca: 6a1a ldr r2, [r3, #32]
|
|
8007fcc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007fd0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007fd4: 430a orrs r2, r1
|
|
8007fd6: 601a str r2, [r3, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8007fd8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007fdc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007fe0: 685b ldr r3, [r3, #4]
|
|
8007fe2: f423 417f bic.w r1, r3, #65280 ; 0xff00
|
|
8007fe6: 687b ldr r3, [r7, #4]
|
|
8007fe8: 69db ldr r3, [r3, #28]
|
|
8007fea: 021a lsls r2, r3, #8
|
|
8007fec: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8007ff0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8007ff4: 430a orrs r2, r1
|
|
8007ff6: 605a str r2, [r3, #4]
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
/* Only possible when MSI is the System clock source */
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8007ff8: 69bb ldr r3, [r7, #24]
|
|
8007ffa: 2b00 cmp r3, #0
|
|
8007ffc: d10a bne.n 8008014 <HAL_RCC_OscConfig+0x194>
|
|
{
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
8007ffe: 687b ldr r3, [r7, #4]
|
|
8008000: 6a1b ldr r3, [r3, #32]
|
|
8008002: 4618 mov r0, r3
|
|
8008004: f000 fe7b bl 8008cfe <RCC_SetFlashLatencyFromMSIRange>
|
|
8008008: 4603 mov r3, r0
|
|
800800a: 2b00 cmp r3, #0
|
|
800800c: d002 beq.n 8008014 <HAL_RCC_OscConfig+0x194>
|
|
{
|
|
return HAL_ERROR;
|
|
800800e: 2301 movs r3, #1
|
|
8008010: f000 bc66 b.w 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8008014: f000 fd8a bl 8008b2c <HAL_RCC_GetSysClockFreq>
|
|
8008018: 4601 mov r1, r0
|
|
800801a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800801e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008022: 689b ldr r3, [r3, #8]
|
|
8008024: 091b lsrs r3, r3, #4
|
|
8008026: f003 020f and.w r2, r3, #15
|
|
800802a: f24e 33ac movw r3, #58284 ; 0xe3ac
|
|
800802e: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8008032: 5c9b ldrb r3, [r3, r2]
|
|
8008034: f003 031f and.w r3, r3, #31
|
|
8008038: fa21 f203 lsr.w r2, r1, r3
|
|
800803c: f240 234c movw r3, #588 ; 0x24c
|
|
8008040: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8008044: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
8008046: f240 2350 movw r3, #592 ; 0x250
|
|
800804a: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
800804e: 681b ldr r3, [r3, #0]
|
|
8008050: 4618 mov r0, r3
|
|
8008052: f7fc fc81 bl 8004958 <HAL_InitTick>
|
|
8008056: 4603 mov r3, r0
|
|
8008058: 73fb strb r3, [r7, #15]
|
|
if(status != HAL_OK)
|
|
800805a: 7bfb ldrb r3, [r7, #15]
|
|
800805c: 2b00 cmp r3, #0
|
|
800805e: d078 beq.n 8008152 <HAL_RCC_OscConfig+0x2d2>
|
|
{
|
|
return status;
|
|
8008060: 7bfb ldrb r3, [r7, #15]
|
|
8008062: f000 bc3d b.w 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the MSI State */
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
8008066: 687b ldr r3, [r7, #4]
|
|
8008068: 699b ldr r3, [r3, #24]
|
|
800806a: 2b00 cmp r3, #0
|
|
800806c: d04e beq.n 800810c <HAL_RCC_OscConfig+0x28c>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
800806e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008072: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008076: 681a ldr r2, [r3, #0]
|
|
8008078: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800807c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008080: f042 0201 orr.w r2, r2, #1
|
|
8008084: 601a str r2, [r3, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8008086: f7fc fcc0 bl 8004a0a <HAL_GetTick>
|
|
800808a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
800808c: e009 b.n 80080a2 <HAL_RCC_OscConfig+0x222>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
800808e: f7fc fcbc bl 8004a0a <HAL_GetTick>
|
|
8008092: 4602 mov r2, r0
|
|
8008094: 693b ldr r3, [r7, #16]
|
|
8008096: 1ad3 subs r3, r2, r3
|
|
8008098: 2b02 cmp r3, #2
|
|
800809a: d902 bls.n 80080a2 <HAL_RCC_OscConfig+0x222>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800809c: 2303 movs r3, #3
|
|
800809e: f000 bc1f b.w 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
80080a2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80080a6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80080aa: 681b ldr r3, [r3, #0]
|
|
80080ac: f003 0302 and.w r3, r3, #2
|
|
80080b0: 2b00 cmp r3, #0
|
|
80080b2: d0ec beq.n 800808e <HAL_RCC_OscConfig+0x20e>
|
|
}
|
|
}
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
80080b4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80080b8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80080bc: 681a ldr r2, [r3, #0]
|
|
80080be: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80080c2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80080c6: f042 0208 orr.w r2, r2, #8
|
|
80080ca: 601a str r2, [r3, #0]
|
|
80080cc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80080d0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80080d4: 681b ldr r3, [r3, #0]
|
|
80080d6: f023 01f0 bic.w r1, r3, #240 ; 0xf0
|
|
80080da: 687b ldr r3, [r7, #4]
|
|
80080dc: 6a1a ldr r2, [r3, #32]
|
|
80080de: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80080e2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80080e6: 430a orrs r2, r1
|
|
80080e8: 601a str r2, [r3, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
80080ea: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80080ee: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80080f2: 685b ldr r3, [r3, #4]
|
|
80080f4: f423 417f bic.w r1, r3, #65280 ; 0xff00
|
|
80080f8: 687b ldr r3, [r7, #4]
|
|
80080fa: 69db ldr r3, [r3, #28]
|
|
80080fc: 021a lsls r2, r3, #8
|
|
80080fe: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008102: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008106: 430a orrs r2, r1
|
|
8008108: 605a str r2, [r3, #4]
|
|
800810a: e023 b.n 8008154 <HAL_RCC_OscConfig+0x2d4>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
800810c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008110: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008114: 681a ldr r2, [r3, #0]
|
|
8008116: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800811a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800811e: f022 0201 bic.w r2, r2, #1
|
|
8008122: 601a str r2, [r3, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8008124: f7fc fc71 bl 8004a0a <HAL_GetTick>
|
|
8008128: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
800812a: e008 b.n 800813e <HAL_RCC_OscConfig+0x2be>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
800812c: f7fc fc6d bl 8004a0a <HAL_GetTick>
|
|
8008130: 4602 mov r2, r0
|
|
8008132: 693b ldr r3, [r7, #16]
|
|
8008134: 1ad3 subs r3, r2, r3
|
|
8008136: 2b02 cmp r3, #2
|
|
8008138: d901 bls.n 800813e <HAL_RCC_OscConfig+0x2be>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800813a: 2303 movs r3, #3
|
|
800813c: e3d0 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
800813e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008142: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008146: 681b ldr r3, [r3, #0]
|
|
8008148: f003 0302 and.w r3, r3, #2
|
|
800814c: 2b00 cmp r3, #0
|
|
800814e: d1ed bne.n 800812c <HAL_RCC_OscConfig+0x2ac>
|
|
8008150: e000 b.n 8008154 <HAL_RCC_OscConfig+0x2d4>
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8008152: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8008154: 687b ldr r3, [r7, #4]
|
|
8008156: 681b ldr r3, [r3, #0]
|
|
8008158: f003 0301 and.w r3, r3, #1
|
|
800815c: 2b00 cmp r3, #0
|
|
800815e: f000 8093 beq.w 8008288 <HAL_RCC_OscConfig+0x408>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
|
|
8008162: 69bb ldr r3, [r7, #24]
|
|
8008164: 2b08 cmp r3, #8
|
|
8008166: d005 beq.n 8008174 <HAL_RCC_OscConfig+0x2f4>
|
|
8008168: 69bb ldr r3, [r7, #24]
|
|
800816a: 2b0c cmp r3, #12
|
|
800816c: d111 bne.n 8008192 <HAL_RCC_OscConfig+0x312>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
800816e: 697b ldr r3, [r7, #20]
|
|
8008170: 2b03 cmp r3, #3
|
|
8008172: d10e bne.n 8008192 <HAL_RCC_OscConfig+0x312>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8008174: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008178: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800817c: 681b ldr r3, [r3, #0]
|
|
800817e: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8008182: 2b00 cmp r3, #0
|
|
8008184: d07f beq.n 8008286 <HAL_RCC_OscConfig+0x406>
|
|
8008186: 687b ldr r3, [r7, #4]
|
|
8008188: 685b ldr r3, [r3, #4]
|
|
800818a: 2b00 cmp r3, #0
|
|
800818c: d17b bne.n 8008286 <HAL_RCC_OscConfig+0x406>
|
|
{
|
|
return HAL_ERROR;
|
|
800818e: 2301 movs r3, #1
|
|
8008190: e3a6 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8008192: 687b ldr r3, [r7, #4]
|
|
8008194: 685b ldr r3, [r3, #4]
|
|
8008196: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
800819a: d10c bne.n 80081b6 <HAL_RCC_OscConfig+0x336>
|
|
800819c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80081a0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80081a4: 681a ldr r2, [r3, #0]
|
|
80081a6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80081aa: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80081ae: f442 3280 orr.w r2, r2, #65536 ; 0x10000
|
|
80081b2: 601a str r2, [r3, #0]
|
|
80081b4: e035 b.n 8008222 <HAL_RCC_OscConfig+0x3a2>
|
|
80081b6: 687b ldr r3, [r7, #4]
|
|
80081b8: 685b ldr r3, [r3, #4]
|
|
80081ba: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
80081be: d118 bne.n 80081f2 <HAL_RCC_OscConfig+0x372>
|
|
80081c0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80081c4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80081c8: 681a ldr r2, [r3, #0]
|
|
80081ca: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80081ce: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80081d2: f442 2280 orr.w r2, r2, #262144 ; 0x40000
|
|
80081d6: 601a str r2, [r3, #0]
|
|
80081d8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80081dc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80081e0: 681a ldr r2, [r3, #0]
|
|
80081e2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80081e6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80081ea: f442 3280 orr.w r2, r2, #65536 ; 0x10000
|
|
80081ee: 601a str r2, [r3, #0]
|
|
80081f0: e017 b.n 8008222 <HAL_RCC_OscConfig+0x3a2>
|
|
80081f2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80081f6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80081fa: 681a ldr r2, [r3, #0]
|
|
80081fc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008200: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008204: f422 3280 bic.w r2, r2, #65536 ; 0x10000
|
|
8008208: 601a str r2, [r3, #0]
|
|
800820a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800820e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008212: 681a ldr r2, [r3, #0]
|
|
8008214: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008218: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800821c: f422 2280 bic.w r2, r2, #262144 ; 0x40000
|
|
8008220: 601a str r2, [r3, #0]
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8008222: 687b ldr r3, [r7, #4]
|
|
8008224: 685b ldr r3, [r3, #4]
|
|
8008226: 2b00 cmp r3, #0
|
|
8008228: d016 beq.n 8008258 <HAL_RCC_OscConfig+0x3d8>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800822a: f7fc fbee bl 8004a0a <HAL_GetTick>
|
|
800822e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8008230: e008 b.n 8008244 <HAL_RCC_OscConfig+0x3c4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8008232: f7fc fbea bl 8004a0a <HAL_GetTick>
|
|
8008236: 4602 mov r2, r0
|
|
8008238: 693b ldr r3, [r7, #16]
|
|
800823a: 1ad3 subs r3, r2, r3
|
|
800823c: 2b64 cmp r3, #100 ; 0x64
|
|
800823e: d901 bls.n 8008244 <HAL_RCC_OscConfig+0x3c4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8008240: 2303 movs r3, #3
|
|
8008242: e34d b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8008244: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008248: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800824c: 681b ldr r3, [r3, #0]
|
|
800824e: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8008252: 2b00 cmp r3, #0
|
|
8008254: d0ed beq.n 8008232 <HAL_RCC_OscConfig+0x3b2>
|
|
8008256: e017 b.n 8008288 <HAL_RCC_OscConfig+0x408>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8008258: f7fc fbd7 bl 8004a0a <HAL_GetTick>
|
|
800825c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
800825e: e008 b.n 8008272 <HAL_RCC_OscConfig+0x3f2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8008260: f7fc fbd3 bl 8004a0a <HAL_GetTick>
|
|
8008264: 4602 mov r2, r0
|
|
8008266: 693b ldr r3, [r7, #16]
|
|
8008268: 1ad3 subs r3, r2, r3
|
|
800826a: 2b64 cmp r3, #100 ; 0x64
|
|
800826c: d901 bls.n 8008272 <HAL_RCC_OscConfig+0x3f2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800826e: 2303 movs r3, #3
|
|
8008270: e336 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8008272: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008276: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800827a: 681b ldr r3, [r3, #0]
|
|
800827c: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8008280: 2b00 cmp r3, #0
|
|
8008282: d1ed bne.n 8008260 <HAL_RCC_OscConfig+0x3e0>
|
|
8008284: e000 b.n 8008288 <HAL_RCC_OscConfig+0x408>
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8008286: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8008288: 687b ldr r3, [r7, #4]
|
|
800828a: 681b ldr r3, [r3, #0]
|
|
800828c: f003 0302 and.w r3, r3, #2
|
|
8008290: 2b00 cmp r3, #0
|
|
8008292: f000 8082 beq.w 800839a <HAL_RCC_OscConfig+0x51a>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
|
|
8008296: 69bb ldr r3, [r7, #24]
|
|
8008298: 2b04 cmp r3, #4
|
|
800829a: d005 beq.n 80082a8 <HAL_RCC_OscConfig+0x428>
|
|
800829c: 69bb ldr r3, [r7, #24]
|
|
800829e: 2b0c cmp r3, #12
|
|
80082a0: d122 bne.n 80082e8 <HAL_RCC_OscConfig+0x468>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
80082a2: 697b ldr r3, [r7, #20]
|
|
80082a4: 2b02 cmp r3, #2
|
|
80082a6: d11f bne.n 80082e8 <HAL_RCC_OscConfig+0x468>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
80082a8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80082ac: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80082b0: 681b ldr r3, [r3, #0]
|
|
80082b2: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
80082b6: 2b00 cmp r3, #0
|
|
80082b8: d005 beq.n 80082c6 <HAL_RCC_OscConfig+0x446>
|
|
80082ba: 687b ldr r3, [r7, #4]
|
|
80082bc: 68db ldr r3, [r3, #12]
|
|
80082be: 2b00 cmp r3, #0
|
|
80082c0: d101 bne.n 80082c6 <HAL_RCC_OscConfig+0x446>
|
|
{
|
|
return HAL_ERROR;
|
|
80082c2: 2301 movs r3, #1
|
|
80082c4: e30c b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
80082c6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80082ca: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80082ce: 685b ldr r3, [r3, #4]
|
|
80082d0: f023 51f8 bic.w r1, r3, #520093696 ; 0x1f000000
|
|
80082d4: 687b ldr r3, [r7, #4]
|
|
80082d6: 691b ldr r3, [r3, #16]
|
|
80082d8: 061a lsls r2, r3, #24
|
|
80082da: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80082de: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80082e2: 430a orrs r2, r1
|
|
80082e4: 605a str r2, [r3, #4]
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
80082e6: e058 b.n 800839a <HAL_RCC_OscConfig+0x51a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
80082e8: 687b ldr r3, [r7, #4]
|
|
80082ea: 68db ldr r3, [r3, #12]
|
|
80082ec: 2b00 cmp r3, #0
|
|
80082ee: d032 beq.n 8008356 <HAL_RCC_OscConfig+0x4d6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
80082f0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80082f4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80082f8: 681a ldr r2, [r3, #0]
|
|
80082fa: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80082fe: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008302: f442 7280 orr.w r2, r2, #256 ; 0x100
|
|
8008306: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8008308: f7fc fb7f bl 8004a0a <HAL_GetTick>
|
|
800830c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
800830e: e008 b.n 8008322 <HAL_RCC_OscConfig+0x4a2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8008310: f7fc fb7b bl 8004a0a <HAL_GetTick>
|
|
8008314: 4602 mov r2, r0
|
|
8008316: 693b ldr r3, [r7, #16]
|
|
8008318: 1ad3 subs r3, r2, r3
|
|
800831a: 2b02 cmp r3, #2
|
|
800831c: d901 bls.n 8008322 <HAL_RCC_OscConfig+0x4a2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800831e: 2303 movs r3, #3
|
|
8008320: e2de b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8008322: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008326: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800832a: 681b ldr r3, [r3, #0]
|
|
800832c: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8008330: 2b00 cmp r3, #0
|
|
8008332: d0ed beq.n 8008310 <HAL_RCC_OscConfig+0x490>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8008334: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008338: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800833c: 685b ldr r3, [r3, #4]
|
|
800833e: f023 51f8 bic.w r1, r3, #520093696 ; 0x1f000000
|
|
8008342: 687b ldr r3, [r7, #4]
|
|
8008344: 691b ldr r3, [r3, #16]
|
|
8008346: 061a lsls r2, r3, #24
|
|
8008348: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800834c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008350: 430a orrs r2, r1
|
|
8008352: 605a str r2, [r3, #4]
|
|
8008354: e021 b.n 800839a <HAL_RCC_OscConfig+0x51a>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8008356: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800835a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800835e: 681a ldr r2, [r3, #0]
|
|
8008360: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008364: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008368: f422 7280 bic.w r2, r2, #256 ; 0x100
|
|
800836c: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800836e: f7fc fb4c bl 8004a0a <HAL_GetTick>
|
|
8008372: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8008374: e008 b.n 8008388 <HAL_RCC_OscConfig+0x508>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8008376: f7fc fb48 bl 8004a0a <HAL_GetTick>
|
|
800837a: 4602 mov r2, r0
|
|
800837c: 693b ldr r3, [r7, #16]
|
|
800837e: 1ad3 subs r3, r2, r3
|
|
8008380: 2b02 cmp r3, #2
|
|
8008382: d901 bls.n 8008388 <HAL_RCC_OscConfig+0x508>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8008384: 2303 movs r3, #3
|
|
8008386: e2ab b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8008388: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800838c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008390: 681b ldr r3, [r3, #0]
|
|
8008392: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8008396: 2b00 cmp r3, #0
|
|
8008398: d1ed bne.n 8008376 <HAL_RCC_OscConfig+0x4f6>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
800839a: 687b ldr r3, [r7, #4]
|
|
800839c: 681b ldr r3, [r3, #0]
|
|
800839e: f003 0308 and.w r3, r3, #8
|
|
80083a2: 2b00 cmp r3, #0
|
|
80083a4: d04e beq.n 8008444 <HAL_RCC_OscConfig+0x5c4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
80083a6: 687b ldr r3, [r7, #4]
|
|
80083a8: 695b ldr r3, [r3, #20]
|
|
80083aa: 2b00 cmp r3, #0
|
|
80083ac: d025 beq.n 80083fa <HAL_RCC_OscConfig+0x57a>
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
|
|
}
|
|
#endif /* RCC_CSR_LSIPREDIV */
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80083ae: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80083b2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80083b6: f8d3 2094 ldr.w r2, [r3, #148] ; 0x94
|
|
80083ba: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80083be: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80083c2: f042 0201 orr.w r2, r2, #1
|
|
80083c6: f8c3 2094 str.w r2, [r3, #148] ; 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80083ca: f7fc fb1e bl 8004a0a <HAL_GetTick>
|
|
80083ce: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
80083d0: e008 b.n 80083e4 <HAL_RCC_OscConfig+0x564>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80083d2: f7fc fb1a bl 8004a0a <HAL_GetTick>
|
|
80083d6: 4602 mov r2, r0
|
|
80083d8: 693b ldr r3, [r7, #16]
|
|
80083da: 1ad3 subs r3, r2, r3
|
|
80083dc: 2b02 cmp r3, #2
|
|
80083de: d901 bls.n 80083e4 <HAL_RCC_OscConfig+0x564>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80083e0: 2303 movs r3, #3
|
|
80083e2: e27d b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
80083e4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80083e8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80083ec: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
80083f0: f003 0302 and.w r3, r3, #2
|
|
80083f4: 2b00 cmp r3, #0
|
|
80083f6: d0ec beq.n 80083d2 <HAL_RCC_OscConfig+0x552>
|
|
80083f8: e024 b.n 8008444 <HAL_RCC_OscConfig+0x5c4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80083fa: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80083fe: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008402: f8d3 2094 ldr.w r2, [r3, #148] ; 0x94
|
|
8008406: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800840a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800840e: f022 0201 bic.w r2, r2, #1
|
|
8008412: f8c3 2094 str.w r2, [r3, #148] ; 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8008416: f7fc faf8 bl 8004a0a <HAL_GetTick>
|
|
800841a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
800841c: e008 b.n 8008430 <HAL_RCC_OscConfig+0x5b0>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
800841e: f7fc faf4 bl 8004a0a <HAL_GetTick>
|
|
8008422: 4602 mov r2, r0
|
|
8008424: 693b ldr r3, [r7, #16]
|
|
8008426: 1ad3 subs r3, r2, r3
|
|
8008428: 2b02 cmp r3, #2
|
|
800842a: d901 bls.n 8008430 <HAL_RCC_OscConfig+0x5b0>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800842c: 2303 movs r3, #3
|
|
800842e: e257 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8008430: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008434: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008438: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
800843c: f003 0302 and.w r3, r3, #2
|
|
8008440: 2b00 cmp r3, #0
|
|
8008442: d1ec bne.n 800841e <HAL_RCC_OscConfig+0x59e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8008444: 687b ldr r3, [r7, #4]
|
|
8008446: 681b ldr r3, [r3, #0]
|
|
8008448: f003 0304 and.w r3, r3, #4
|
|
800844c: 2b00 cmp r3, #0
|
|
800844e: f000 80e3 beq.w 8008618 <HAL_RCC_OscConfig+0x798>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8008452: 2300 movs r3, #0
|
|
8008454: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
|
|
8008456: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800845a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800845e: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8008460: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8008464: 2b00 cmp r3, #0
|
|
8008466: d116 bne.n 8008496 <HAL_RCC_OscConfig+0x616>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8008468: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800846c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008470: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8008472: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008476: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800847a: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
|
|
800847e: 659a str r2, [r3, #88] ; 0x58
|
|
8008480: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008484: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008488: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
800848a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
800848e: 60bb str r3, [r7, #8]
|
|
8008490: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8008492: 2301 movs r3, #1
|
|
8008494: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8008496: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
800849a: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800849e: 681b ldr r3, [r3, #0]
|
|
80084a0: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
80084a4: 2b00 cmp r3, #0
|
|
80084a6: d121 bne.n 80084ec <HAL_RCC_OscConfig+0x66c>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80084a8: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
80084ac: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
80084b0: 681a ldr r2, [r3, #0]
|
|
80084b2: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
80084b6: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
80084ba: f442 7280 orr.w r2, r2, #256 ; 0x100
|
|
80084be: 601a str r2, [r3, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80084c0: f7fc faa3 bl 8004a0a <HAL_GetTick>
|
|
80084c4: 6138 str r0, [r7, #16]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
80084c6: e008 b.n 80084da <HAL_RCC_OscConfig+0x65a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80084c8: f7fc fa9f bl 8004a0a <HAL_GetTick>
|
|
80084cc: 4602 mov r2, r0
|
|
80084ce: 693b ldr r3, [r7, #16]
|
|
80084d0: 1ad3 subs r3, r2, r3
|
|
80084d2: 2b02 cmp r3, #2
|
|
80084d4: d901 bls.n 80084da <HAL_RCC_OscConfig+0x65a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80084d6: 2303 movs r3, #3
|
|
80084d8: e202 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
80084da: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
80084de: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
80084e2: 681b ldr r3, [r3, #0]
|
|
80084e4: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
80084e8: 2b00 cmp r3, #0
|
|
80084ea: d0ed beq.n 80084c8 <HAL_RCC_OscConfig+0x648>
|
|
{
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
}
|
|
#else
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
80084ec: 687b ldr r3, [r7, #4]
|
|
80084ee: 689b ldr r3, [r3, #8]
|
|
80084f0: 2b01 cmp r3, #1
|
|
80084f2: d10e bne.n 8008512 <HAL_RCC_OscConfig+0x692>
|
|
80084f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80084f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80084fc: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8008500: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008504: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008508: f042 0201 orr.w r2, r2, #1
|
|
800850c: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
8008510: e03c b.n 800858c <HAL_RCC_OscConfig+0x70c>
|
|
8008512: 687b ldr r3, [r7, #4]
|
|
8008514: 689b ldr r3, [r3, #8]
|
|
8008516: 2b05 cmp r3, #5
|
|
8008518: d11c bne.n 8008554 <HAL_RCC_OscConfig+0x6d4>
|
|
800851a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800851e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008522: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8008526: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800852a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800852e: f042 0204 orr.w r2, r2, #4
|
|
8008532: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
8008536: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800853a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800853e: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8008542: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008546: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800854a: f042 0201 orr.w r2, r2, #1
|
|
800854e: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
8008552: e01b b.n 800858c <HAL_RCC_OscConfig+0x70c>
|
|
8008554: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008558: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800855c: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8008560: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008564: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008568: f022 0201 bic.w r2, r2, #1
|
|
800856c: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
8008570: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008574: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008578: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
800857c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008580: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008584: f022 0204 bic.w r2, r2, #4
|
|
8008588: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
800858c: 687b ldr r3, [r7, #4]
|
|
800858e: 689b ldr r3, [r3, #8]
|
|
8008590: 2b00 cmp r3, #0
|
|
8008592: d019 beq.n 80085c8 <HAL_RCC_OscConfig+0x748>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8008594: f7fc fa39 bl 8004a0a <HAL_GetTick>
|
|
8008598: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
800859a: e00a b.n 80085b2 <HAL_RCC_OscConfig+0x732>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800859c: f7fc fa35 bl 8004a0a <HAL_GetTick>
|
|
80085a0: 4602 mov r2, r0
|
|
80085a2: 693b ldr r3, [r7, #16]
|
|
80085a4: 1ad3 subs r3, r2, r3
|
|
80085a6: f241 3288 movw r2, #5000 ; 0x1388
|
|
80085aa: 4293 cmp r3, r2
|
|
80085ac: d901 bls.n 80085b2 <HAL_RCC_OscConfig+0x732>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80085ae: 2303 movs r3, #3
|
|
80085b0: e196 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
80085b2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80085b6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80085ba: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
80085be: f003 0302 and.w r3, r3, #2
|
|
80085c2: 2b00 cmp r3, #0
|
|
80085c4: d0ea beq.n 800859c <HAL_RCC_OscConfig+0x71c>
|
|
80085c6: e018 b.n 80085fa <HAL_RCC_OscConfig+0x77a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80085c8: f7fc fa1f bl 8004a0a <HAL_GetTick>
|
|
80085cc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
80085ce: e00a b.n 80085e6 <HAL_RCC_OscConfig+0x766>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80085d0: f7fc fa1b bl 8004a0a <HAL_GetTick>
|
|
80085d4: 4602 mov r2, r0
|
|
80085d6: 693b ldr r3, [r7, #16]
|
|
80085d8: 1ad3 subs r3, r2, r3
|
|
80085da: f241 3288 movw r2, #5000 ; 0x1388
|
|
80085de: 4293 cmp r3, r2
|
|
80085e0: d901 bls.n 80085e6 <HAL_RCC_OscConfig+0x766>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80085e2: 2303 movs r3, #3
|
|
80085e4: e17c b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
80085e6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80085ea: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80085ee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
80085f2: f003 0302 and.w r3, r3, #2
|
|
80085f6: 2b00 cmp r3, #0
|
|
80085f8: d1ea bne.n 80085d0 <HAL_RCC_OscConfig+0x750>
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
80085fa: 7ffb ldrb r3, [r7, #31]
|
|
80085fc: 2b01 cmp r3, #1
|
|
80085fe: d10b bne.n 8008618 <HAL_RCC_OscConfig+0x798>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8008600: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008604: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008608: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
800860a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800860e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008612: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
|
|
8008616: 659a str r2, [r3, #88] ; 0x58
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8008618: 687b ldr r3, [r7, #4]
|
|
800861a: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800861c: 2b00 cmp r3, #0
|
|
800861e: f000 815e beq.w 80088de <HAL_RCC_OscConfig+0xa5e>
|
|
{
|
|
/* PLL On ? */
|
|
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8008622: 687b ldr r3, [r7, #4]
|
|
8008624: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8008626: 2b02 cmp r3, #2
|
|
8008628: f040 810e bne.w 8008848 <HAL_RCC_OscConfig+0x9c8>
|
|
#endif /* RCC_PLLP_SUPPORT */
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Do nothing if PLL configuration is the unchanged */
|
|
pll_config = RCC->PLLCFGR;
|
|
800862c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008630: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008634: 68db ldr r3, [r3, #12]
|
|
8008636: 617b str r3, [r7, #20]
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8008638: 697b ldr r3, [r7, #20]
|
|
800863a: f003 0203 and.w r2, r3, #3
|
|
800863e: 687b ldr r3, [r7, #4]
|
|
8008640: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8008642: 429a cmp r2, r3
|
|
8008644: d131 bne.n 80086aa <HAL_RCC_OscConfig+0x82a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8008646: 697b ldr r3, [r7, #20]
|
|
8008648: f003 0270 and.w r2, r3, #112 ; 0x70
|
|
800864c: 687b ldr r3, [r7, #4]
|
|
800864e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8008650: 3b01 subs r3, #1
|
|
8008652: 011b lsls r3, r3, #4
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8008654: 429a cmp r2, r3
|
|
8008656: d128 bne.n 80086aa <HAL_RCC_OscConfig+0x82a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8008658: 697b ldr r3, [r7, #20]
|
|
800865a: f403 42fe and.w r2, r3, #32512 ; 0x7f00
|
|
800865e: 687b ldr r3, [r7, #4]
|
|
8008660: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8008662: 021b lsls r3, r3, #8
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8008664: 429a cmp r2, r3
|
|
8008666: d120 bne.n 80086aa <HAL_RCC_OscConfig+0x82a>
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
#else
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8008668: 697b ldr r3, [r7, #20]
|
|
800866a: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
800866e: 687a ldr r2, [r7, #4]
|
|
8008670: 6b92 ldr r2, [r2, #56] ; 0x38
|
|
8008672: 2a07 cmp r2, #7
|
|
8008674: bf14 ite ne
|
|
8008676: 2201 movne r2, #1
|
|
8008678: 2200 moveq r2, #0
|
|
800867a: b2d2 uxtb r2, r2
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
800867c: 4293 cmp r3, r2
|
|
800867e: d114 bne.n 80086aa <HAL_RCC_OscConfig+0x82a>
|
|
#endif
|
|
#endif
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8008680: 697b ldr r3, [r7, #20]
|
|
8008682: f403 02c0 and.w r2, r3, #6291456 ; 0x600000
|
|
8008686: 687b ldr r3, [r7, #4]
|
|
8008688: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800868a: 085b lsrs r3, r3, #1
|
|
800868c: 3b01 subs r3, #1
|
|
800868e: 055b lsls r3, r3, #21
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8008690: 429a cmp r2, r3
|
|
8008692: d10a bne.n 80086aa <HAL_RCC_OscConfig+0x82a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
8008694: 697b ldr r3, [r7, #20]
|
|
8008696: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000
|
|
800869a: 687b ldr r3, [r7, #4]
|
|
800869c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800869e: 085b lsrs r3, r3, #1
|
|
80086a0: 3b01 subs r3, #1
|
|
80086a2: 065b lsls r3, r3, #25
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
80086a4: 429a cmp r2, r3
|
|
80086a6: f000 8097 beq.w 80087d8 <HAL_RCC_OscConfig+0x958>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
80086aa: 69bb ldr r3, [r7, #24]
|
|
80086ac: 2b0c cmp r3, #12
|
|
80086ae: f000 8091 beq.w 80087d4 <HAL_RCC_OscConfig+0x954>
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
|
|
/* Check if main PLL can be updated */
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
|
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
|
80086b2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80086b6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80086ba: 681b ldr r3, [r3, #0]
|
|
80086bc: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
|
80086c0: 2b00 cmp r3, #0
|
|
80086c2: d108 bne.n 80086d6 <HAL_RCC_OscConfig+0x856>
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
|
|
80086c4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80086c8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80086cc: 681b ldr r3, [r3, #0]
|
|
80086ce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
80086d2: 2b00 cmp r3, #0
|
|
80086d4: d001 beq.n 80086da <HAL_RCC_OscConfig+0x85a>
|
|
#endif
|
|
)
|
|
{
|
|
return HAL_ERROR;
|
|
80086d6: 2301 movs r3, #1
|
|
80086d8: e102 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
else
|
|
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80086da: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80086de: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80086e2: 681a ldr r2, [r3, #0]
|
|
80086e4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80086e8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80086ec: f022 7280 bic.w r2, r2, #16777216 ; 0x1000000
|
|
80086f0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80086f2: f7fc f98a bl 8004a0a <HAL_GetTick>
|
|
80086f6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80086f8: e008 b.n 800870c <HAL_RCC_OscConfig+0x88c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80086fa: f7fc f986 bl 8004a0a <HAL_GetTick>
|
|
80086fe: 4602 mov r2, r0
|
|
8008700: 693b ldr r3, [r7, #16]
|
|
8008702: 1ad3 subs r3, r2, r3
|
|
8008704: 2b02 cmp r3, #2
|
|
8008706: d901 bls.n 800870c <HAL_RCC_OscConfig+0x88c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8008708: 2303 movs r3, #3
|
|
800870a: e0e9 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
800870c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008710: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008714: 681b ldr r3, [r3, #0]
|
|
8008716: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
800871a: 2b00 cmp r3, #0
|
|
800871c: d1ed bne.n 80086fa <HAL_RCC_OscConfig+0x87a>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
800871e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008722: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008726: 68da ldr r2, [r3, #12]
|
|
8008728: f248 038c movw r3, #32908 ; 0x808c
|
|
800872c: f6cf 139d movt r3, #63901 ; 0xf99d
|
|
8008730: 4013 ands r3, r2
|
|
8008732: 687a ldr r2, [r7, #4]
|
|
8008734: 6ad1 ldr r1, [r2, #44] ; 0x2c
|
|
8008736: 687a ldr r2, [r7, #4]
|
|
8008738: 6b12 ldr r2, [r2, #48] ; 0x30
|
|
800873a: 3a01 subs r2, #1
|
|
800873c: 0112 lsls r2, r2, #4
|
|
800873e: 4311 orrs r1, r2
|
|
8008740: 687a ldr r2, [r7, #4]
|
|
8008742: 6b52 ldr r2, [r2, #52] ; 0x34
|
|
8008744: 0212 lsls r2, r2, #8
|
|
8008746: 4311 orrs r1, r2
|
|
8008748: 687a ldr r2, [r7, #4]
|
|
800874a: 6bd2 ldr r2, [r2, #60] ; 0x3c
|
|
800874c: 0852 lsrs r2, r2, #1
|
|
800874e: 3a01 subs r2, #1
|
|
8008750: 0552 lsls r2, r2, #21
|
|
8008752: 4311 orrs r1, r2
|
|
8008754: 687a ldr r2, [r7, #4]
|
|
8008756: 6c12 ldr r2, [r2, #64] ; 0x40
|
|
8008758: 0852 lsrs r2, r2, #1
|
|
800875a: 3a01 subs r2, #1
|
|
800875c: 0652 lsls r2, r2, #25
|
|
800875e: 4311 orrs r1, r2
|
|
8008760: 687a ldr r2, [r7, #4]
|
|
8008762: 6b92 ldr r2, [r2, #56] ; 0x38
|
|
8008764: 0912 lsrs r2, r2, #4
|
|
8008766: 0452 lsls r2, r2, #17
|
|
8008768: 4311 orrs r1, r2
|
|
800876a: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
800876e: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
8008772: 430b orrs r3, r1
|
|
8008774: 60d3 str r3, [r2, #12]
|
|
#endif
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8008776: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800877a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800877e: 681a ldr r2, [r3, #0]
|
|
8008780: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008784: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008788: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000
|
|
800878c: 601a str r2, [r3, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
800878e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008792: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008796: 68da ldr r2, [r3, #12]
|
|
8008798: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800879c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80087a0: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000
|
|
80087a4: 60da str r2, [r3, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80087a6: f7fc f930 bl 8004a0a <HAL_GetTick>
|
|
80087aa: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80087ac: e008 b.n 80087c0 <HAL_RCC_OscConfig+0x940>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80087ae: f7fc f92c bl 8004a0a <HAL_GetTick>
|
|
80087b2: 4602 mov r2, r0
|
|
80087b4: 693b ldr r3, [r7, #16]
|
|
80087b6: 1ad3 subs r3, r2, r3
|
|
80087b8: 2b02 cmp r3, #2
|
|
80087ba: d901 bls.n 80087c0 <HAL_RCC_OscConfig+0x940>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80087bc: 2303 movs r3, #3
|
|
80087be: e08f b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80087c0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80087c4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80087c8: 681b ldr r3, [r3, #0]
|
|
80087ca: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80087ce: 2b00 cmp r3, #0
|
|
80087d0: d0ed beq.n 80087ae <HAL_RCC_OscConfig+0x92e>
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
80087d2: e084 b.n 80088de <HAL_RCC_OscConfig+0xa5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
80087d4: 2301 movs r3, #1
|
|
80087d6: e083 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
else
|
|
{
|
|
/* PLL configuration is unchanged */
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80087d8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80087dc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80087e0: 681b ldr r3, [r3, #0]
|
|
80087e2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80087e6: 2b00 cmp r3, #0
|
|
80087e8: d179 bne.n 80088de <HAL_RCC_OscConfig+0xa5e>
|
|
{
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80087ea: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80087ee: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80087f2: 681a ldr r2, [r3, #0]
|
|
80087f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80087f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80087fc: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000
|
|
8008800: 601a str r2, [r3, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8008802: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008806: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800880a: 68da ldr r2, [r3, #12]
|
|
800880c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008810: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008814: f042 7280 orr.w r2, r2, #16777216 ; 0x1000000
|
|
8008818: 60da str r2, [r3, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800881a: f7fc f8f6 bl 8004a0a <HAL_GetTick>
|
|
800881e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8008820: e008 b.n 8008834 <HAL_RCC_OscConfig+0x9b4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8008822: f7fc f8f2 bl 8004a0a <HAL_GetTick>
|
|
8008826: 4602 mov r2, r0
|
|
8008828: 693b ldr r3, [r7, #16]
|
|
800882a: 1ad3 subs r3, r2, r3
|
|
800882c: 2b02 cmp r3, #2
|
|
800882e: d901 bls.n 8008834 <HAL_RCC_OscConfig+0x9b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8008830: 2303 movs r3, #3
|
|
8008832: e055 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8008834: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008838: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800883c: 681b ldr r3, [r3, #0]
|
|
800883e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8008842: 2b00 cmp r3, #0
|
|
8008844: d0ed beq.n 8008822 <HAL_RCC_OscConfig+0x9a2>
|
|
8008846: e04a b.n 80088de <HAL_RCC_OscConfig+0xa5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check that PLL is not used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8008848: 69bb ldr r3, [r7, #24]
|
|
800884a: 2b0c cmp r3, #12
|
|
800884c: d045 beq.n 80088da <HAL_RCC_OscConfig+0xa5a>
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800884e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008852: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008856: 681a ldr r2, [r3, #0]
|
|
8008858: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800885c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008860: f022 7280 bic.w r2, r2, #16777216 ; 0x1000000
|
|
8008864: 601a str r2, [r3, #0]
|
|
|
|
/* Disable all PLL outputs to save power if no PLLs on */
|
|
#if defined(RCC_PLLSAI1_SUPPORT) && defined(RCC_CR_PLLSAI2RDY)
|
|
if(READ_BIT(RCC->CR, (RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY)) == 0U)
|
|
8008866: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800886a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800886e: 681b ldr r3, [r3, #0]
|
|
8008870: f003 5320 and.w r3, r3, #671088640 ; 0x28000000
|
|
8008874: 2b00 cmp r3, #0
|
|
8008876: d10b bne.n 8008890 <HAL_RCC_OscConfig+0xa10>
|
|
{
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
|
|
8008878: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800887c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008880: 68da ldr r2, [r3, #12]
|
|
8008882: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008886: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800888a: f022 0203 bic.w r2, r2, #3
|
|
800888e: 60da str r2, [r3, #12]
|
|
#else
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE);
|
|
#endif /* RCC_PLLSAI1_SUPPORT && RCC_CR_PLLSAI2RDY */
|
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
|
|
8008890: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008894: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008898: 68db ldr r3, [r3, #12]
|
|
800889a: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
800889e: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
80088a2: f023 7388 bic.w r3, r3, #17825792 ; 0x1100000
|
|
80088a6: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
80088aa: 60d3 str r3, [r2, #12]
|
|
#else
|
|
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK);
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80088ac: f7fc f8ad bl 8004a0a <HAL_GetTick>
|
|
80088b0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80088b2: e008 b.n 80088c6 <HAL_RCC_OscConfig+0xa46>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80088b4: f7fc f8a9 bl 8004a0a <HAL_GetTick>
|
|
80088b8: 4602 mov r2, r0
|
|
80088ba: 693b ldr r3, [r7, #16]
|
|
80088bc: 1ad3 subs r3, r2, r3
|
|
80088be: 2b02 cmp r3, #2
|
|
80088c0: d901 bls.n 80088c6 <HAL_RCC_OscConfig+0xa46>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80088c2: 2303 movs r3, #3
|
|
80088c4: e00c b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
80088c6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80088ca: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80088ce: 681b ldr r3, [r3, #0]
|
|
80088d0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80088d4: 2b00 cmp r3, #0
|
|
80088d6: d1ed bne.n 80088b4 <HAL_RCC_OscConfig+0xa34>
|
|
80088d8: e001 b.n 80088de <HAL_RCC_OscConfig+0xa5e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
80088da: 2301 movs r3, #1
|
|
80088dc: e000 b.n 80088e0 <HAL_RCC_OscConfig+0xa60>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80088de: 2300 movs r3, #0
|
|
}
|
|
80088e0: 4618 mov r0, r3
|
|
80088e2: 3720 adds r7, #32
|
|
80088e4: 46bd mov sp, r7
|
|
80088e6: bd80 pop {r7, pc}
|
|
|
|
080088e8 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80088e8: b580 push {r7, lr}
|
|
80088ea: b084 sub sp, #16
|
|
80088ec: af00 add r7, sp, #0
|
|
80088ee: 6078 str r0, [r7, #4]
|
|
80088f0: 6039 str r1, [r7, #0]
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
#endif
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
80088f2: 687b ldr r3, [r7, #4]
|
|
80088f4: 2b00 cmp r3, #0
|
|
80088f6: d101 bne.n 80088fc <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80088f8: 2301 movs r3, #1
|
|
80088fa: e113 b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80088fc: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008900: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008904: 681b ldr r3, [r3, #0]
|
|
8008906: f003 0307 and.w r3, r3, #7
|
|
800890a: 683a ldr r2, [r7, #0]
|
|
800890c: 429a cmp r2, r3
|
|
800890e: d919 bls.n 8008944 <HAL_RCC_ClockConfig+0x5c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8008910: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008914: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008918: 681b ldr r3, [r3, #0]
|
|
800891a: f023 0107 bic.w r1, r3, #7
|
|
800891e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008922: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008926: 683a ldr r2, [r7, #0]
|
|
8008928: 430a orrs r2, r1
|
|
800892a: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800892c: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008930: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008934: 681b ldr r3, [r3, #0]
|
|
8008936: f003 0307 and.w r3, r3, #7
|
|
800893a: 683a ldr r2, [r7, #0]
|
|
800893c: 429a cmp r2, r3
|
|
800893e: d001 beq.n 8008944 <HAL_RCC_ClockConfig+0x5c>
|
|
{
|
|
return HAL_ERROR;
|
|
8008940: 2301 movs r3, #1
|
|
8008942: e0ef b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8008944: 687b ldr r3, [r7, #4]
|
|
8008946: 681b ldr r3, [r3, #0]
|
|
8008948: f003 0301 and.w r3, r3, #1
|
|
800894c: 2b00 cmp r3, #0
|
|
800894e: d061 beq.n 8008a14 <HAL_RCC_ClockConfig+0x12c>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8008950: 687b ldr r3, [r7, #4]
|
|
8008952: 685b ldr r3, [r3, #4]
|
|
8008954: 2b03 cmp r3, #3
|
|
8008956: d10a bne.n 800896e <HAL_RCC_ClockConfig+0x86>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8008958: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800895c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008960: 681b ldr r3, [r3, #0]
|
|
8008962: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8008966: 2b00 cmp r3, #0
|
|
8008968: d12a bne.n 80089c0 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
800896a: 2301 movs r3, #1
|
|
800896c: e0da b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
800896e: 687b ldr r3, [r7, #4]
|
|
8008970: 685b ldr r3, [r3, #4]
|
|
8008972: 2b02 cmp r3, #2
|
|
8008974: d10a bne.n 800898c <HAL_RCC_ClockConfig+0xa4>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8008976: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800897a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800897e: 681b ldr r3, [r3, #0]
|
|
8008980: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8008984: 2b00 cmp r3, #0
|
|
8008986: d11b bne.n 80089c0 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
8008988: 2301 movs r3, #1
|
|
800898a: e0cb b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
800898c: 687b ldr r3, [r7, #4]
|
|
800898e: 685b ldr r3, [r3, #4]
|
|
8008990: 2b00 cmp r3, #0
|
|
8008992: d10a bne.n 80089aa <HAL_RCC_ClockConfig+0xc2>
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
8008994: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008998: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800899c: 681b ldr r3, [r3, #0]
|
|
800899e: f003 0302 and.w r3, r3, #2
|
|
80089a2: 2b00 cmp r3, #0
|
|
80089a4: d10c bne.n 80089c0 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
80089a6: 2301 movs r3, #1
|
|
80089a8: e0bc b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
80089aa: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80089ae: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80089b2: 681b ldr r3, [r3, #0]
|
|
80089b4: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
80089b8: 2b00 cmp r3, #0
|
|
80089ba: d101 bne.n 80089c0 <HAL_RCC_ClockConfig+0xd8>
|
|
{
|
|
return HAL_ERROR;
|
|
80089bc: 2301 movs r3, #1
|
|
80089be: e0b1 b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
80089c0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80089c4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80089c8: 689b ldr r3, [r3, #8]
|
|
80089ca: f023 0103 bic.w r1, r3, #3
|
|
80089ce: 687b ldr r3, [r7, #4]
|
|
80089d0: 685a ldr r2, [r3, #4]
|
|
80089d2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80089d6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80089da: 430a orrs r2, r1
|
|
80089dc: 609a str r2, [r3, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80089de: f7fc f814 bl 8004a0a <HAL_GetTick>
|
|
80089e2: 60f8 str r0, [r7, #12]
|
|
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80089e4: e00a b.n 80089fc <HAL_RCC_ClockConfig+0x114>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80089e6: f7fc f810 bl 8004a0a <HAL_GetTick>
|
|
80089ea: 4602 mov r2, r0
|
|
80089ec: 68fb ldr r3, [r7, #12]
|
|
80089ee: 1ad3 subs r3, r2, r3
|
|
80089f0: f241 3288 movw r2, #5000 ; 0x1388
|
|
80089f4: 4293 cmp r3, r2
|
|
80089f6: d901 bls.n 80089fc <HAL_RCC_ClockConfig+0x114>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80089f8: 2303 movs r3, #3
|
|
80089fa: e093 b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
80089fc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008a00: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a04: 689b ldr r3, [r3, #8]
|
|
8008a06: f003 020c and.w r2, r3, #12
|
|
8008a0a: 687b ldr r3, [r7, #4]
|
|
8008a0c: 685b ldr r3, [r3, #4]
|
|
8008a0e: 009b lsls r3, r3, #2
|
|
8008a10: 429a cmp r2, r3
|
|
8008a12: d1e8 bne.n 80089e6 <HAL_RCC_ClockConfig+0xfe>
|
|
}
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8008a14: 687b ldr r3, [r7, #4]
|
|
8008a16: 681b ldr r3, [r3, #0]
|
|
8008a18: f003 0302 and.w r3, r3, #2
|
|
8008a1c: 2b00 cmp r3, #0
|
|
8008a1e: d00e beq.n 8008a3e <HAL_RCC_ClockConfig+0x156>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8008a20: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008a24: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a28: 689b ldr r3, [r3, #8]
|
|
8008a2a: f023 01f0 bic.w r1, r3, #240 ; 0xf0
|
|
8008a2e: 687b ldr r3, [r7, #4]
|
|
8008a30: 689a ldr r2, [r3, #8]
|
|
8008a32: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008a36: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a3a: 430a orrs r2, r1
|
|
8008a3c: 609a str r2, [r3, #8]
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8008a3e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008a42: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a46: 681b ldr r3, [r3, #0]
|
|
8008a48: f003 0307 and.w r3, r3, #7
|
|
8008a4c: 683a ldr r2, [r7, #0]
|
|
8008a4e: 429a cmp r2, r3
|
|
8008a50: d219 bcs.n 8008a86 <HAL_RCC_ClockConfig+0x19e>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8008a52: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008a56: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a5a: 681b ldr r3, [r3, #0]
|
|
8008a5c: f023 0107 bic.w r1, r3, #7
|
|
8008a60: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008a64: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a68: 683a ldr r2, [r7, #0]
|
|
8008a6a: 430a orrs r2, r1
|
|
8008a6c: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8008a6e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008a72: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a76: 681b ldr r3, [r3, #0]
|
|
8008a78: f003 0307 and.w r3, r3, #7
|
|
8008a7c: 683a ldr r2, [r7, #0]
|
|
8008a7e: 429a cmp r2, r3
|
|
8008a80: d001 beq.n 8008a86 <HAL_RCC_ClockConfig+0x19e>
|
|
{
|
|
return HAL_ERROR;
|
|
8008a82: 2301 movs r3, #1
|
|
8008a84: e04e b.n 8008b24 <HAL_RCC_ClockConfig+0x23c>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8008a86: 687b ldr r3, [r7, #4]
|
|
8008a88: 681b ldr r3, [r3, #0]
|
|
8008a8a: f003 0304 and.w r3, r3, #4
|
|
8008a8e: 2b00 cmp r3, #0
|
|
8008a90: d00e beq.n 8008ab0 <HAL_RCC_ClockConfig+0x1c8>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8008a92: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008a96: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008a9a: 689b ldr r3, [r3, #8]
|
|
8008a9c: f423 61e0 bic.w r1, r3, #1792 ; 0x700
|
|
8008aa0: 687b ldr r3, [r7, #4]
|
|
8008aa2: 68da ldr r2, [r3, #12]
|
|
8008aa4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008aa8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008aac: 430a orrs r2, r1
|
|
8008aae: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8008ab0: 687b ldr r3, [r7, #4]
|
|
8008ab2: 681b ldr r3, [r3, #0]
|
|
8008ab4: f003 0308 and.w r3, r3, #8
|
|
8008ab8: 2b00 cmp r3, #0
|
|
8008aba: d00f beq.n 8008adc <HAL_RCC_ClockConfig+0x1f4>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8008abc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008ac0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008ac4: 689b ldr r3, [r3, #8]
|
|
8008ac6: f423 5160 bic.w r1, r3, #14336 ; 0x3800
|
|
8008aca: 687b ldr r3, [r7, #4]
|
|
8008acc: 691b ldr r3, [r3, #16]
|
|
8008ace: 00da lsls r2, r3, #3
|
|
8008ad0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008ad4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008ad8: 430a orrs r2, r1
|
|
8008ada: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8008adc: f000 f826 bl 8008b2c <HAL_RCC_GetSysClockFreq>
|
|
8008ae0: 4601 mov r1, r0
|
|
8008ae2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008ae6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008aea: 689b ldr r3, [r3, #8]
|
|
8008aec: 091b lsrs r3, r3, #4
|
|
8008aee: f003 020f and.w r2, r3, #15
|
|
8008af2: f24e 33ac movw r3, #58284 ; 0xe3ac
|
|
8008af6: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8008afa: 5c9b ldrb r3, [r3, r2]
|
|
8008afc: f003 031f and.w r3, r3, #31
|
|
8008b00: fa21 f203 lsr.w r2, r1, r3
|
|
8008b04: f240 234c movw r3, #588 ; 0x24c
|
|
8008b08: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8008b0c: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
8008b0e: f240 2350 movw r3, #592 ; 0x250
|
|
8008b12: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8008b16: 681b ldr r3, [r3, #0]
|
|
8008b18: 4618 mov r0, r3
|
|
8008b1a: f7fb ff1d bl 8004958 <HAL_InitTick>
|
|
8008b1e: 4603 mov r3, r0
|
|
8008b20: 72fb strb r3, [r7, #11]
|
|
|
|
return status;
|
|
8008b22: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
8008b24: 4618 mov r0, r3
|
|
8008b26: 3710 adds r7, #16
|
|
8008b28: 46bd mov sp, r7
|
|
8008b2a: bd80 pop {r7, pc}
|
|
|
|
08008b2c <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8008b2c: b480 push {r7}
|
|
8008b2e: b089 sub sp, #36 ; 0x24
|
|
8008b30: af00 add r7, sp, #0
|
|
uint32_t msirange = 0U, sysclockfreq = 0U;
|
|
8008b32: 2300 movs r3, #0
|
|
8008b34: 61fb str r3, [r7, #28]
|
|
8008b36: 2300 movs r3, #0
|
|
8008b38: 61bb str r3, [r7, #24]
|
|
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
|
|
uint32_t sysclk_source, pll_oscsource;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8008b3a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008b3e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008b42: 689b ldr r3, [r3, #8]
|
|
8008b44: f003 030c and.w r3, r3, #12
|
|
8008b48: 613b str r3, [r7, #16]
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8008b4a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008b4e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008b52: 68db ldr r3, [r3, #12]
|
|
8008b54: f003 0303 and.w r3, r3, #3
|
|
8008b58: 60fb str r3, [r7, #12]
|
|
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
8008b5a: 693b ldr r3, [r7, #16]
|
|
8008b5c: 2b00 cmp r3, #0
|
|
8008b5e: d005 beq.n 8008b6c <HAL_RCC_GetSysClockFreq+0x40>
|
|
8008b60: 693b ldr r3, [r7, #16]
|
|
8008b62: 2b0c cmp r3, #12
|
|
8008b64: d12d bne.n 8008bc2 <HAL_RCC_GetSysClockFreq+0x96>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
|
8008b66: 68fb ldr r3, [r7, #12]
|
|
8008b68: 2b01 cmp r3, #1
|
|
8008b6a: d12a bne.n 8008bc2 <HAL_RCC_GetSysClockFreq+0x96>
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
|
|
/* Get SYSCLK source */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
|
8008b6c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008b70: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008b74: 681b ldr r3, [r3, #0]
|
|
8008b76: f003 0308 and.w r3, r3, #8
|
|
8008b7a: 2b00 cmp r3, #0
|
|
8008b7c: d10a bne.n 8008b94 <HAL_RCC_GetSysClockFreq+0x68>
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
|
|
8008b7e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008b82: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008b86: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94
|
|
8008b8a: 0a1b lsrs r3, r3, #8
|
|
8008b8c: f003 030f and.w r3, r3, #15
|
|
8008b90: 61fb str r3, [r7, #28]
|
|
8008b92: e008 b.n 8008ba6 <HAL_RCC_GetSysClockFreq+0x7a>
|
|
}
|
|
else
|
|
{ /* MSIRANGE from RCC_CR applies */
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
|
8008b94: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008b98: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008b9c: 681b ldr r3, [r3, #0]
|
|
8008b9e: 091b lsrs r3, r3, #4
|
|
8008ba0: f003 030f and.w r3, r3, #15
|
|
8008ba4: 61fb str r3, [r7, #28]
|
|
}
|
|
/*MSI frequency range in HZ*/
|
|
msirange = MSIRangeTable[msirange];
|
|
8008ba6: f24e 33c4 movw r3, #58308 ; 0xe3c4
|
|
8008baa: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8008bae: 69fa ldr r2, [r7, #28]
|
|
8008bb0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008bb4: 61fb str r3, [r7, #28]
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8008bb6: 693b ldr r3, [r7, #16]
|
|
8008bb8: 2b00 cmp r3, #0
|
|
8008bba: d113 bne.n 8008be4 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msirange;
|
|
8008bbc: 69fb ldr r3, [r7, #28]
|
|
8008bbe: 61bb str r3, [r7, #24]
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8008bc0: e010 b.n 8008be4 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
}
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSI)
|
|
8008bc2: 693b ldr r3, [r7, #16]
|
|
8008bc4: 2b04 cmp r3, #4
|
|
8008bc6: d105 bne.n 8008bd4 <HAL_RCC_GetSysClockFreq+0xa8>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
8008bc8: f44f 5310 mov.w r3, #9216 ; 0x2400
|
|
8008bcc: f2c0 03f4 movt r3, #244 ; 0xf4
|
|
8008bd0: 61bb str r3, [r7, #24]
|
|
8008bd2: e007 b.n 8008be4 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSE)
|
|
8008bd4: 693b ldr r3, [r7, #16]
|
|
8008bd6: 2b08 cmp r3, #8
|
|
8008bd8: d104 bne.n 8008be4 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
8008bda: f44f 5390 mov.w r3, #4608 ; 0x1200
|
|
8008bde: f2c0 037a movt r3, #122 ; 0x7a
|
|
8008be2: 61bb str r3, [r7, #24]
|
|
else
|
|
{
|
|
/* unexpected case: sysclockfreq at 0 */
|
|
}
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_PLL)
|
|
8008be4: 693b ldr r3, [r7, #16]
|
|
8008be6: 2b0c cmp r3, #12
|
|
8008be8: d146 bne.n 8008c78 <HAL_RCC_GetSysClockFreq+0x14c>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
8008bea: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008bee: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008bf2: 68db ldr r3, [r3, #12]
|
|
8008bf4: f003 0303 and.w r3, r3, #3
|
|
8008bf8: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
8008bfa: 68bb ldr r3, [r7, #8]
|
|
8008bfc: 2b02 cmp r3, #2
|
|
8008bfe: d003 beq.n 8008c08 <HAL_RCC_GetSysClockFreq+0xdc>
|
|
8008c00: 68bb ldr r3, [r7, #8]
|
|
8008c02: 2b03 cmp r3, #3
|
|
8008c04: d006 beq.n 8008c14 <HAL_RCC_GetSysClockFreq+0xe8>
|
|
8008c06: e00b b.n 8008c20 <HAL_RCC_GetSysClockFreq+0xf4>
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllvco = HSI_VALUE;
|
|
8008c08: f44f 5310 mov.w r3, #9216 ; 0x2400
|
|
8008c0c: f2c0 03f4 movt r3, #244 ; 0xf4
|
|
8008c10: 617b str r3, [r7, #20]
|
|
break;
|
|
8008c12: e008 b.n 8008c26 <HAL_RCC_GetSysClockFreq+0xfa>
|
|
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = HSE_VALUE;
|
|
8008c14: f44f 5390 mov.w r3, #4608 ; 0x1200
|
|
8008c18: f2c0 037a movt r3, #122 ; 0x7a
|
|
8008c1c: 617b str r3, [r7, #20]
|
|
break;
|
|
8008c1e: e002 b.n 8008c26 <HAL_RCC_GetSysClockFreq+0xfa>
|
|
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllvco = msirange;
|
|
8008c20: 69fb ldr r3, [r7, #28]
|
|
8008c22: 617b str r3, [r7, #20]
|
|
break;
|
|
8008c24: bf00 nop
|
|
}
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
8008c26: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008c2a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008c2e: 68db ldr r3, [r3, #12]
|
|
8008c30: 091b lsrs r3, r3, #4
|
|
8008c32: f003 0307 and.w r3, r3, #7
|
|
8008c36: 3301 adds r3, #1
|
|
8008c38: 607b str r3, [r7, #4]
|
|
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
|
|
8008c3a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008c3e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008c42: 68db ldr r3, [r3, #12]
|
|
8008c44: 0a1b lsrs r3, r3, #8
|
|
8008c46: f003 037f and.w r3, r3, #127 ; 0x7f
|
|
8008c4a: 697a ldr r2, [r7, #20]
|
|
8008c4c: fb02 f203 mul.w r2, r2, r3
|
|
8008c50: 687b ldr r3, [r7, #4]
|
|
8008c52: fbb2 f3f3 udiv r3, r2, r3
|
|
8008c56: 617b str r3, [r7, #20]
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
8008c58: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008c5c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008c60: 68db ldr r3, [r3, #12]
|
|
8008c62: 0e5b lsrs r3, r3, #25
|
|
8008c64: f003 0303 and.w r3, r3, #3
|
|
8008c68: 3301 adds r3, #1
|
|
8008c6a: 005b lsls r3, r3, #1
|
|
8008c6c: 603b str r3, [r7, #0]
|
|
sysclockfreq = pllvco / pllr;
|
|
8008c6e: 697a ldr r2, [r7, #20]
|
|
8008c70: 683b ldr r3, [r7, #0]
|
|
8008c72: fbb2 f3f3 udiv r3, r2, r3
|
|
8008c76: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
8008c78: 69bb ldr r3, [r7, #24]
|
|
}
|
|
8008c7a: 4618 mov r0, r3
|
|
8008c7c: 3724 adds r7, #36 ; 0x24
|
|
8008c7e: 46bd mov sp, r7
|
|
8008c80: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008c84: 4770 bx lr
|
|
|
|
08008c86 <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8008c86: b480 push {r7}
|
|
8008c88: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8008c8a: f240 234c movw r3, #588 ; 0x24c
|
|
8008c8e: f2c2 0300 movt r3, #8192 ; 0x2000
|
|
8008c92: 681b ldr r3, [r3, #0]
|
|
}
|
|
8008c94: 4618 mov r0, r3
|
|
8008c96: 46bd mov sp, r7
|
|
8008c98: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008c9c: 4770 bx lr
|
|
|
|
08008c9e <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8008c9e: b580 push {r7, lr}
|
|
8008ca0: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
8008ca2: f7ff fff0 bl 8008c86 <HAL_RCC_GetHCLKFreq>
|
|
8008ca6: 4601 mov r1, r0
|
|
8008ca8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008cac: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008cb0: 689b ldr r3, [r3, #8]
|
|
8008cb2: 0a1b lsrs r3, r3, #8
|
|
8008cb4: f003 0207 and.w r2, r3, #7
|
|
8008cb8: f24e 33bc movw r3, #58300 ; 0xe3bc
|
|
8008cbc: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8008cc0: 5c9b ldrb r3, [r3, r2]
|
|
8008cc2: f003 031f and.w r3, r3, #31
|
|
8008cc6: fa21 f303 lsr.w r3, r1, r3
|
|
}
|
|
8008cca: 4618 mov r0, r3
|
|
8008ccc: bd80 pop {r7, pc}
|
|
|
|
08008cce <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8008cce: b580 push {r7, lr}
|
|
8008cd0: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
8008cd2: f7ff ffd8 bl 8008c86 <HAL_RCC_GetHCLKFreq>
|
|
8008cd6: 4601 mov r1, r0
|
|
8008cd8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008cdc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008ce0: 689b ldr r3, [r3, #8]
|
|
8008ce2: 0adb lsrs r3, r3, #11
|
|
8008ce4: f003 0207 and.w r2, r3, #7
|
|
8008ce8: f24e 33bc movw r3, #58300 ; 0xe3bc
|
|
8008cec: f6c0 0300 movt r3, #2048 ; 0x800
|
|
8008cf0: 5c9b ldrb r3, [r3, r2]
|
|
8008cf2: f003 031f and.w r3, r3, #31
|
|
8008cf6: fa21 f303 lsr.w r3, r1, r3
|
|
}
|
|
8008cfa: 4618 mov r0, r3
|
|
8008cfc: bd80 pop {r7, pc}
|
|
|
|
08008cfe <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range.
|
|
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
|
{
|
|
8008cfe: b580 push {r7, lr}
|
|
8008d00: b086 sub sp, #24
|
|
8008d02: af00 add r7, sp, #0
|
|
8008d04: 6078 str r0, [r7, #4]
|
|
uint32_t vos;
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
8008d06: 2300 movs r3, #0
|
|
8008d08: 613b str r3, [r7, #16]
|
|
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
8008d0a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008d0e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008d12: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8008d14: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8008d18: 2b00 cmp r3, #0
|
|
8008d1a: d003 beq.n 8008d24 <RCC_SetFlashLatencyFromMSIRange+0x26>
|
|
{
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
8008d1c: f7fe ffc5 bl 8007caa <HAL_PWREx_GetVoltageRange>
|
|
8008d20: 6178 str r0, [r7, #20]
|
|
8008d22: e023 b.n 8008d6c <RCC_SetFlashLatencyFromMSIRange+0x6e>
|
|
}
|
|
else
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8008d24: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008d28: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008d2c: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8008d2e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008d32: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008d36: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
|
|
8008d3a: 659a str r2, [r3, #88] ; 0x58
|
|
8008d3c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008d40: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008d44: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8008d46: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8008d4a: 60fb str r3, [r7, #12]
|
|
8008d4c: 68fb ldr r3, [r7, #12]
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
8008d4e: f7fe ffac bl 8007caa <HAL_PWREx_GetVoltageRange>
|
|
8008d52: 6178 str r0, [r7, #20]
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8008d54: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008d58: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008d5c: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8008d5e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008d62: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008d66: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
|
|
8008d6a: 659a str r2, [r3, #88] ; 0x58
|
|
}
|
|
|
|
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
8008d6c: 697b ldr r3, [r7, #20]
|
|
8008d6e: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
8008d72: d10b bne.n 8008d8c <RCC_SetFlashLatencyFromMSIRange+0x8e>
|
|
{
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
8008d74: 687b ldr r3, [r7, #4]
|
|
8008d76: 2b80 cmp r3, #128 ; 0x80
|
|
8008d78: d919 bls.n 8008dae <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
if(msirange > RCC_MSIRANGE_10)
|
|
8008d7a: 687b ldr r3, [r7, #4]
|
|
8008d7c: 2ba0 cmp r3, #160 ; 0xa0
|
|
8008d7e: d902 bls.n 8008d86 <RCC_SetFlashLatencyFromMSIRange+0x88>
|
|
{
|
|
/* MSI 48Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
8008d80: 2302 movs r3, #2
|
|
8008d82: 613b str r3, [r7, #16]
|
|
8008d84: e013 b.n 8008dae <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
}
|
|
else
|
|
{
|
|
/* MSI 24Mhz or 32Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
8008d86: 2301 movs r3, #1
|
|
8008d88: 613b str r3, [r7, #16]
|
|
8008d8a: e010 b.n 8008dae <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
}
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
#else
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
8008d8c: 687b ldr r3, [r7, #4]
|
|
8008d8e: 2b80 cmp r3, #128 ; 0x80
|
|
8008d90: d902 bls.n 8008d98 <RCC_SetFlashLatencyFromMSIRange+0x9a>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
latency = FLASH_LATENCY_3; /* 3WS */
|
|
8008d92: 2303 movs r3, #3
|
|
8008d94: 613b str r3, [r7, #16]
|
|
8008d96: e00a b.n 8008dae <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
}
|
|
else
|
|
{
|
|
if(msirange == RCC_MSIRANGE_8)
|
|
8008d98: 687b ldr r3, [r7, #4]
|
|
8008d9a: 2b80 cmp r3, #128 ; 0x80
|
|
8008d9c: d102 bne.n 8008da4 <RCC_SetFlashLatencyFromMSIRange+0xa6>
|
|
{
|
|
/* MSI 16Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
8008d9e: 2302 movs r3, #2
|
|
8008da0: 613b str r3, [r7, #16]
|
|
8008da2: e004 b.n 8008dae <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
}
|
|
else if(msirange == RCC_MSIRANGE_7)
|
|
8008da4: 687b ldr r3, [r7, #4]
|
|
8008da6: 2b70 cmp r3, #112 ; 0x70
|
|
8008da8: d101 bne.n 8008dae <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
{
|
|
/* MSI 8Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
8008daa: 2301 movs r3, #1
|
|
8008dac: 613b str r3, [r7, #16]
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
#endif
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
8008dae: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008db2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008db6: 681b ldr r3, [r3, #0]
|
|
8008db8: f023 0107 bic.w r1, r3, #7
|
|
8008dbc: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008dc0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008dc4: 693a ldr r2, [r7, #16]
|
|
8008dc6: 430a orrs r2, r1
|
|
8008dc8: 601a str r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
|
8008dca: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8008dce: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008dd2: 681b ldr r3, [r3, #0]
|
|
8008dd4: f003 0307 and.w r3, r3, #7
|
|
8008dd8: 693a ldr r2, [r7, #16]
|
|
8008dda: 429a cmp r2, r3
|
|
8008ddc: d001 beq.n 8008de2 <RCC_SetFlashLatencyFromMSIRange+0xe4>
|
|
{
|
|
return HAL_ERROR;
|
|
8008dde: 2301 movs r3, #1
|
|
8008de0: e000 b.n 8008de4 <RCC_SetFlashLatencyFromMSIRange+0xe6>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8008de2: 2300 movs r3, #0
|
|
}
|
|
8008de4: 4618 mov r0, r3
|
|
8008de6: 3718 adds r7, #24
|
|
8008de8: 46bd mov sp, r7
|
|
8008dea: bd80 pop {r7, pc}
|
|
|
|
08008dec <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8008dec: b580 push {r7, lr}
|
|
8008dee: b086 sub sp, #24
|
|
8008df0: af00 add r7, sp, #0
|
|
8008df2: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister, tickstart; /* no init needed */
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
8008df4: 2300 movs r3, #0
|
|
8008df6: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8008df8: 2300 movs r3, #0
|
|
8008dfa: 74bb strb r3, [r7, #18]
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
#if defined(SAI1)
|
|
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
|
8008dfc: 687b ldr r3, [r7, #4]
|
|
8008dfe: 681b ldr r3, [r3, #0]
|
|
8008e00: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
8008e04: 2b00 cmp r3, #0
|
|
8008e06: d04d beq.n 8008ea4 <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai1ClockSelection)
|
|
8008e08: 687b ldr r3, [r7, #4]
|
|
8008e0a: 6e5b ldr r3, [r3, #100] ; 0x64
|
|
8008e0c: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
|
|
8008e10: d030 beq.n 8008e74 <HAL_RCCEx_PeriphCLKConfig+0x88>
|
|
8008e12: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000
|
|
8008e16: d82a bhi.n 8008e6e <HAL_RCCEx_PeriphCLKConfig+0x82>
|
|
8008e18: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
|
|
8008e1c: d008 beq.n 8008e30 <HAL_RCCEx_PeriphCLKConfig+0x44>
|
|
8008e1e: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000
|
|
8008e22: d824 bhi.n 8008e6e <HAL_RCCEx_PeriphCLKConfig+0x82>
|
|
8008e24: 2b00 cmp r3, #0
|
|
8008e26: d010 beq.n 8008e4a <HAL_RCCEx_PeriphCLKConfig+0x5e>
|
|
8008e28: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
|
|
8008e2c: d016 beq.n 8008e5c <HAL_RCCEx_PeriphCLKConfig+0x70>
|
|
8008e2e: e01e b.n 8008e6e <HAL_RCCEx_PeriphCLKConfig+0x82>
|
|
{
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
8008e30: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008e34: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008e38: 68da ldr r2, [r3, #12]
|
|
8008e3a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008e3e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008e42: f442 3280 orr.w r2, r2, #65536 ; 0x10000
|
|
8008e46: 60da str r2, [r3, #12]
|
|
#else
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8008e48: e015 b.n 8008e76 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
8008e4a: 687b ldr r3, [r7, #4]
|
|
8008e4c: 3304 adds r3, #4
|
|
8008e4e: 2100 movs r1, #0
|
|
8008e50: 4618 mov r0, r3
|
|
8008e52: f000 fb87 bl 8009564 <RCCEx_PLLSAI1_Config>
|
|
8008e56: 4603 mov r3, r0
|
|
8008e58: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8008e5a: e00c b.n 8008e76 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
8008e5c: 687b ldr r3, [r7, #4]
|
|
8008e5e: 3320 adds r3, #32
|
|
8008e60: 2100 movs r1, #0
|
|
8008e62: 4618 mov r0, r3
|
|
8008e64: f000 fcb6 bl 80097d4 <RCCEx_PLLSAI2_Config>
|
|
8008e68: 4603 mov r3, r0
|
|
8008e6a: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
8008e6c: e003 b.n 8008e76 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
8008e6e: 2301 movs r3, #1
|
|
8008e70: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8008e72: e000 b.n 8008e76 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
break;
|
|
8008e74: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8008e76: 7cfb ldrb r3, [r7, #19]
|
|
8008e78: 2b00 cmp r3, #0
|
|
8008e7a: d111 bne.n 8008ea0 <HAL_RCCEx_PeriphCLKConfig+0xb4>
|
|
{
|
|
/* Set the source of SAI1 clock*/
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8008e7c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008e80: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008e84: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8008e88: f423 0140 bic.w r1, r3, #12582912 ; 0xc00000
|
|
8008e8c: 687b ldr r3, [r7, #4]
|
|
8008e8e: 6e5a ldr r2, [r3, #100] ; 0x64
|
|
8008e90: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008e94: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008e98: 430a orrs r2, r1
|
|
8008e9a: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
8008e9e: e001 b.n 8008ea4 <HAL_RCCEx_PeriphCLKConfig+0xb8>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8008ea0: 7cfb ldrb r3, [r7, #19]
|
|
8008ea2: 74bb strb r3, [r7, #18]
|
|
#endif /* SAI1 */
|
|
|
|
#if defined(SAI2)
|
|
|
|
/*-------------------------- SAI2 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
|
|
8008ea4: 687b ldr r3, [r7, #4]
|
|
8008ea6: 681b ldr r3, [r3, #0]
|
|
8008ea8: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
|
8008eac: 2b00 cmp r3, #0
|
|
8008eae: d04d beq.n 8008f4c <HAL_RCCEx_PeriphCLKConfig+0x160>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai2ClockSelection)
|
|
8008eb0: 687b ldr r3, [r7, #4]
|
|
8008eb2: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
8008eb4: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000
|
|
8008eb8: d030 beq.n 8008f1c <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
8008eba: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000
|
|
8008ebe: d82a bhi.n 8008f16 <HAL_RCCEx_PeriphCLKConfig+0x12a>
|
|
8008ec0: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
|
8008ec4: d008 beq.n 8008ed8 <HAL_RCCEx_PeriphCLKConfig+0xec>
|
|
8008ec6: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
|
8008eca: d824 bhi.n 8008f16 <HAL_RCCEx_PeriphCLKConfig+0x12a>
|
|
8008ecc: 2b00 cmp r3, #0
|
|
8008ece: d010 beq.n 8008ef2 <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
8008ed0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
|
|
8008ed4: d016 beq.n 8008f04 <HAL_RCCEx_PeriphCLKConfig+0x118>
|
|
8008ed6: e01e b.n 8008f16 <HAL_RCCEx_PeriphCLKConfig+0x12a>
|
|
{
|
|
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
8008ed8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008edc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008ee0: 68da ldr r2, [r3, #12]
|
|
8008ee2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008ee6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008eea: f442 3280 orr.w r2, r2, #65536 ; 0x10000
|
|
8008eee: 60da str r2, [r3, #12]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8008ef0: e015 b.n 8008f1e <HAL_RCCEx_PeriphCLKConfig+0x132>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
8008ef2: 687b ldr r3, [r7, #4]
|
|
8008ef4: 3304 adds r3, #4
|
|
8008ef6: 2100 movs r1, #0
|
|
8008ef8: 4618 mov r0, r3
|
|
8008efa: f000 fb33 bl 8009564 <RCCEx_PLLSAI1_Config>
|
|
8008efe: 4603 mov r3, r0
|
|
8008f00: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8008f02: e00c b.n 8008f1e <HAL_RCCEx_PeriphCLKConfig+0x132>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
8008f04: 687b ldr r3, [r7, #4]
|
|
8008f06: 3320 adds r3, #32
|
|
8008f08: 2100 movs r1, #0
|
|
8008f0a: 4618 mov r0, r3
|
|
8008f0c: f000 fc62 bl 80097d4 <RCCEx_PLLSAI2_Config>
|
|
8008f10: 4603 mov r3, r0
|
|
8008f12: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8008f14: e003 b.n 8008f1e <HAL_RCCEx_PeriphCLKConfig+0x132>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
8008f16: 2301 movs r3, #1
|
|
8008f18: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8008f1a: e000 b.n 8008f1e <HAL_RCCEx_PeriphCLKConfig+0x132>
|
|
break;
|
|
8008f1c: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8008f1e: 7cfb ldrb r3, [r7, #19]
|
|
8008f20: 2b00 cmp r3, #0
|
|
8008f22: d111 bne.n 8008f48 <HAL_RCCEx_PeriphCLKConfig+0x15c>
|
|
{
|
|
/* Set the source of SAI2 clock*/
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
8008f24: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008f28: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008f2c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8008f30: f023 7140 bic.w r1, r3, #50331648 ; 0x3000000
|
|
8008f34: 687b ldr r3, [r7, #4]
|
|
8008f36: 6e9a ldr r2, [r3, #104] ; 0x68
|
|
8008f38: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008f3c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008f40: 430a orrs r2, r1
|
|
8008f42: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
8008f46: e001 b.n 8008f4c <HAL_RCCEx_PeriphCLKConfig+0x160>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8008f48: 7cfb ldrb r3, [r7, #19]
|
|
8008f4a: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
#endif /* SAI2 */
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
8008f4c: 687b ldr r3, [r7, #4]
|
|
8008f4e: 681b ldr r3, [r3, #0]
|
|
8008f50: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8008f54: 2b00 cmp r3, #0
|
|
8008f56: f000 80d4 beq.w 8009102 <HAL_RCCEx_PeriphCLKConfig+0x316>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8008f5a: 2300 movs r3, #0
|
|
8008f5c: 747b strb r3, [r7, #17]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
8008f5e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008f62: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008f66: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8008f68: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8008f6c: 2b00 cmp r3, #0
|
|
8008f6e: d101 bne.n 8008f74 <HAL_RCCEx_PeriphCLKConfig+0x188>
|
|
8008f70: 2301 movs r3, #1
|
|
8008f72: e000 b.n 8008f76 <HAL_RCCEx_PeriphCLKConfig+0x18a>
|
|
8008f74: 2300 movs r3, #0
|
|
8008f76: 2b00 cmp r3, #0
|
|
8008f78: d016 beq.n 8008fa8 <HAL_RCCEx_PeriphCLKConfig+0x1bc>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8008f7a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008f7e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008f82: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
8008f84: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008f88: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008f8c: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
|
|
8008f90: 659a str r2, [r3, #88] ; 0x58
|
|
8008f92: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008f96: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008f9a: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8008f9c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8008fa0: 60bb str r3, [r7, #8]
|
|
8008fa2: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8008fa4: 2301 movs r3, #1
|
|
8008fa6: 747b strb r3, [r7, #17]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8008fa8: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8008fac: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8008fb0: 681a ldr r2, [r3, #0]
|
|
8008fb2: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8008fb6: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8008fba: f442 7280 orr.w r2, r2, #256 ; 0x100
|
|
8008fbe: 601a str r2, [r3, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8008fc0: f7fb fd23 bl 8004a0a <HAL_GetTick>
|
|
8008fc4: 60f8 str r0, [r7, #12]
|
|
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
8008fc6: e009 b.n 8008fdc <HAL_RCCEx_PeriphCLKConfig+0x1f0>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8008fc8: f7fb fd1f bl 8004a0a <HAL_GetTick>
|
|
8008fcc: 4602 mov r2, r0
|
|
8008fce: 68fb ldr r3, [r7, #12]
|
|
8008fd0: 1ad3 subs r3, r2, r3
|
|
8008fd2: 2b02 cmp r3, #2
|
|
8008fd4: d902 bls.n 8008fdc <HAL_RCCEx_PeriphCLKConfig+0x1f0>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8008fd6: 2303 movs r3, #3
|
|
8008fd8: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8008fda: e008 b.n 8008fee <HAL_RCCEx_PeriphCLKConfig+0x202>
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
8008fdc: f44f 43e0 mov.w r3, #28672 ; 0x7000
|
|
8008fe0: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8008fe4: 681b ldr r3, [r3, #0]
|
|
8008fe6: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8008fea: 2b00 cmp r3, #0
|
|
8008fec: d0ec beq.n 8008fc8 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8008fee: 7cfb ldrb r3, [r7, #19]
|
|
8008ff0: 2b00 cmp r3, #0
|
|
8008ff2: d175 bne.n 80090e0 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
8008ff4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8008ff8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8008ffc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8009000: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
8009004: 617b str r3, [r7, #20]
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
8009006: 697b ldr r3, [r7, #20]
|
|
8009008: 2b00 cmp r3, #0
|
|
800900a: d031 beq.n 8009070 <HAL_RCCEx_PeriphCLKConfig+0x284>
|
|
800900c: 687b ldr r3, [r7, #4]
|
|
800900e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
8009012: 697a ldr r2, [r7, #20]
|
|
8009014: 429a cmp r2, r3
|
|
8009016: d02b beq.n 8009070 <HAL_RCCEx_PeriphCLKConfig+0x284>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
8009018: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800901c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009020: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8009024: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
8009028: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
800902a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800902e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009032: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8009036: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800903a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800903e: f442 3280 orr.w r2, r2, #65536 ; 0x10000
|
|
8009042: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8009046: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800904a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800904e: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90
|
|
8009052: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009056: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800905a: f422 3280 bic.w r2, r2, #65536 ; 0x10000
|
|
800905e: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8009062: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009066: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800906a: 697a ldr r2, [r7, #20]
|
|
800906c: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
8009070: 697b ldr r3, [r7, #20]
|
|
8009072: f003 0301 and.w r3, r3, #1
|
|
8009076: 2b00 cmp r3, #0
|
|
8009078: d019 beq.n 80090ae <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800907a: f7fb fcc6 bl 8004a0a <HAL_GetTick>
|
|
800907e: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8009080: e00b b.n 800909a <HAL_RCCEx_PeriphCLKConfig+0x2ae>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8009082: f7fb fcc2 bl 8004a0a <HAL_GetTick>
|
|
8009086: 4602 mov r2, r0
|
|
8009088: 68fb ldr r3, [r7, #12]
|
|
800908a: 1ad3 subs r3, r2, r3
|
|
800908c: f241 3288 movw r2, #5000 ; 0x1388
|
|
8009090: 4293 cmp r3, r2
|
|
8009092: d902 bls.n 800909a <HAL_RCCEx_PeriphCLKConfig+0x2ae>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8009094: 2303 movs r3, #3
|
|
8009096: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8009098: e009 b.n 80090ae <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
800909a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800909e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80090a2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
80090a6: f003 0302 and.w r3, r3, #2
|
|
80090aa: 2b00 cmp r3, #0
|
|
80090ac: d0e9 beq.n 8009082 <HAL_RCCEx_PeriphCLKConfig+0x296>
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
80090ae: 7cfb ldrb r3, [r7, #19]
|
|
80090b0: 2b00 cmp r3, #0
|
|
80090b2: d112 bne.n 80090da <HAL_RCCEx_PeriphCLKConfig+0x2ee>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80090b4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80090b8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80090bc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
80090c0: f423 7140 bic.w r1, r3, #768 ; 0x300
|
|
80090c4: 687b ldr r3, [r7, #4]
|
|
80090c6: f8d3 2084 ldr.w r2, [r3, #132] ; 0x84
|
|
80090ca: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80090ce: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80090d2: 430a orrs r2, r1
|
|
80090d4: f8c3 2090 str.w r2, [r3, #144] ; 0x90
|
|
80090d8: e004 b.n 80090e4 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80090da: 7cfb ldrb r3, [r7, #19]
|
|
80090dc: 74bb strb r3, [r7, #18]
|
|
80090de: e001 b.n 80090e4 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80090e0: 7cfb ldrb r3, [r7, #19]
|
|
80090e2: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
80090e4: 7c7b ldrb r3, [r7, #17]
|
|
80090e6: 2b01 cmp r3, #1
|
|
80090e8: d10b bne.n 8009102 <HAL_RCCEx_PeriphCLKConfig+0x316>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80090ea: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80090ee: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80090f2: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
80090f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80090f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80090fc: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
|
|
8009100: 659a str r2, [r3, #88] ; 0x58
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
8009102: 687b ldr r3, [r7, #4]
|
|
8009104: 681b ldr r3, [r3, #0]
|
|
8009106: f003 0301 and.w r3, r3, #1
|
|
800910a: 2b00 cmp r3, #0
|
|
800910c: d010 beq.n 8009130 <HAL_RCCEx_PeriphCLKConfig+0x344>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
800910e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009112: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009116: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800911a: f023 0103 bic.w r1, r3, #3
|
|
800911e: 687b ldr r3, [r7, #4]
|
|
8009120: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
8009122: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009126: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800912a: 430a orrs r2, r1
|
|
800912c: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
8009130: 687b ldr r3, [r7, #4]
|
|
8009132: 681b ldr r3, [r3, #0]
|
|
8009134: f003 0302 and.w r3, r3, #2
|
|
8009138: 2b00 cmp r3, #0
|
|
800913a: d010 beq.n 800915e <HAL_RCCEx_PeriphCLKConfig+0x372>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
800913c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009140: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009144: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8009148: f023 010c bic.w r1, r3, #12
|
|
800914c: 687b ldr r3, [r7, #4]
|
|
800914e: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
8009150: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009154: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009158: 430a orrs r2, r1
|
|
800915a: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
#if defined(USART3)
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
800915e: 687b ldr r3, [r7, #4]
|
|
8009160: 681b ldr r3, [r3, #0]
|
|
8009162: f003 0304 and.w r3, r3, #4
|
|
8009166: 2b00 cmp r3, #0
|
|
8009168: d010 beq.n 800918c <HAL_RCCEx_PeriphCLKConfig+0x3a0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
800916a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800916e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009172: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8009176: f023 0130 bic.w r1, r3, #48 ; 0x30
|
|
800917a: 687b ldr r3, [r7, #4]
|
|
800917c: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
800917e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009182: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009186: 430a orrs r2, r1
|
|
8009188: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
#endif /* USART3 */
|
|
|
|
#if defined(UART4)
|
|
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
800918c: 687b ldr r3, [r7, #4]
|
|
800918e: 681b ldr r3, [r3, #0]
|
|
8009190: f003 0308 and.w r3, r3, #8
|
|
8009194: 2b00 cmp r3, #0
|
|
8009196: d010 beq.n 80091ba <HAL_RCCEx_PeriphCLKConfig+0x3ce>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
8009198: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800919c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80091a0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
80091a4: f023 01c0 bic.w r1, r3, #192 ; 0xc0
|
|
80091a8: 687b ldr r3, [r7, #4]
|
|
80091aa: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
80091ac: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80091b0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80091b4: 430a orrs r2, r1
|
|
80091b6: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
#endif /* UART4 */
|
|
|
|
#if defined(UART5)
|
|
|
|
/*-------------------------- UART5 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
|
80091ba: 687b ldr r3, [r7, #4]
|
|
80091bc: 681b ldr r3, [r3, #0]
|
|
80091be: f003 0310 and.w r3, r3, #16
|
|
80091c2: 2b00 cmp r3, #0
|
|
80091c4: d010 beq.n 80091e8 <HAL_RCCEx_PeriphCLKConfig+0x3fc>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
|
|
|
/* Configure the UART5 clock source */
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
|
80091c6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80091ca: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80091ce: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
80091d2: f423 7140 bic.w r1, r3, #768 ; 0x300
|
|
80091d6: 687b ldr r3, [r7, #4]
|
|
80091d8: 6c9a ldr r2, [r3, #72] ; 0x48
|
|
80091da: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80091de: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80091e2: 430a orrs r2, r1
|
|
80091e4: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
#endif /* UART5 */
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
80091e8: 687b ldr r3, [r7, #4]
|
|
80091ea: 681b ldr r3, [r3, #0]
|
|
80091ec: f003 0320 and.w r3, r3, #32
|
|
80091f0: 2b00 cmp r3, #0
|
|
80091f2: d010 beq.n 8009216 <HAL_RCCEx_PeriphCLKConfig+0x42a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUART1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
80091f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80091f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80091fc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8009200: f423 6140 bic.w r1, r3, #3072 ; 0xc00
|
|
8009204: 687b ldr r3, [r7, #4]
|
|
8009206: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8009208: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800920c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009210: 430a orrs r2, r1
|
|
8009212: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
8009216: 687b ldr r3, [r7, #4]
|
|
8009218: 681b ldr r3, [r3, #0]
|
|
800921a: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
800921e: 2b00 cmp r3, #0
|
|
8009220: d010 beq.n 8009244 <HAL_RCCEx_PeriphCLKConfig+0x458>
|
|
{
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
8009222: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009226: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800922a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800922e: f423 2140 bic.w r1, r3, #786432 ; 0xc0000
|
|
8009232: 687b ldr r3, [r7, #4]
|
|
8009234: 6dda ldr r2, [r3, #92] ; 0x5c
|
|
8009236: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800923a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800923e: 430a orrs r2, r1
|
|
8009240: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
8009244: 687b ldr r3, [r7, #4]
|
|
8009246: 681b ldr r3, [r3, #0]
|
|
8009248: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
800924c: 2b00 cmp r3, #0
|
|
800924e: d010 beq.n 8009272 <HAL_RCCEx_PeriphCLKConfig+0x486>
|
|
{
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
8009250: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009254: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009258: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800925c: f423 1140 bic.w r1, r3, #3145728 ; 0x300000
|
|
8009260: 687b ldr r3, [r7, #4]
|
|
8009262: 6e1a ldr r2, [r3, #96] ; 0x60
|
|
8009264: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009268: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800926c: 430a orrs r2, r1
|
|
800926e: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
8009272: 687b ldr r3, [r7, #4]
|
|
8009274: 681b ldr r3, [r3, #0]
|
|
8009276: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800927a: 2b00 cmp r3, #0
|
|
800927c: d010 beq.n 80092a0 <HAL_RCCEx_PeriphCLKConfig+0x4b4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
800927e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009282: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009286: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800928a: f423 5140 bic.w r1, r3, #12288 ; 0x3000
|
|
800928e: 687b ldr r3, [r7, #4]
|
|
8009290: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
8009292: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009296: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800929a: 430a orrs r2, r1
|
|
800929c: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
#if defined(I2C2)
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
80092a0: 687b ldr r3, [r7, #4]
|
|
80092a2: 681b ldr r3, [r3, #0]
|
|
80092a4: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
80092a8: 2b00 cmp r3, #0
|
|
80092aa: d010 beq.n 80092ce <HAL_RCCEx_PeriphCLKConfig+0x4e2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
80092ac: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80092b0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80092b4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
80092b8: f423 4140 bic.w r1, r3, #49152 ; 0xc000
|
|
80092bc: 687b ldr r3, [r7, #4]
|
|
80092be: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
80092c0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80092c4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80092c8: 430a orrs r2, r1
|
|
80092ca: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
|
|
#endif /* I2C2 */
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
80092ce: 687b ldr r3, [r7, #4]
|
|
80092d0: 681b ldr r3, [r3, #0]
|
|
80092d2: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
80092d6: 2b00 cmp r3, #0
|
|
80092d8: d010 beq.n 80092fc <HAL_RCCEx_PeriphCLKConfig+0x510>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
80092da: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80092de: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80092e2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
80092e6: f423 3140 bic.w r1, r3, #196608 ; 0x30000
|
|
80092ea: 687b ldr r3, [r7, #4]
|
|
80092ec: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
80092ee: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80092f2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80092f6: 430a orrs r2, r1
|
|
80092f8: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
#endif /* I2C4 */
|
|
|
|
#if defined(USB_OTG_FS) || defined(USB)
|
|
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
80092fc: 687b ldr r3, [r7, #4]
|
|
80092fe: 681b ldr r3, [r3, #0]
|
|
8009300: f403 5300 and.w r3, r3, #8192 ; 0x2000
|
|
8009304: 2b00 cmp r3, #0
|
|
8009306: d034 beq.n 8009372 <HAL_RCCEx_PeriphCLKConfig+0x586>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
8009308: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800930c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009310: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8009314: f023 6140 bic.w r1, r3, #201326592 ; 0xc000000
|
|
8009318: 687b ldr r3, [r7, #4]
|
|
800931a: 6eda ldr r2, [r3, #108] ; 0x6c
|
|
800931c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009320: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009324: 430a orrs r2, r1
|
|
8009326: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
800932a: 687b ldr r3, [r7, #4]
|
|
800932c: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
800932e: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
|
8009332: d10c bne.n 800934e <HAL_RCCEx_PeriphCLKConfig+0x562>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8009334: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009338: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800933c: 68da ldr r2, [r3, #12]
|
|
800933e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009342: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009346: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
800934a: 60da str r2, [r3, #12]
|
|
800934c: e011 b.n 8009372 <HAL_RCCEx_PeriphCLKConfig+0x586>
|
|
}
|
|
else
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
|
|
800934e: 687b ldr r3, [r7, #4]
|
|
8009350: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8009352: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
|
8009356: d10c bne.n 8009372 <HAL_RCCEx_PeriphCLKConfig+0x586>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8009358: 687b ldr r3, [r7, #4]
|
|
800935a: 3304 adds r3, #4
|
|
800935c: 2101 movs r1, #1
|
|
800935e: 4618 mov r0, r3
|
|
8009360: f000 f900 bl 8009564 <RCCEx_PLLSAI1_Config>
|
|
8009364: 4603 mov r3, r0
|
|
8009366: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8009368: 7cfb ldrb r3, [r7, #19]
|
|
800936a: 2b00 cmp r3, #0
|
|
800936c: d001 beq.n 8009372 <HAL_RCCEx_PeriphCLKConfig+0x586>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800936e: 7cfb ldrb r3, [r7, #19]
|
|
8009370: 74bb strb r3, [r7, #18]
|
|
#endif /* USB_OTG_FS || USB */
|
|
|
|
#if defined(SDMMC1)
|
|
|
|
/*-------------------------- SDMMC1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
|
|
8009372: 687b ldr r3, [r7, #4]
|
|
8009374: 681b ldr r3, [r3, #0]
|
|
8009376: f403 2300 and.w r3, r3, #524288 ; 0x80000
|
|
800937a: 2b00 cmp r3, #0
|
|
800937c: d034 beq.n 80093e8 <HAL_RCCEx_PeriphCLKConfig+0x5fc>
|
|
{
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
|
800937e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009382: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009386: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800938a: f023 6140 bic.w r1, r3, #201326592 ; 0xc000000
|
|
800938e: 687b ldr r3, [r7, #4]
|
|
8009390: 6f1a ldr r2, [r3, #112] ; 0x70
|
|
8009392: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009396: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800939a: 430a orrs r2, r1
|
|
800939c: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
|
|
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
|
|
80093a0: 687b ldr r3, [r7, #4]
|
|
80093a2: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80093a4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
|
80093a8: d10c bne.n 80093c4 <HAL_RCCEx_PeriphCLKConfig+0x5d8>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
80093aa: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80093ae: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80093b2: 68da ldr r2, [r3, #12]
|
|
80093b4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80093b8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80093bc: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
80093c0: 60da str r2, [r3, #12]
|
|
80093c2: e011 b.n 80093e8 <HAL_RCCEx_PeriphCLKConfig+0x5fc>
|
|
{
|
|
/* Enable PLLSAI3CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
}
|
|
#endif
|
|
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
|
|
80093c4: 687b ldr r3, [r7, #4]
|
|
80093c6: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80093c8: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
|
80093cc: d10c bne.n 80093e8 <HAL_RCCEx_PeriphCLKConfig+0x5fc>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
80093ce: 687b ldr r3, [r7, #4]
|
|
80093d0: 3304 adds r3, #4
|
|
80093d2: 2101 movs r1, #1
|
|
80093d4: 4618 mov r0, r3
|
|
80093d6: f000 f8c5 bl 8009564 <RCCEx_PLLSAI1_Config>
|
|
80093da: 4603 mov r3, r0
|
|
80093dc: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
80093de: 7cfb ldrb r3, [r7, #19]
|
|
80093e0: 2b00 cmp r3, #0
|
|
80093e2: d001 beq.n 80093e8 <HAL_RCCEx_PeriphCLKConfig+0x5fc>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80093e4: 7cfb ldrb r3, [r7, #19]
|
|
80093e6: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
#endif /* SDMMC1 */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
80093e8: 687b ldr r3, [r7, #4]
|
|
80093ea: 681b ldr r3, [r3, #0]
|
|
80093ec: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
|
80093f0: 2b00 cmp r3, #0
|
|
80093f2: d034 beq.n 800945e <HAL_RCCEx_PeriphCLKConfig+0x672>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
80093f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80093f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80093fc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8009400: f023 6140 bic.w r1, r3, #201326592 ; 0xc000000
|
|
8009404: 687b ldr r3, [r7, #4]
|
|
8009406: 6f5a ldr r2, [r3, #116] ; 0x74
|
|
8009408: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800940c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009410: 430a orrs r2, r1
|
|
8009412: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8009416: 687b ldr r3, [r7, #4]
|
|
8009418: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
800941a: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
|
800941e: d10c bne.n 800943a <HAL_RCCEx_PeriphCLKConfig+0x64e>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8009420: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009424: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009428: 68da ldr r2, [r3, #12]
|
|
800942a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800942e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009432: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
8009436: 60da str r2, [r3, #12]
|
|
8009438: e011 b.n 800945e <HAL_RCCEx_PeriphCLKConfig+0x672>
|
|
}
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
|
|
800943a: 687b ldr r3, [r7, #4]
|
|
800943c: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
800943e: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000
|
|
8009442: d10c bne.n 800945e <HAL_RCCEx_PeriphCLKConfig+0x672>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8009444: 687b ldr r3, [r7, #4]
|
|
8009446: 3304 adds r3, #4
|
|
8009448: 2101 movs r1, #1
|
|
800944a: 4618 mov r0, r3
|
|
800944c: f000 f88a bl 8009564 <RCCEx_PLLSAI1_Config>
|
|
8009450: 4603 mov r3, r0
|
|
8009452: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8009454: 7cfb ldrb r3, [r7, #19]
|
|
8009456: 2b00 cmp r3, #0
|
|
8009458: d001 beq.n 800945e <HAL_RCCEx_PeriphCLKConfig+0x672>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800945a: 7cfb ldrb r3, [r7, #19]
|
|
800945c: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
#if !defined(STM32L412xx) && !defined(STM32L422xx)
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
800945e: 687b ldr r3, [r7, #4]
|
|
8009460: 681b ldr r3, [r3, #0]
|
|
8009462: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
8009466: 2b00 cmp r3, #0
|
|
8009468: d035 beq.n 80094d6 <HAL_RCCEx_PeriphCLKConfig+0x6ea>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
800946a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800946e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009472: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8009476: f023 5140 bic.w r1, r3, #805306368 ; 0x30000000
|
|
800947a: 687b ldr r3, [r7, #4]
|
|
800947c: 6f9a ldr r2, [r3, #120] ; 0x78
|
|
800947e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009482: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009486: 430a orrs r2, r1
|
|
8009488: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
|
800948c: 687b ldr r3, [r7, #4]
|
|
800948e: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8009490: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
|
|
8009494: d10d bne.n 80094b2 <HAL_RCCEx_PeriphCLKConfig+0x6c6>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
|
|
8009496: 687b ldr r3, [r7, #4]
|
|
8009498: 3304 adds r3, #4
|
|
800949a: 2102 movs r1, #2
|
|
800949c: 4618 mov r0, r3
|
|
800949e: f000 f861 bl 8009564 <RCCEx_PLLSAI1_Config>
|
|
80094a2: 4603 mov r3, r0
|
|
80094a4: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
80094a6: 7cfb ldrb r3, [r7, #19]
|
|
80094a8: 2b00 cmp r3, #0
|
|
80094aa: d014 beq.n 80094d6 <HAL_RCCEx_PeriphCLKConfig+0x6ea>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80094ac: 7cfb ldrb r3, [r7, #19]
|
|
80094ae: 74bb strb r3, [r7, #18]
|
|
80094b0: e011 b.n 80094d6 <HAL_RCCEx_PeriphCLKConfig+0x6ea>
|
|
}
|
|
#endif /* RCC_PLLSAI1_SUPPORT */
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
|
|
|
|
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
|
|
80094b2: 687b ldr r3, [r7, #4]
|
|
80094b4: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
80094b6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
80094ba: d10c bne.n 80094d6 <HAL_RCCEx_PeriphCLKConfig+0x6ea>
|
|
{
|
|
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
|
|
80094bc: 687b ldr r3, [r7, #4]
|
|
80094be: 3320 adds r3, #32
|
|
80094c0: 2102 movs r1, #2
|
|
80094c2: 4618 mov r0, r3
|
|
80094c4: f000 f986 bl 80097d4 <RCCEx_PLLSAI2_Config>
|
|
80094c8: 4603 mov r3, r0
|
|
80094ca: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
80094cc: 7cfb ldrb r3, [r7, #19]
|
|
80094ce: 2b00 cmp r3, #0
|
|
80094d0: d001 beq.n 80094d6 <HAL_RCCEx_PeriphCLKConfig+0x6ea>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80094d2: 7cfb ldrb r3, [r7, #19]
|
|
80094d4: 74bb strb r3, [r7, #18]
|
|
#endif /* !STM32L412xx && !STM32L422xx */
|
|
|
|
#if defined(SWPMI1)
|
|
|
|
/*-------------------------- SWPMI1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
|
|
80094d6: 687b ldr r3, [r7, #4]
|
|
80094d8: 681b ldr r3, [r3, #0]
|
|
80094da: f403 4300 and.w r3, r3, #32768 ; 0x8000
|
|
80094de: 2b00 cmp r3, #0
|
|
80094e0: d010 beq.n 8009504 <HAL_RCCEx_PeriphCLKConfig+0x718>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
|
|
|
|
/* Configure the SWPMI1 clock source */
|
|
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
|
|
80094e2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80094e6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80094ea: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
80094ee: f023 4180 bic.w r1, r3, #1073741824 ; 0x40000000
|
|
80094f2: 687b ldr r3, [r7, #4]
|
|
80094f4: 6fda ldr r2, [r3, #124] ; 0x7c
|
|
80094f6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80094fa: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80094fe: 430a orrs r2, r1
|
|
8009500: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
#endif /* SWPMI1 */
|
|
|
|
#if defined(DFSDM1_Filter0)
|
|
|
|
/*-------------------------- DFSDM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
|
|
8009504: 687b ldr r3, [r7, #4]
|
|
8009506: 681b ldr r3, [r3, #0]
|
|
8009508: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
800950c: 2b00 cmp r3, #0
|
|
800950e: d011 beq.n 8009534 <HAL_RCCEx_PeriphCLKConfig+0x748>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
|
|
|
|
/* Configure the DFSDM1 interface clock source */
|
|
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
|
|
8009510: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009514: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009518: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800951c: f023 4100 bic.w r1, r3, #2147483648 ; 0x80000000
|
|
8009520: 687b ldr r3, [r7, #4]
|
|
8009522: f8d3 2080 ldr.w r2, [r3, #128] ; 0x80
|
|
8009526: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800952a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800952e: 430a orrs r2, r1
|
|
8009530: f8c3 2088 str.w r2, [r3, #136] ; 0x88
|
|
}
|
|
}
|
|
|
|
#endif /* OCTOSPI1 || OCTOSPI2 */
|
|
|
|
return status;
|
|
8009534: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8009536: 4618 mov r0, r3
|
|
8009538: 3718 adds r7, #24
|
|
800953a: 46bd mov sp, r7
|
|
800953c: bd80 pop {r7, pc}
|
|
|
|
0800953e <HAL_RCCEx_EnableMSIPLLMode>:
|
|
* @note Prior to enable the PLL-mode of the MSI for automatic hardware
|
|
* calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCCEx_EnableMSIPLLMode(void)
|
|
{
|
|
800953e: b480 push {r7}
|
|
8009540: af00 add r7, sp, #0
|
|
SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ;
|
|
8009542: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009546: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800954a: 681a ldr r2, [r3, #0]
|
|
800954c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009550: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009554: f042 0204 orr.w r2, r2, #4
|
|
8009558: 601a str r2, [r3, #0]
|
|
}
|
|
800955a: bf00 nop
|
|
800955c: 46bd mov sp, r7
|
|
800955e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009562: 4770 bx lr
|
|
|
|
08009564 <RCCEx_PLLSAI1_Config>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
|
|
{
|
|
8009564: b580 push {r7, lr}
|
|
8009566: b084 sub sp, #16
|
|
8009568: af00 add r7, sp, #0
|
|
800956a: 6078 str r0, [r7, #4]
|
|
800956c: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800956e: 2300 movs r3, #0
|
|
8009570: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
|
|
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
|
|
|
|
/* Check that PLLSAI1 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8009572: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009576: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800957a: 68db ldr r3, [r3, #12]
|
|
800957c: f003 0303 and.w r3, r3, #3
|
|
8009580: 2b00 cmp r3, #0
|
|
8009582: d01e beq.n 80095c2 <RCCEx_PLLSAI1_Config+0x5e>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
|
|
8009584: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009588: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800958c: 68db ldr r3, [r3, #12]
|
|
800958e: f003 0203 and.w r2, r3, #3
|
|
8009592: 687b ldr r3, [r7, #4]
|
|
8009594: 681b ldr r3, [r3, #0]
|
|
8009596: 429a cmp r2, r3
|
|
8009598: d110 bne.n 80095bc <RCCEx_PLLSAI1_Config+0x58>
|
|
||
|
|
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
|
|
800959a: 687b ldr r3, [r7, #4]
|
|
800959c: 681b ldr r3, [r3, #0]
|
|
||
|
|
800959e: 2b00 cmp r3, #0
|
|
80095a0: d00c beq.n 80095bc <RCCEx_PLLSAI1_Config+0x58>
|
|
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
|
|
80095a2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80095a6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80095aa: 68db ldr r3, [r3, #12]
|
|
80095ac: 091b lsrs r3, r3, #4
|
|
80095ae: f003 0307 and.w r3, r3, #7
|
|
80095b2: 1c5a adds r2, r3, #1
|
|
80095b4: 687b ldr r3, [r7, #4]
|
|
80095b6: 685b ldr r3, [r3, #4]
|
|
||
|
|
80095b8: 429a cmp r2, r3
|
|
80095ba: d059 beq.n 8009670 <RCCEx_PLLSAI1_Config+0x10c>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
80095bc: 2301 movs r3, #1
|
|
80095be: 73fb strb r3, [r7, #15]
|
|
80095c0: e056 b.n 8009670 <RCCEx_PLLSAI1_Config+0x10c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI1 clock source availability */
|
|
switch(PllSai1->PLLSAI1Source)
|
|
80095c2: 687b ldr r3, [r7, #4]
|
|
80095c4: 681b ldr r3, [r3, #0]
|
|
80095c6: 2b03 cmp r3, #3
|
|
80095c8: d01e beq.n 8009608 <RCCEx_PLLSAI1_Config+0xa4>
|
|
80095ca: 2b03 cmp r3, #3
|
|
80095cc: d831 bhi.n 8009632 <RCCEx_PLLSAI1_Config+0xce>
|
|
80095ce: 2b01 cmp r3, #1
|
|
80095d0: d002 beq.n 80095d8 <RCCEx_PLLSAI1_Config+0x74>
|
|
80095d2: 2b02 cmp r3, #2
|
|
80095d4: d00c beq.n 80095f0 <RCCEx_PLLSAI1_Config+0x8c>
|
|
80095d6: e02c b.n 8009632 <RCCEx_PLLSAI1_Config+0xce>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
80095d8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80095dc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80095e0: 681b ldr r3, [r3, #0]
|
|
80095e2: f003 0302 and.w r3, r3, #2
|
|
80095e6: 2b00 cmp r3, #0
|
|
80095e8: d126 bne.n 8009638 <RCCEx_PLLSAI1_Config+0xd4>
|
|
{
|
|
status = HAL_ERROR;
|
|
80095ea: 2301 movs r3, #1
|
|
80095ec: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
80095ee: e023 b.n 8009638 <RCCEx_PLLSAI1_Config+0xd4>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
80095f0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80095f4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80095f8: 681b ldr r3, [r3, #0]
|
|
80095fa: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
80095fe: 2b00 cmp r3, #0
|
|
8009600: d11c bne.n 800963c <RCCEx_PLLSAI1_Config+0xd8>
|
|
{
|
|
status = HAL_ERROR;
|
|
8009602: 2301 movs r3, #1
|
|
8009604: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8009606: e019 b.n 800963c <RCCEx_PLLSAI1_Config+0xd8>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8009608: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800960c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009610: 681b ldr r3, [r3, #0]
|
|
8009612: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8009616: 2b00 cmp r3, #0
|
|
8009618: d112 bne.n 8009640 <RCCEx_PLLSAI1_Config+0xdc>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
800961a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800961e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009622: 681b ldr r3, [r3, #0]
|
|
8009624: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
|
8009628: 2b00 cmp r3, #0
|
|
800962a: d109 bne.n 8009640 <RCCEx_PLLSAI1_Config+0xdc>
|
|
{
|
|
status = HAL_ERROR;
|
|
800962c: 2301 movs r3, #1
|
|
800962e: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8009630: e006 b.n 8009640 <RCCEx_PLLSAI1_Config+0xdc>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8009632: 2301 movs r3, #1
|
|
8009634: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009636: e004 b.n 8009642 <RCCEx_PLLSAI1_Config+0xde>
|
|
break;
|
|
8009638: bf00 nop
|
|
800963a: e002 b.n 8009642 <RCCEx_PLLSAI1_Config+0xde>
|
|
break;
|
|
800963c: bf00 nop
|
|
800963e: e000 b.n 8009642 <RCCEx_PLLSAI1_Config+0xde>
|
|
break;
|
|
8009640: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8009642: 7bfb ldrb r3, [r7, #15]
|
|
8009644: 2b00 cmp r3, #0
|
|
8009646: d113 bne.n 8009670 <RCCEx_PLLSAI1_Config+0x10c>
|
|
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI1 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
|
|
#else
|
|
/* Set PLLSAI1 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
8009648: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800964c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009650: 68db ldr r3, [r3, #12]
|
|
8009652: f023 0173 bic.w r1, r3, #115 ; 0x73
|
|
8009656: 687b ldr r3, [r7, #4]
|
|
8009658: 681a ldr r2, [r3, #0]
|
|
800965a: 687b ldr r3, [r7, #4]
|
|
800965c: 685b ldr r3, [r3, #4]
|
|
800965e: 3b01 subs r3, #1
|
|
8009660: 011b lsls r3, r3, #4
|
|
8009662: 431a orrs r2, r3
|
|
8009664: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009668: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800966c: 430a orrs r2, r1
|
|
800966e: 60da str r2, [r3, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8009670: 7bfb ldrb r3, [r7, #15]
|
|
8009672: 2b00 cmp r3, #0
|
|
8009674: f040 80a9 bne.w 80097ca <RCCEx_PLLSAI1_Config+0x266>
|
|
{
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
8009678: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800967c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009680: 681a ldr r2, [r3, #0]
|
|
8009682: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009686: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800968a: f022 6280 bic.w r2, r2, #67108864 ; 0x4000000
|
|
800968e: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009690: f7fb f9bb bl 8004a0a <HAL_GetTick>
|
|
8009694: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8009696: e009 b.n 80096ac <RCCEx_PLLSAI1_Config+0x148>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8009698: f7fb f9b7 bl 8004a0a <HAL_GetTick>
|
|
800969c: 4602 mov r2, r0
|
|
800969e: 68bb ldr r3, [r7, #8]
|
|
80096a0: 1ad3 subs r3, r2, r3
|
|
80096a2: 2b02 cmp r3, #2
|
|
80096a4: d902 bls.n 80096ac <RCCEx_PLLSAI1_Config+0x148>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
80096a6: 2303 movs r3, #3
|
|
80096a8: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80096aa: e008 b.n 80096be <RCCEx_PLLSAI1_Config+0x15a>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
80096ac: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80096b0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80096b4: 681b ldr r3, [r3, #0]
|
|
80096b6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
80096ba: 2b00 cmp r3, #0
|
|
80096bc: d1ec bne.n 8009698 <RCCEx_PLLSAI1_Config+0x134>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80096be: 7bfb ldrb r3, [r7, #15]
|
|
80096c0: 2b00 cmp r3, #0
|
|
80096c2: f040 8082 bne.w 80097ca <RCCEx_PLLSAI1_Config+0x266>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
80096c6: 683b ldr r3, [r7, #0]
|
|
80096c8: 2b00 cmp r3, #0
|
|
80096ca: d117 bne.n 80096fc <RCCEx_PLLSAI1_Config+0x198>
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
80096cc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80096d0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80096d4: 691b ldr r3, [r3, #16]
|
|
80096d6: f423 331f bic.w r3, r3, #162816 ; 0x27c00
|
|
80096da: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
80096de: 687a ldr r2, [r7, #4]
|
|
80096e0: 6892 ldr r2, [r2, #8]
|
|
80096e2: 0211 lsls r1, r2, #8
|
|
80096e4: 687a ldr r2, [r7, #4]
|
|
80096e6: 68d2 ldr r2, [r2, #12]
|
|
80096e8: 0912 lsrs r2, r2, #4
|
|
80096ea: 0452 lsls r2, r2, #17
|
|
80096ec: 4311 orrs r1, r2
|
|
80096ee: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
80096f2: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
80096f6: 430b orrs r3, r1
|
|
80096f8: 6113 str r3, [r2, #16]
|
|
80096fa: e033 b.n 8009764 <RCCEx_PLLSAI1_Config+0x200>
|
|
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
else if(Divider == DIVIDER_Q_UPDATE)
|
|
80096fc: 683b ldr r3, [r7, #0]
|
|
80096fe: 2b01 cmp r3, #1
|
|
8009700: d118 bne.n 8009734 <RCCEx_PLLSAI1_Config+0x1d0>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8009702: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009706: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800970a: 691b ldr r3, [r3, #16]
|
|
800970c: f423 03c0 bic.w r3, r3, #6291456 ; 0x600000
|
|
8009710: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
|
8009714: 687a ldr r2, [r7, #4]
|
|
8009716: 6892 ldr r2, [r2, #8]
|
|
8009718: 0211 lsls r1, r2, #8
|
|
800971a: 687a ldr r2, [r7, #4]
|
|
800971c: 6912 ldr r2, [r2, #16]
|
|
800971e: 0852 lsrs r2, r2, #1
|
|
8009720: 3a01 subs r2, #1
|
|
8009722: 0552 lsls r2, r2, #21
|
|
8009724: 4311 orrs r1, r2
|
|
8009726: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
800972a: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
800972e: 430b orrs r3, r1
|
|
8009730: 6113 str r3, [r2, #16]
|
|
8009732: e017 b.n 8009764 <RCCEx_PLLSAI1_Config+0x200>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8009734: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009738: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800973c: 691b ldr r3, [r3, #16]
|
|
800973e: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000
|
|
8009742: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
|
8009746: 687a ldr r2, [r7, #4]
|
|
8009748: 6892 ldr r2, [r2, #8]
|
|
800974a: 0211 lsls r1, r2, #8
|
|
800974c: 687a ldr r2, [r7, #4]
|
|
800974e: 6952 ldr r2, [r2, #20]
|
|
8009750: 0852 lsrs r2, r2, #1
|
|
8009752: 3a01 subs r2, #1
|
|
8009754: 0652 lsls r2, r2, #25
|
|
8009756: 4311 orrs r1, r2
|
|
8009758: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
800975c: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
8009760: 430b orrs r3, r1
|
|
8009762: 6113 str r3, [r2, #16]
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
8009764: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009768: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800976c: 681a ldr r2, [r3, #0]
|
|
800976e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009772: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009776: f042 6280 orr.w r2, r2, #67108864 ; 0x4000000
|
|
800977a: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800977c: f7fb f945 bl 8004a0a <HAL_GetTick>
|
|
8009780: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8009782: e009 b.n 8009798 <RCCEx_PLLSAI1_Config+0x234>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8009784: f7fb f941 bl 8004a0a <HAL_GetTick>
|
|
8009788: 4602 mov r2, r0
|
|
800978a: 68bb ldr r3, [r7, #8]
|
|
800978c: 1ad3 subs r3, r2, r3
|
|
800978e: 2b02 cmp r3, #2
|
|
8009790: d902 bls.n 8009798 <RCCEx_PLLSAI1_Config+0x234>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8009792: 2303 movs r3, #3
|
|
8009794: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009796: e008 b.n 80097aa <RCCEx_PLLSAI1_Config+0x246>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8009798: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800979c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80097a0: 681b ldr r3, [r3, #0]
|
|
80097a2: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
80097a6: 2b00 cmp r3, #0
|
|
80097a8: d0ec beq.n 8009784 <RCCEx_PLLSAI1_Config+0x220>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80097aa: 7bfb ldrb r3, [r7, #15]
|
|
80097ac: 2b00 cmp r3, #0
|
|
80097ae: d10c bne.n 80097ca <RCCEx_PLLSAI1_Config+0x266>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
|
|
80097b0: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80097b4: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80097b8: 6919 ldr r1, [r3, #16]
|
|
80097ba: 687b ldr r3, [r7, #4]
|
|
80097bc: 699a ldr r2, [r3, #24]
|
|
80097be: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80097c2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80097c6: 430a orrs r2, r1
|
|
80097c8: 611a str r2, [r3, #16]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
80097ca: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80097cc: 4618 mov r0, r3
|
|
80097ce: 3710 adds r7, #16
|
|
80097d0: 46bd mov sp, r7
|
|
80097d2: bd80 pop {r7, pc}
|
|
|
|
080097d4 <RCCEx_PLLSAI2_Config>:
|
|
* @note PLLSAI2 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
|
|
{
|
|
80097d4: b580 push {r7, lr}
|
|
80097d6: b084 sub sp, #16
|
|
80097d8: af00 add r7, sp, #0
|
|
80097da: 6078 str r0, [r7, #4]
|
|
80097dc: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80097de: 2300 movs r3, #0
|
|
80097e0: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
|
|
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
|
|
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
|
|
|
|
/* Check that PLLSAI2 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
80097e2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80097e6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80097ea: 68db ldr r3, [r3, #12]
|
|
80097ec: f003 0303 and.w r3, r3, #3
|
|
80097f0: 2b00 cmp r3, #0
|
|
80097f2: d01e beq.n 8009832 <RCCEx_PLLSAI2_Config+0x5e>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
|
|
80097f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80097f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80097fc: 68db ldr r3, [r3, #12]
|
|
80097fe: f003 0203 and.w r2, r3, #3
|
|
8009802: 687b ldr r3, [r7, #4]
|
|
8009804: 681b ldr r3, [r3, #0]
|
|
8009806: 429a cmp r2, r3
|
|
8009808: d110 bne.n 800982c <RCCEx_PLLSAI2_Config+0x58>
|
|
||
|
|
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
|
|
800980a: 687b ldr r3, [r7, #4]
|
|
800980c: 681b ldr r3, [r3, #0]
|
|
||
|
|
800980e: 2b00 cmp r3, #0
|
|
8009810: d00c beq.n 800982c <RCCEx_PLLSAI2_Config+0x58>
|
|
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
|
|
8009812: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009816: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800981a: 68db ldr r3, [r3, #12]
|
|
800981c: 091b lsrs r3, r3, #4
|
|
800981e: f003 0307 and.w r3, r3, #7
|
|
8009822: 1c5a adds r2, r3, #1
|
|
8009824: 687b ldr r3, [r7, #4]
|
|
8009826: 685b ldr r3, [r3, #4]
|
|
||
|
|
8009828: 429a cmp r2, r3
|
|
800982a: d059 beq.n 80098e0 <RCCEx_PLLSAI2_Config+0x10c>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
800982c: 2301 movs r3, #1
|
|
800982e: 73fb strb r3, [r7, #15]
|
|
8009830: e056 b.n 80098e0 <RCCEx_PLLSAI2_Config+0x10c>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI2 clock source availability */
|
|
switch(PllSai2->PLLSAI2Source)
|
|
8009832: 687b ldr r3, [r7, #4]
|
|
8009834: 681b ldr r3, [r3, #0]
|
|
8009836: 2b03 cmp r3, #3
|
|
8009838: d01e beq.n 8009878 <RCCEx_PLLSAI2_Config+0xa4>
|
|
800983a: 2b03 cmp r3, #3
|
|
800983c: d831 bhi.n 80098a2 <RCCEx_PLLSAI2_Config+0xce>
|
|
800983e: 2b01 cmp r3, #1
|
|
8009840: d002 beq.n 8009848 <RCCEx_PLLSAI2_Config+0x74>
|
|
8009842: 2b02 cmp r3, #2
|
|
8009844: d00c beq.n 8009860 <RCCEx_PLLSAI2_Config+0x8c>
|
|
8009846: e02c b.n 80098a2 <RCCEx_PLLSAI2_Config+0xce>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8009848: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800984c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009850: 681b ldr r3, [r3, #0]
|
|
8009852: f003 0302 and.w r3, r3, #2
|
|
8009856: 2b00 cmp r3, #0
|
|
8009858: d126 bne.n 80098a8 <RCCEx_PLLSAI2_Config+0xd4>
|
|
{
|
|
status = HAL_ERROR;
|
|
800985a: 2301 movs r3, #1
|
|
800985c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
800985e: e023 b.n 80098a8 <RCCEx_PLLSAI2_Config+0xd4>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8009860: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009864: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009868: 681b ldr r3, [r3, #0]
|
|
800986a: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
800986e: 2b00 cmp r3, #0
|
|
8009870: d11c bne.n 80098ac <RCCEx_PLLSAI2_Config+0xd8>
|
|
{
|
|
status = HAL_ERROR;
|
|
8009872: 2301 movs r3, #1
|
|
8009874: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8009876: e019 b.n 80098ac <RCCEx_PLLSAI2_Config+0xd8>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8009878: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800987c: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009880: 681b ldr r3, [r3, #0]
|
|
8009882: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8009886: 2b00 cmp r3, #0
|
|
8009888: d112 bne.n 80098b0 <RCCEx_PLLSAI2_Config+0xdc>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
800988a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800988e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009892: 681b ldr r3, [r3, #0]
|
|
8009894: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
|
8009898: 2b00 cmp r3, #0
|
|
800989a: d109 bne.n 80098b0 <RCCEx_PLLSAI2_Config+0xdc>
|
|
{
|
|
status = HAL_ERROR;
|
|
800989c: 2301 movs r3, #1
|
|
800989e: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
80098a0: e006 b.n 80098b0 <RCCEx_PLLSAI2_Config+0xdc>
|
|
default:
|
|
status = HAL_ERROR;
|
|
80098a2: 2301 movs r3, #1
|
|
80098a4: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80098a6: e004 b.n 80098b2 <RCCEx_PLLSAI2_Config+0xde>
|
|
break;
|
|
80098a8: bf00 nop
|
|
80098aa: e002 b.n 80098b2 <RCCEx_PLLSAI2_Config+0xde>
|
|
break;
|
|
80098ac: bf00 nop
|
|
80098ae: e000 b.n 80098b2 <RCCEx_PLLSAI2_Config+0xde>
|
|
break;
|
|
80098b0: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80098b2: 7bfb ldrb r3, [r7, #15]
|
|
80098b4: 2b00 cmp r3, #0
|
|
80098b6: d113 bne.n 80098e0 <RCCEx_PLLSAI2_Config+0x10c>
|
|
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI2 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
|
|
#else
|
|
/* Set PLLSAI2 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
80098b8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80098bc: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80098c0: 68db ldr r3, [r3, #12]
|
|
80098c2: f023 0173 bic.w r1, r3, #115 ; 0x73
|
|
80098c6: 687b ldr r3, [r7, #4]
|
|
80098c8: 681a ldr r2, [r3, #0]
|
|
80098ca: 687b ldr r3, [r7, #4]
|
|
80098cc: 685b ldr r3, [r3, #4]
|
|
80098ce: 3b01 subs r3, #1
|
|
80098d0: 011b lsls r3, r3, #4
|
|
80098d2: 431a orrs r2, r3
|
|
80098d4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80098d8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80098dc: 430a orrs r2, r1
|
|
80098de: 60da str r2, [r3, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80098e0: 7bfb ldrb r3, [r7, #15]
|
|
80098e2: 2b00 cmp r3, #0
|
|
80098e4: f040 808c bne.w 8009a00 <RCCEx_PLLSAI2_Config+0x22c>
|
|
{
|
|
/* Disable the PLLSAI2 */
|
|
__HAL_RCC_PLLSAI2_DISABLE();
|
|
80098e8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80098ec: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80098f0: 681a ldr r2, [r3, #0]
|
|
80098f2: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80098f6: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80098fa: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
|
|
80098fe: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009900: f7fb f883 bl 8004a0a <HAL_GetTick>
|
|
8009904: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
8009906: e009 b.n 800991c <RCCEx_PLLSAI2_Config+0x148>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
8009908: f7fb f87f bl 8004a0a <HAL_GetTick>
|
|
800990c: 4602 mov r2, r0
|
|
800990e: 68bb ldr r3, [r7, #8]
|
|
8009910: 1ad3 subs r3, r2, r3
|
|
8009912: 2b02 cmp r3, #2
|
|
8009914: d902 bls.n 800991c <RCCEx_PLLSAI2_Config+0x148>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8009916: 2303 movs r3, #3
|
|
8009918: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800991a: e008 b.n 800992e <RCCEx_PLLSAI2_Config+0x15a>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
800991c: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8009920: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009924: 681b ldr r3, [r3, #0]
|
|
8009926: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
|
800992a: 2b00 cmp r3, #0
|
|
800992c: d1ec bne.n 8009908 <RCCEx_PLLSAI2_Config+0x134>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
800992e: 7bfb ldrb r3, [r7, #15]
|
|
8009930: 2b00 cmp r3, #0
|
|
8009932: d165 bne.n 8009a00 <RCCEx_PLLSAI2_Config+0x22c>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8009934: 683b ldr r3, [r7, #0]
|
|
8009936: 2b00 cmp r3, #0
|
|
8009938: d117 bne.n 800996a <RCCEx_PLLSAI2_Config+0x196>
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
800993a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800993e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009942: 695b ldr r3, [r3, #20]
|
|
8009944: f423 331f bic.w r3, r3, #162816 ; 0x27c00
|
|
8009948: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
800994c: 687a ldr r2, [r7, #4]
|
|
800994e: 6892 ldr r2, [r2, #8]
|
|
8009950: 0211 lsls r1, r2, #8
|
|
8009952: 687a ldr r2, [r7, #4]
|
|
8009954: 68d2 ldr r2, [r2, #12]
|
|
8009956: 0912 lsrs r2, r2, #4
|
|
8009958: 0452 lsls r2, r2, #17
|
|
800995a: 4311 orrs r1, r2
|
|
800995c: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
8009960: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
8009964: 430b orrs r3, r1
|
|
8009966: 6153 str r3, [r2, #20]
|
|
8009968: e017 b.n 800999a <RCCEx_PLLSAI2_Config+0x1c6>
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
|
|
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
800996a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800996e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
8009972: 695b ldr r3, [r3, #20]
|
|
8009974: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000
|
|
8009978: f423 43fe bic.w r3, r3, #32512 ; 0x7f00
|
|
800997c: 687a ldr r2, [r7, #4]
|
|
800997e: 6892 ldr r2, [r2, #8]
|
|
8009980: 0211 lsls r1, r2, #8
|
|
8009982: 687a ldr r2, [r7, #4]
|
|
8009984: 6912 ldr r2, [r2, #16]
|
|
8009986: 0852 lsrs r2, r2, #1
|
|
8009988: 3a01 subs r2, #1
|
|
800998a: 0652 lsls r2, r2, #25
|
|
800998c: 4311 orrs r1, r2
|
|
800998e: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
8009992: f2c4 0202 movt r2, #16386 ; 0x4002
|
|
8009996: 430b orrs r3, r1
|
|
8009998: 6153 str r3, [r2, #20]
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
|
|
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
|
|
__HAL_RCC_PLLSAI2_ENABLE();
|
|
800999a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800999e: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80099a2: 681a ldr r2, [r3, #0]
|
|
80099a4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80099a8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80099ac: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
|
|
80099b0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80099b2: f7fb f82a bl 8004a0a <HAL_GetTick>
|
|
80099b6: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
80099b8: e009 b.n 80099ce <RCCEx_PLLSAI2_Config+0x1fa>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
80099ba: f7fb f826 bl 8004a0a <HAL_GetTick>
|
|
80099be: 4602 mov r2, r0
|
|
80099c0: 68bb ldr r3, [r7, #8]
|
|
80099c2: 1ad3 subs r3, r2, r3
|
|
80099c4: 2b02 cmp r3, #2
|
|
80099c6: d902 bls.n 80099ce <RCCEx_PLLSAI2_Config+0x1fa>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
80099c8: 2303 movs r3, #3
|
|
80099ca: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80099cc: e008 b.n 80099e0 <RCCEx_PLLSAI2_Config+0x20c>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
80099ce: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80099d2: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80099d6: 681b ldr r3, [r3, #0]
|
|
80099d8: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
|
80099dc: 2b00 cmp r3, #0
|
|
80099de: d0ec beq.n 80099ba <RCCEx_PLLSAI2_Config+0x1e6>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
80099e0: 7bfb ldrb r3, [r7, #15]
|
|
80099e2: 2b00 cmp r3, #0
|
|
80099e4: d10c bne.n 8009a00 <RCCEx_PLLSAI2_Config+0x22c>
|
|
{
|
|
/* Configure the PLLSAI2 Clock output(s) */
|
|
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
|
|
80099e6: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80099ea: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80099ee: 6959 ldr r1, [r3, #20]
|
|
80099f0: 687b ldr r3, [r7, #4]
|
|
80099f2: 695a ldr r2, [r3, #20]
|
|
80099f4: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80099f8: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
80099fc: 430a orrs r2, r1
|
|
80099fe: 615a str r2, [r3, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8009a00: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009a02: 4618 mov r0, r3
|
|
8009a04: 3710 adds r7, #16
|
|
8009a06: 46bd mov sp, r7
|
|
8009a08: bd80 pop {r7, pc}
|
|
|
|
08009a0a <HAL_RTC_Init>:
|
|
* @brief Initialize the RTC peripheral
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8009a0a: b580 push {r7, lr}
|
|
8009a0c: b084 sub sp, #16
|
|
8009a0e: af00 add r7, sp, #0
|
|
8009a10: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_ERROR;
|
|
8009a12: 2301 movs r3, #1
|
|
8009a14: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the RTC peripheral state */
|
|
if (hrtc != NULL)
|
|
8009a16: 687b ldr r3, [r7, #4]
|
|
8009a18: 2b00 cmp r3, #0
|
|
8009a1a: d06c beq.n 8009af6 <HAL_RTC_Init+0xec>
|
|
{
|
|
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
|
|
}
|
|
}
|
|
#else /* #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
|
|
if (hrtc->State == HAL_RTC_STATE_RESET)
|
|
8009a1c: 687b ldr r3, [r7, #4]
|
|
8009a1e: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
|
|
8009a22: b2db uxtb r3, r3
|
|
8009a24: 2b00 cmp r3, #0
|
|
8009a26: d106 bne.n 8009a36 <HAL_RTC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hrtc->Lock = HAL_UNLOCKED;
|
|
8009a28: 687b ldr r3, [r7, #4]
|
|
8009a2a: 2200 movs r2, #0
|
|
8009a2c: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
/* Initialize RTC MSP */
|
|
HAL_RTC_MspInit(hrtc);
|
|
8009a30: 6878 ldr r0, [r7, #4]
|
|
8009a32: f7f8 ff73 bl 800291c <HAL_RTC_MspInit>
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
/* Process TAMP ip offset from RTC one */
|
|
hrtc->TampOffset = (TAMP_BASE - RTC_BASE);
|
|
#endif
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
8009a36: 687b ldr r3, [r7, #4]
|
|
8009a38: 2202 movs r2, #2
|
|
8009a3a: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
8009a3e: 687b ldr r3, [r7, #4]
|
|
8009a40: 681b ldr r3, [r3, #0]
|
|
8009a42: 22ca movs r2, #202 ; 0xca
|
|
8009a44: 625a str r2, [r3, #36] ; 0x24
|
|
8009a46: 687b ldr r3, [r7, #4]
|
|
8009a48: 681b ldr r3, [r3, #0]
|
|
8009a4a: 2253 movs r2, #83 ; 0x53
|
|
8009a4c: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Enter Initialization mode */
|
|
status = RTC_EnterInitMode(hrtc);
|
|
8009a4e: 6878 ldr r0, [r7, #4]
|
|
8009a50: f000 f87c bl 8009b4c <RTC_EnterInitMode>
|
|
8009a54: 4603 mov r3, r0
|
|
8009a56: 73fb strb r3, [r7, #15]
|
|
|
|
if (status == HAL_OK)
|
|
8009a58: 7bfb ldrb r3, [r7, #15]
|
|
8009a5a: 2b00 cmp r3, #0
|
|
8009a5c: d14b bne.n 8009af6 <HAL_RTC_Init+0xec>
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
/* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */
|
|
hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
|
|
#else
|
|
/* Clear RTC_CR FMT, OSEL and POL Bits */
|
|
hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL);
|
|
8009a5e: 687b ldr r3, [r7, #4]
|
|
8009a60: 681b ldr r3, [r3, #0]
|
|
8009a62: 689b ldr r3, [r3, #8]
|
|
8009a64: 687a ldr r2, [r7, #4]
|
|
8009a66: 6812 ldr r2, [r2, #0]
|
|
8009a68: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000
|
|
8009a6c: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
8009a70: 6093 str r3, [r2, #8]
|
|
#endif
|
|
/* Set RTC_CR register */
|
|
hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
|
|
8009a72: 687b ldr r3, [r7, #4]
|
|
8009a74: 681b ldr r3, [r3, #0]
|
|
8009a76: 6899 ldr r1, [r3, #8]
|
|
8009a78: 687b ldr r3, [r7, #4]
|
|
8009a7a: 685a ldr r2, [r3, #4]
|
|
8009a7c: 687b ldr r3, [r7, #4]
|
|
8009a7e: 691b ldr r3, [r3, #16]
|
|
8009a80: 431a orrs r2, r3
|
|
8009a82: 687b ldr r3, [r7, #4]
|
|
8009a84: 699b ldr r3, [r3, #24]
|
|
8009a86: 431a orrs r2, r3
|
|
8009a88: 687b ldr r3, [r7, #4]
|
|
8009a8a: 681b ldr r3, [r3, #0]
|
|
8009a8c: 430a orrs r2, r1
|
|
8009a8e: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the RTC PRER */
|
|
hrtc->Instance->PRER = (hrtc->Init.SynchPrediv);
|
|
8009a90: 687b ldr r3, [r7, #4]
|
|
8009a92: 681b ldr r3, [r3, #0]
|
|
8009a94: 687a ldr r2, [r7, #4]
|
|
8009a96: 68d2 ldr r2, [r2, #12]
|
|
8009a98: 611a str r2, [r3, #16]
|
|
hrtc->Instance->PRER |= (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
|
|
8009a9a: 687b ldr r3, [r7, #4]
|
|
8009a9c: 681b ldr r3, [r3, #0]
|
|
8009a9e: 6919 ldr r1, [r3, #16]
|
|
8009aa0: 687b ldr r3, [r7, #4]
|
|
8009aa2: 689b ldr r3, [r3, #8]
|
|
8009aa4: 041a lsls r2, r3, #16
|
|
8009aa6: 687b ldr r3, [r7, #4]
|
|
8009aa8: 681b ldr r3, [r3, #0]
|
|
8009aaa: 430a orrs r2, r1
|
|
8009aac: 611a str r2, [r3, #16]
|
|
/* Configure the Binary mode */
|
|
MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU);
|
|
#endif
|
|
|
|
/* Exit Initialization mode */
|
|
status = RTC_ExitInitMode(hrtc);
|
|
8009aae: 6878 ldr r0, [r7, #4]
|
|
8009ab0: f000 f87f bl 8009bb2 <RTC_ExitInitMode>
|
|
8009ab4: 4603 mov r3, r0
|
|
8009ab6: 73fb strb r3, [r7, #15]
|
|
|
|
if (status == HAL_OK)
|
|
8009ab8: 7bfb ldrb r3, [r7, #15]
|
|
8009aba: 2b00 cmp r3, #0
|
|
8009abc: d11b bne.n 8009af6 <HAL_RTC_Init+0xec>
|
|
{
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
|
|
hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
|
|
#else
|
|
hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
|
|
8009abe: 687b ldr r3, [r7, #4]
|
|
8009ac0: 681b ldr r3, [r3, #0]
|
|
8009ac2: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
8009ac4: 687b ldr r3, [r7, #4]
|
|
8009ac6: 681b ldr r3, [r3, #0]
|
|
8009ac8: f022 0203 bic.w r2, r2, #3
|
|
8009acc: 64da str r2, [r3, #76] ; 0x4c
|
|
hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
|
|
8009ace: 687b ldr r3, [r7, #4]
|
|
8009ad0: 681b ldr r3, [r3, #0]
|
|
8009ad2: 6cd9 ldr r1, [r3, #76] ; 0x4c
|
|
8009ad4: 687b ldr r3, [r7, #4]
|
|
8009ad6: 69da ldr r2, [r3, #28]
|
|
8009ad8: 687b ldr r3, [r7, #4]
|
|
8009ada: 695b ldr r3, [r3, #20]
|
|
8009adc: 431a orrs r2, r3
|
|
8009ade: 687b ldr r3, [r7, #4]
|
|
8009ae0: 681b ldr r3, [r3, #0]
|
|
8009ae2: 430a orrs r2, r1
|
|
8009ae4: 64da str r2, [r3, #76] ; 0x4c
|
|
#endif
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
8009ae6: 687b ldr r3, [r7, #4]
|
|
8009ae8: 681b ldr r3, [r3, #0]
|
|
8009aea: 22ff movs r2, #255 ; 0xff
|
|
8009aec: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
8009aee: 687b ldr r3, [r7, #4]
|
|
8009af0: 2201 movs r2, #1
|
|
8009af2: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8009af6: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009af8: 4618 mov r0, r3
|
|
8009afa: 3710 adds r7, #16
|
|
8009afc: 46bd mov sp, r7
|
|
8009afe: bd80 pop {r7, pc}
|
|
|
|
08009b00 <HAL_RTC_WaitForSynchro>:
|
|
* correctly copied into the RTC_TR and RTC_DR shadow registers.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8009b00: b580 push {r7, lr}
|
|
8009b02: b084 sub sp, #16
|
|
8009b04: af00 add r7, sp, #0
|
|
8009b06: 6078 str r0, [r7, #4]
|
|
|
|
/* Clear RSF flag */
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
|
|
#else
|
|
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
|
|
8009b08: 687b ldr r3, [r7, #4]
|
|
8009b0a: 681b ldr r3, [r3, #0]
|
|
8009b0c: 68da ldr r2, [r3, #12]
|
|
8009b0e: 687b ldr r3, [r7, #4]
|
|
8009b10: 681b ldr r3, [r3, #0]
|
|
8009b12: f022 02a0 bic.w r2, r2, #160 ; 0xa0
|
|
8009b16: 60da str r2, [r3, #12]
|
|
#endif
|
|
|
|
tickstart = HAL_GetTick();
|
|
8009b18: f7fa ff77 bl 8004a0a <HAL_GetTick>
|
|
8009b1c: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait the registers to be synchronised */
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U)
|
|
#else
|
|
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
|
|
8009b1e: e009 b.n 8009b34 <HAL_RTC_WaitForSynchro+0x34>
|
|
#endif
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
8009b20: f7fa ff73 bl 8004a0a <HAL_GetTick>
|
|
8009b24: 4602 mov r2, r0
|
|
8009b26: 68fb ldr r3, [r7, #12]
|
|
8009b28: 1ad3 subs r3, r2, r3
|
|
8009b2a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
8009b2e: d901 bls.n 8009b34 <HAL_RTC_WaitForSynchro+0x34>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009b30: 2303 movs r3, #3
|
|
8009b32: e007 b.n 8009b44 <HAL_RTC_WaitForSynchro+0x44>
|
|
while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
|
|
8009b34: 687b ldr r3, [r7, #4]
|
|
8009b36: 681b ldr r3, [r3, #0]
|
|
8009b38: 68db ldr r3, [r3, #12]
|
|
8009b3a: f003 0320 and.w r3, r3, #32
|
|
8009b3e: 2b00 cmp r3, #0
|
|
8009b40: d0ee beq.n 8009b20 <HAL_RTC_WaitForSynchro+0x20>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8009b42: 2300 movs r3, #0
|
|
}
|
|
8009b44: 4618 mov r0, r3
|
|
8009b46: 3710 adds r7, #16
|
|
8009b48: 46bd mov sp, r7
|
|
8009b4a: bd80 pop {r7, pc}
|
|
|
|
08009b4c <RTC_EnterInitMode>:
|
|
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8009b4c: b580 push {r7, lr}
|
|
8009b4e: b084 sub sp, #16
|
|
8009b50: af00 add r7, sp, #0
|
|
8009b52: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8009b54: 2300 movs r3, #0
|
|
8009b56: 73fb strb r3, [r7, #15]
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
#else /* #if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
|
|
if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
|
|
8009b58: 687b ldr r3, [r7, #4]
|
|
8009b5a: 681b ldr r3, [r3, #0]
|
|
8009b5c: 68db ldr r3, [r3, #12]
|
|
8009b5e: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8009b62: 2b00 cmp r3, #0
|
|
8009b64: d120 bne.n 8009ba8 <RTC_EnterInitMode+0x5c>
|
|
{
|
|
/* Set the Initialization mode */
|
|
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
|
|
8009b66: 687b ldr r3, [r7, #4]
|
|
8009b68: 681b ldr r3, [r3, #0]
|
|
8009b6a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
8009b6e: 60da str r2, [r3, #12]
|
|
|
|
tickstart = HAL_GetTick();
|
|
8009b70: f7fa ff4b bl 8004a0a <HAL_GetTick>
|
|
8009b74: 60b8 str r0, [r7, #8]
|
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
|
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
|
|
8009b76: e00d b.n 8009b94 <RTC_EnterInitMode+0x48>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
8009b78: f7fa ff47 bl 8004a0a <HAL_GetTick>
|
|
8009b7c: 4602 mov r2, r0
|
|
8009b7e: 68bb ldr r3, [r7, #8]
|
|
8009b80: 1ad3 subs r3, r2, r3
|
|
8009b82: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
8009b86: d905 bls.n 8009b94 <RTC_EnterInitMode+0x48>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8009b88: 2303 movs r3, #3
|
|
8009b8a: 73fb strb r3, [r7, #15]
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
8009b8c: 687b ldr r3, [r7, #4]
|
|
8009b8e: 2203 movs r2, #3
|
|
8009b90: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
|
|
8009b94: 687b ldr r3, [r7, #4]
|
|
8009b96: 681b ldr r3, [r3, #0]
|
|
8009b98: 68db ldr r3, [r3, #12]
|
|
8009b9a: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8009b9e: 2b00 cmp r3, #0
|
|
8009ba0: d102 bne.n 8009ba8 <RTC_EnterInitMode+0x5c>
|
|
8009ba2: 7bfb ldrb r3, [r7, #15]
|
|
8009ba4: 2b03 cmp r3, #3
|
|
8009ba6: d1e7 bne.n 8009b78 <RTC_EnterInitMode+0x2c>
|
|
}
|
|
}
|
|
}
|
|
#endif /* #if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
|
|
|
|
return status;
|
|
8009ba8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009baa: 4618 mov r0, r3
|
|
8009bac: 3710 adds r7, #16
|
|
8009bae: 46bd mov sp, r7
|
|
8009bb0: bd80 pop {r7, pc}
|
|
|
|
08009bb2 <RTC_ExitInitMode>:
|
|
* @brief Exit the RTC Initialization mode.
|
|
* @param hrtc RTC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8009bb2: b580 push {r7, lr}
|
|
8009bb4: b084 sub sp, #16
|
|
8009bb6: af00 add r7, sp, #0
|
|
8009bb8: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8009bba: 2300 movs r3, #0
|
|
8009bbc: 73fb strb r3, [r7, #15]
|
|
/* Exit Initialization mode */
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx)
|
|
CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
|
|
#else
|
|
/* Exit Initialization mode */
|
|
CLEAR_BIT(RTC->ISR, RTC_ISR_INIT);
|
|
8009bbe: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
8009bc2: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8009bc6: 68da ldr r2, [r3, #12]
|
|
8009bc8: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
8009bcc: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8009bd0: f022 0280 bic.w r2, r2, #128 ; 0x80
|
|
8009bd4: 60da str r2, [r3, #12]
|
|
#endif
|
|
|
|
/* If CR_BYPSHAD bit = 0, wait for synchro */
|
|
if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
|
|
8009bd6: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
8009bda: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8009bde: 689b ldr r3, [r3, #8]
|
|
8009be0: f003 0320 and.w r3, r3, #32
|
|
8009be4: 2b00 cmp r3, #0
|
|
8009be6: d10c bne.n 8009c02 <RTC_ExitInitMode+0x50>
|
|
{
|
|
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
8009be8: 6878 ldr r0, [r7, #4]
|
|
8009bea: f7ff ff89 bl 8009b00 <HAL_RTC_WaitForSynchro>
|
|
8009bee: 4603 mov r3, r0
|
|
8009bf0: 2b00 cmp r3, #0
|
|
8009bf2: d02a beq.n 8009c4a <RTC_ExitInitMode+0x98>
|
|
{
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
8009bf4: 687b ldr r3, [r7, #4]
|
|
8009bf6: 2203 movs r2, #3
|
|
8009bf8: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
status = HAL_TIMEOUT;
|
|
8009bfc: 2303 movs r3, #3
|
|
8009bfe: 73fb strb r3, [r7, #15]
|
|
8009c00: e023 b.n 8009c4a <RTC_ExitInitMode+0x98>
|
|
}
|
|
}
|
|
else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry */
|
|
{
|
|
/* Clear BYPSHAD bit */
|
|
CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
|
8009c02: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
8009c06: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8009c0a: 689a ldr r2, [r3, #8]
|
|
8009c0c: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
8009c10: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8009c14: f022 0220 bic.w r2, r2, #32
|
|
8009c18: 609a str r2, [r3, #8]
|
|
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
8009c1a: 6878 ldr r0, [r7, #4]
|
|
8009c1c: f7ff ff70 bl 8009b00 <HAL_RTC_WaitForSynchro>
|
|
8009c20: 4603 mov r3, r0
|
|
8009c22: 2b00 cmp r3, #0
|
|
8009c24: d005 beq.n 8009c32 <RTC_ExitInitMode+0x80>
|
|
{
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
8009c26: 687b ldr r3, [r7, #4]
|
|
8009c28: 2203 movs r2, #3
|
|
8009c2a: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
status = HAL_TIMEOUT;
|
|
8009c2e: 2303 movs r3, #3
|
|
8009c30: 73fb strb r3, [r7, #15]
|
|
}
|
|
/* Restore BYPSHAD bit */
|
|
SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
|
|
8009c32: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
8009c36: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8009c3a: 689a ldr r2, [r3, #8]
|
|
8009c3c: f44f 5320 mov.w r3, #10240 ; 0x2800
|
|
8009c40: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
8009c44: f042 0220 orr.w r2, r2, #32
|
|
8009c48: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
return status;
|
|
8009c4a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009c4c: 4618 mov r0, r3
|
|
8009c4e: 3710 adds r7, #16
|
|
8009c50: 46bd mov sp, r7
|
|
8009c52: bd80 pop {r7, pc}
|
|
|
|
08009c54 <HAL_RTCEx_SetWakeUpTimer_IT>:
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr)
|
|
#else
|
|
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
|
|
#endif
|
|
{
|
|
8009c54: b580 push {r7, lr}
|
|
8009c56: b086 sub sp, #24
|
|
8009c58: af00 add r7, sp, #0
|
|
8009c5a: 60f8 str r0, [r7, #12]
|
|
8009c5c: 60b9 str r1, [r7, #8]
|
|
8009c5e: 607a str r2, [r7, #4]
|
|
/* (0x0000<=WUTOCLR<=WUT) */
|
|
assert_param(WakeUpAutoClr <= WakeUpCounter);
|
|
#endif
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
8009c60: 68fb ldr r3, [r7, #12]
|
|
8009c62: f893 3020 ldrb.w r3, [r3, #32]
|
|
8009c66: 2b01 cmp r3, #1
|
|
8009c68: d101 bne.n 8009c6e <HAL_RTCEx_SetWakeUpTimer_IT+0x1a>
|
|
8009c6a: 2302 movs r3, #2
|
|
8009c6c: e08b b.n 8009d86 <HAL_RTCEx_SetWakeUpTimer_IT+0x132>
|
|
8009c6e: 68fb ldr r3, [r7, #12]
|
|
8009c70: 2201 movs r2, #1
|
|
8009c72: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
8009c76: 68fb ldr r3, [r7, #12]
|
|
8009c78: 2202 movs r2, #2
|
|
8009c7a: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
8009c7e: 68fb ldr r3, [r7, #12]
|
|
8009c80: 681b ldr r3, [r3, #0]
|
|
8009c82: 22ca movs r2, #202 ; 0xca
|
|
8009c84: 625a str r2, [r3, #36] ; 0x24
|
|
8009c86: 68fb ldr r3, [r7, #12]
|
|
8009c88: 681b ldr r3, [r3, #0]
|
|
8009c8a: 2253 movs r2, #83 ; 0x53
|
|
8009c8c: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Clear WUTE in RTC_CR to disable the wakeup timer */
|
|
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE);
|
|
8009c8e: 68fb ldr r3, [r7, #12]
|
|
8009c90: 681b ldr r3, [r3, #0]
|
|
8009c92: 689a ldr r2, [r3, #8]
|
|
8009c94: 68fb ldr r3, [r7, #12]
|
|
8009c96: 681b ldr r3, [r3, #0]
|
|
8009c98: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
8009c9c: 609a str r2, [r3, #8]
|
|
|
|
/* Clear flag Wake-Up */
|
|
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
|
|
8009c9e: 68fb ldr r3, [r7, #12]
|
|
8009ca0: 681b ldr r3, [r3, #0]
|
|
8009ca2: 68db ldr r3, [r3, #12]
|
|
8009ca4: b2da uxtb r2, r3
|
|
8009ca6: 68fb ldr r3, [r7, #12]
|
|
8009ca8: 681b ldr r3, [r3, #0]
|
|
8009caa: f462 6290 orn r2, r2, #1152 ; 0x480
|
|
8009cae: 60da str r2, [r3, #12]
|
|
counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
|
|
calendar initialization mode. */
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U)
|
|
#else
|
|
if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U)
|
|
8009cb0: 68fb ldr r3, [r7, #12]
|
|
8009cb2: 681b ldr r3, [r3, #0]
|
|
8009cb4: 68db ldr r3, [r3, #12]
|
|
8009cb6: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8009cba: 2b00 cmp r3, #0
|
|
8009cbc: d120 bne.n 8009d00 <HAL_RTCEx_SetWakeUpTimer_IT+0xac>
|
|
#endif
|
|
{
|
|
tickstart = HAL_GetTick();
|
|
8009cbe: f7fa fea4 bl 8004a0a <HAL_GetTick>
|
|
8009cc2: 6178 str r0, [r7, #20]
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U)
|
|
#else
|
|
while (READ_BIT(hrtc->Instance->ISR, RTC_ISR_WUTWF) == 0U)
|
|
8009cc4: e015 b.n 8009cf2 <HAL_RTCEx_SetWakeUpTimer_IT+0x9e>
|
|
#endif
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
|
|
8009cc6: f7fa fea0 bl 8004a0a <HAL_GetTick>
|
|
8009cca: 4602 mov r2, r0
|
|
8009ccc: 697b ldr r3, [r7, #20]
|
|
8009cce: 1ad3 subs r3, r2, r3
|
|
8009cd0: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
8009cd4: d90d bls.n 8009cf2 <HAL_RTCEx_SetWakeUpTimer_IT+0x9e>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
8009cd6: 68fb ldr r3, [r7, #12]
|
|
8009cd8: 681b ldr r3, [r3, #0]
|
|
8009cda: 22ff movs r2, #255 ; 0xff
|
|
8009cdc: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
8009cde: 68fb ldr r3, [r7, #12]
|
|
8009ce0: 2203 movs r2, #3
|
|
8009ce2: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
8009ce6: 68fb ldr r3, [r7, #12]
|
|
8009ce8: 2200 movs r2, #0
|
|
8009cea: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_TIMEOUT;
|
|
8009cee: 2303 movs r3, #3
|
|
8009cf0: e049 b.n 8009d86 <HAL_RTCEx_SetWakeUpTimer_IT+0x132>
|
|
while (READ_BIT(hrtc->Instance->ISR, RTC_ISR_WUTWF) == 0U)
|
|
8009cf2: 68fb ldr r3, [r7, #12]
|
|
8009cf4: 681b ldr r3, [r3, #0]
|
|
8009cf6: 68db ldr r3, [r3, #12]
|
|
8009cf8: f003 0304 and.w r3, r3, #4
|
|
8009cfc: 2b00 cmp r3, #0
|
|
8009cfe: d0e2 beq.n 8009cc6 <HAL_RTCEx_SetWakeUpTimer_IT+0x72>
|
|
#if defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx)
|
|
/* Configure the Wakeup Timer counter and auto clear value */
|
|
hrtc->Instance->WUTR = (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos));
|
|
#else
|
|
/* Configure the Wakeup Timer counter */
|
|
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
|
|
8009d00: 68fb ldr r3, [r7, #12]
|
|
8009d02: 681b ldr r3, [r3, #0]
|
|
8009d04: 68ba ldr r2, [r7, #8]
|
|
8009d06: 615a str r2, [r3, #20]
|
|
#endif
|
|
|
|
/* Configure the clock source */
|
|
MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
|
|
8009d08: 68fb ldr r3, [r7, #12]
|
|
8009d0a: 681b ldr r3, [r3, #0]
|
|
8009d0c: 689b ldr r3, [r3, #8]
|
|
8009d0e: f023 0107 bic.w r1, r3, #7
|
|
8009d12: 68fb ldr r3, [r7, #12]
|
|
8009d14: 681b ldr r3, [r3, #0]
|
|
8009d16: 687a ldr r2, [r7, #4]
|
|
8009d18: 430a orrs r2, r1
|
|
8009d1a: 609a str r2, [r3, #8]
|
|
{
|
|
/* RTC WakeUpTimer EXTI Configuration: Interrupt configuration */
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
|
|
}
|
|
#else /* defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
|
|
8009d1c: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8009d20: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8009d24: 681a ldr r2, [r3, #0]
|
|
8009d26: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8009d2a: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8009d2e: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
8009d32: 601a str r2, [r3, #0]
|
|
#endif /* defined(STM32L412xx) || defined(STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) */
|
|
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
|
|
8009d34: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8009d38: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8009d3c: 689a ldr r2, [r3, #8]
|
|
8009d3e: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8009d42: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8009d46: f442 1280 orr.w r2, r2, #1048576 ; 0x100000
|
|
8009d4a: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the Interrupt in the RTC_CR register */
|
|
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
|
|
8009d4c: 68fb ldr r3, [r7, #12]
|
|
8009d4e: 681b ldr r3, [r3, #0]
|
|
8009d50: 689a ldr r2, [r3, #8]
|
|
8009d52: 68fb ldr r3, [r7, #12]
|
|
8009d54: 681b ldr r3, [r3, #0]
|
|
8009d56: f442 4280 orr.w r2, r2, #16384 ; 0x4000
|
|
8009d5a: 609a str r2, [r3, #8]
|
|
|
|
/* Enable the Wakeup Timer */
|
|
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
|
|
8009d5c: 68fb ldr r3, [r7, #12]
|
|
8009d5e: 681b ldr r3, [r3, #0]
|
|
8009d60: 689a ldr r2, [r3, #8]
|
|
8009d62: 68fb ldr r3, [r7, #12]
|
|
8009d64: 681b ldr r3, [r3, #0]
|
|
8009d66: f442 6280 orr.w r2, r2, #1024 ; 0x400
|
|
8009d6a: 609a str r2, [r3, #8]
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
8009d6c: 68fb ldr r3, [r7, #12]
|
|
8009d6e: 681b ldr r3, [r3, #0]
|
|
8009d70: 22ff movs r2, #255 ; 0xff
|
|
8009d72: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
8009d74: 68fb ldr r3, [r7, #12]
|
|
8009d76: 2201 movs r2, #1
|
|
8009d78: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
8009d7c: 68fb ldr r3, [r7, #12]
|
|
8009d7e: 2200 movs r2, #0
|
|
8009d80: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_OK;
|
|
8009d84: 2300 movs r3, #0
|
|
}
|
|
8009d86: 4618 mov r0, r3
|
|
8009d88: 3718 adds r7, #24
|
|
8009d8a: 46bd mov sp, r7
|
|
8009d8c: bd80 pop {r7, pc}
|
|
|
|
08009d8e <HAL_RTCEx_WakeUpTimerIRQHandler>:
|
|
* @brief Handle Wake Up Timer interrupt request.
|
|
* @param hrtc RTC handle
|
|
* @retval None
|
|
*/
|
|
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
8009d8e: b580 push {r7, lr}
|
|
8009d90: b082 sub sp, #8
|
|
8009d92: af00 add r7, sp, #0
|
|
8009d94: 6078 str r0, [r7, #4]
|
|
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
|
|
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
|
|
8009d96: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8009d9a: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
8009d9e: f44f 1280 mov.w r2, #1048576 ; 0x100000
|
|
8009da2: 615a str r2, [r3, #20]
|
|
{
|
|
/* Immediately clear flags */
|
|
hrtc->Instance->SCR = RTC_SCR_CWUTF;
|
|
#else
|
|
/* Get the pending status of the WAKEUPTIMER Interrupt */
|
|
if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
|
|
8009da4: 687b ldr r3, [r7, #4]
|
|
8009da6: 681b ldr r3, [r3, #0]
|
|
8009da8: 68db ldr r3, [r3, #12]
|
|
8009daa: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8009dae: 2b00 cmp r3, #0
|
|
8009db0: d00b beq.n 8009dca <HAL_RTCEx_WakeUpTimerIRQHandler+0x3c>
|
|
{
|
|
/* Clear the WAKEUPTIMER interrupt pending bit */
|
|
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
|
|
8009db2: 687b ldr r3, [r7, #4]
|
|
8009db4: 681b ldr r3, [r3, #0]
|
|
8009db6: 68db ldr r3, [r3, #12]
|
|
8009db8: b2da uxtb r2, r3
|
|
8009dba: 687b ldr r3, [r7, #4]
|
|
8009dbc: 681b ldr r3, [r3, #0]
|
|
8009dbe: f462 6290 orn r2, r2, #1152 ; 0x480
|
|
8009dc2: 60da str r2, [r3, #12]
|
|
/* WAKEUPTIMER callback */
|
|
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
|
/* Call WakeUpTimerEvent registered Callback */
|
|
hrtc->WakeUpTimerEventCallback(hrtc);
|
|
#else
|
|
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
|
|
8009dc4: 6878 ldr r0, [r7, #4]
|
|
8009dc6: f7f8 fbe3 bl 8002590 <HAL_RTCEx_WakeUpTimerEventCallback>
|
|
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Change RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
8009dca: 687b ldr r3, [r7, #4]
|
|
8009dcc: 2201 movs r2, #1
|
|
8009dce: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
}
|
|
8009dd2: bf00 nop
|
|
8009dd4: 3708 adds r7, #8
|
|
8009dd6: 46bd mov sp, r7
|
|
8009dd8: bd80 pop {r7, pc}
|
|
|
|
08009dda <HAL_RTCEx_SetCalibrationOutPut>:
|
|
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
|
|
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
|
|
{
|
|
8009dda: b480 push {r7}
|
|
8009ddc: b083 sub sp, #12
|
|
8009dde: af00 add r7, sp, #0
|
|
8009de0: 6078 str r0, [r7, #4]
|
|
8009de2: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
8009de4: 687b ldr r3, [r7, #4]
|
|
8009de6: f893 3020 ldrb.w r3, [r3, #32]
|
|
8009dea: 2b01 cmp r3, #1
|
|
8009dec: d101 bne.n 8009df2 <HAL_RTCEx_SetCalibrationOutPut+0x18>
|
|
8009dee: 2302 movs r3, #2
|
|
8009df0: e034 b.n 8009e5c <HAL_RTCEx_SetCalibrationOutPut+0x82>
|
|
8009df2: 687b ldr r3, [r7, #4]
|
|
8009df4: 2201 movs r2, #1
|
|
8009df6: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
8009dfa: 687b ldr r3, [r7, #4]
|
|
8009dfc: 2202 movs r2, #2
|
|
8009dfe: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
8009e02: 687b ldr r3, [r7, #4]
|
|
8009e04: 681b ldr r3, [r3, #0]
|
|
8009e06: 22ca movs r2, #202 ; 0xca
|
|
8009e08: 625a str r2, [r3, #36] ; 0x24
|
|
8009e0a: 687b ldr r3, [r7, #4]
|
|
8009e0c: 681b ldr r3, [r3, #0]
|
|
8009e0e: 2253 movs r2, #83 ; 0x53
|
|
8009e10: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Clear flags before config */
|
|
hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
|
|
8009e12: 687b ldr r3, [r7, #4]
|
|
8009e14: 681b ldr r3, [r3, #0]
|
|
8009e16: 689a ldr r2, [r3, #8]
|
|
8009e18: 687b ldr r3, [r7, #4]
|
|
8009e1a: 681b ldr r3, [r3, #0]
|
|
8009e1c: f422 2200 bic.w r2, r2, #524288 ; 0x80000
|
|
8009e20: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the RTC_CR register */
|
|
hrtc->Instance->CR |= (uint32_t)CalibOutput;
|
|
8009e22: 687b ldr r3, [r7, #4]
|
|
8009e24: 681b ldr r3, [r3, #0]
|
|
8009e26: 6899 ldr r1, [r3, #8]
|
|
8009e28: 687b ldr r3, [r7, #4]
|
|
8009e2a: 681b ldr r3, [r3, #0]
|
|
8009e2c: 683a ldr r2, [r7, #0]
|
|
8009e2e: 430a orrs r2, r1
|
|
8009e30: 609a str r2, [r3, #8]
|
|
|
|
__HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
|
|
8009e32: 687b ldr r3, [r7, #4]
|
|
8009e34: 681b ldr r3, [r3, #0]
|
|
8009e36: 689a ldr r2, [r3, #8]
|
|
8009e38: 687b ldr r3, [r7, #4]
|
|
8009e3a: 681b ldr r3, [r3, #0]
|
|
8009e3c: f442 0200 orr.w r2, r2, #8388608 ; 0x800000
|
|
8009e40: 609a str r2, [r3, #8]
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
8009e42: 687b ldr r3, [r7, #4]
|
|
8009e44: 681b ldr r3, [r3, #0]
|
|
8009e46: 22ff movs r2, #255 ; 0xff
|
|
8009e48: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Change RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
8009e4a: 687b ldr r3, [r7, #4]
|
|
8009e4c: 2201 movs r2, #1
|
|
8009e4e: f883 2021 strb.w r2, [r3, #33] ; 0x21
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
8009e52: 687b ldr r3, [r7, #4]
|
|
8009e54: 2200 movs r2, #0
|
|
8009e56: f883 2020 strb.w r2, [r3, #32]
|
|
|
|
return HAL_OK;
|
|
8009e5a: 2300 movs r3, #0
|
|
}
|
|
8009e5c: 4618 mov r0, r3
|
|
8009e5e: 370c adds r7, #12
|
|
8009e60: 46bd mov sp, r7
|
|
8009e62: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009e66: 4770 bx lr
|
|
|
|
08009e68 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8009e68: b580 push {r7, lr}
|
|
8009e6a: b082 sub sp, #8
|
|
8009e6c: af00 add r7, sp, #0
|
|
8009e6e: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8009e70: 687b ldr r3, [r7, #4]
|
|
8009e72: 2b00 cmp r3, #0
|
|
8009e74: d101 bne.n 8009e7a <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8009e76: 2301 movs r3, #1
|
|
8009e78: e040 b.n 8009efc <HAL_UART_Init+0x94>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8009e7a: 687b ldr r3, [r7, #4]
|
|
8009e7c: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8009e7e: 2b00 cmp r3, #0
|
|
8009e80: d106 bne.n 8009e90 <HAL_UART_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8009e82: 687b ldr r3, [r7, #4]
|
|
8009e84: 2200 movs r2, #0
|
|
8009e86: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8009e8a: 6878 ldr r0, [r7, #4]
|
|
8009e8c: f7f8 fdb9 bl 8002a02 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8009e90: 687b ldr r3, [r7, #4]
|
|
8009e92: 2224 movs r2, #36 ; 0x24
|
|
8009e94: 679a str r2, [r3, #120] ; 0x78
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8009e96: 687b ldr r3, [r7, #4]
|
|
8009e98: 681b ldr r3, [r3, #0]
|
|
8009e9a: 681a ldr r2, [r3, #0]
|
|
8009e9c: 687b ldr r3, [r7, #4]
|
|
8009e9e: 681b ldr r3, [r3, #0]
|
|
8009ea0: f022 0201 bic.w r2, r2, #1
|
|
8009ea4: 601a str r2, [r3, #0]
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8009ea6: 6878 ldr r0, [r7, #4]
|
|
8009ea8: f000 fbb4 bl 800a614 <UART_SetConfig>
|
|
8009eac: 4603 mov r3, r0
|
|
8009eae: 2b01 cmp r3, #1
|
|
8009eb0: d101 bne.n 8009eb6 <HAL_UART_Init+0x4e>
|
|
{
|
|
return HAL_ERROR;
|
|
8009eb2: 2301 movs r3, #1
|
|
8009eb4: e022 b.n 8009efc <HAL_UART_Init+0x94>
|
|
}
|
|
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8009eb6: 687b ldr r3, [r7, #4]
|
|
8009eb8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8009eba: 2b00 cmp r3, #0
|
|
8009ebc: d002 beq.n 8009ec4 <HAL_UART_Init+0x5c>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
8009ebe: 6878 ldr r0, [r7, #4]
|
|
8009ec0: f000 fe52 bl 800ab68 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8009ec4: 687b ldr r3, [r7, #4]
|
|
8009ec6: 681b ldr r3, [r3, #0]
|
|
8009ec8: 685a ldr r2, [r3, #4]
|
|
8009eca: 687b ldr r3, [r7, #4]
|
|
8009ecc: 681b ldr r3, [r3, #0]
|
|
8009ece: f422 4290 bic.w r2, r2, #18432 ; 0x4800
|
|
8009ed2: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8009ed4: 687b ldr r3, [r7, #4]
|
|
8009ed6: 681b ldr r3, [r3, #0]
|
|
8009ed8: 689a ldr r2, [r3, #8]
|
|
8009eda: 687b ldr r3, [r7, #4]
|
|
8009edc: 681b ldr r3, [r3, #0]
|
|
8009ede: f022 022a bic.w r2, r2, #42 ; 0x2a
|
|
8009ee2: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
8009ee4: 687b ldr r3, [r7, #4]
|
|
8009ee6: 681b ldr r3, [r3, #0]
|
|
8009ee8: 681a ldr r2, [r3, #0]
|
|
8009eea: 687b ldr r3, [r7, #4]
|
|
8009eec: 681b ldr r3, [r3, #0]
|
|
8009eee: f042 0201 orr.w r2, r2, #1
|
|
8009ef2: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
8009ef4: 6878 ldr r0, [r7, #4]
|
|
8009ef6: f000 fed9 bl 800acac <UART_CheckIdleState>
|
|
8009efa: 4603 mov r3, r0
|
|
}
|
|
8009efc: 4618 mov r0, r3
|
|
8009efe: 3708 adds r7, #8
|
|
8009f00: 46bd mov sp, r7
|
|
8009f02: bd80 pop {r7, pc}
|
|
|
|
08009f04 <HAL_UART_Transmit>:
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8009f04: b580 push {r7, lr}
|
|
8009f06: b08a sub sp, #40 ; 0x28
|
|
8009f08: af02 add r7, sp, #8
|
|
8009f0a: 60f8 str r0, [r7, #12]
|
|
8009f0c: 60b9 str r1, [r7, #8]
|
|
8009f0e: 603b str r3, [r7, #0]
|
|
8009f10: 4613 mov r3, r2
|
|
8009f12: 80fb strh r3, [r7, #6]
|
|
uint8_t *pdata8bits;
|
|
uint16_t *pdata16bits;
|
|
uint32_t tickstart;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8009f14: 68fb ldr r3, [r7, #12]
|
|
8009f16: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8009f18: 2b20 cmp r3, #32
|
|
8009f1a: f040 8082 bne.w 800a022 <HAL_UART_Transmit+0x11e>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8009f1e: 68bb ldr r3, [r7, #8]
|
|
8009f20: 2b00 cmp r3, #0
|
|
8009f22: d002 beq.n 8009f2a <HAL_UART_Transmit+0x26>
|
|
8009f24: 88fb ldrh r3, [r7, #6]
|
|
8009f26: 2b00 cmp r3, #0
|
|
8009f28: d101 bne.n 8009f2e <HAL_UART_Transmit+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
8009f2a: 2301 movs r3, #1
|
|
8009f2c: e07a b.n 800a024 <HAL_UART_Transmit+0x120>
|
|
}
|
|
|
|
__HAL_LOCK(huart);
|
|
8009f2e: 68fb ldr r3, [r7, #12]
|
|
8009f30: f893 3074 ldrb.w r3, [r3, #116] ; 0x74
|
|
8009f34: 2b01 cmp r3, #1
|
|
8009f36: d101 bne.n 8009f3c <HAL_UART_Transmit+0x38>
|
|
8009f38: 2302 movs r3, #2
|
|
8009f3a: e073 b.n 800a024 <HAL_UART_Transmit+0x120>
|
|
8009f3c: 68fb ldr r3, [r7, #12]
|
|
8009f3e: 2201 movs r2, #1
|
|
8009f40: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8009f44: 68fb ldr r3, [r7, #12]
|
|
8009f46: 2200 movs r2, #0
|
|
8009f48: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8009f4c: 68fb ldr r3, [r7, #12]
|
|
8009f4e: 2221 movs r2, #33 ; 0x21
|
|
8009f50: 679a str r2, [r3, #120] ; 0x78
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8009f52: f7fa fd5a bl 8004a0a <HAL_GetTick>
|
|
8009f56: 6178 str r0, [r7, #20]
|
|
|
|
huart->TxXferSize = Size;
|
|
8009f58: 68fb ldr r3, [r7, #12]
|
|
8009f5a: 88fa ldrh r2, [r7, #6]
|
|
8009f5c: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
|
|
huart->TxXferCount = Size;
|
|
8009f60: 68fb ldr r3, [r7, #12]
|
|
8009f62: 88fa ldrh r2, [r7, #6]
|
|
8009f64: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8009f68: 68fb ldr r3, [r7, #12]
|
|
8009f6a: 689b ldr r3, [r3, #8]
|
|
8009f6c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
8009f70: d108 bne.n 8009f84 <HAL_UART_Transmit+0x80>
|
|
8009f72: 68fb ldr r3, [r7, #12]
|
|
8009f74: 691b ldr r3, [r3, #16]
|
|
8009f76: 2b00 cmp r3, #0
|
|
8009f78: d104 bne.n 8009f84 <HAL_UART_Transmit+0x80>
|
|
{
|
|
pdata8bits = NULL;
|
|
8009f7a: 2300 movs r3, #0
|
|
8009f7c: 61fb str r3, [r7, #28]
|
|
pdata16bits = (uint16_t *) pData;
|
|
8009f7e: 68bb ldr r3, [r7, #8]
|
|
8009f80: 61bb str r3, [r7, #24]
|
|
8009f82: e003 b.n 8009f8c <HAL_UART_Transmit+0x88>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
8009f84: 68bb ldr r3, [r7, #8]
|
|
8009f86: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
8009f88: 2300 movs r3, #0
|
|
8009f8a: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8009f8c: 68fb ldr r3, [r7, #12]
|
|
8009f8e: 2200 movs r2, #0
|
|
8009f90: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
8009f94: e02d b.n 8009ff2 <HAL_UART_Transmit+0xee>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
8009f96: 683b ldr r3, [r7, #0]
|
|
8009f98: 9300 str r3, [sp, #0]
|
|
8009f9a: 697b ldr r3, [r7, #20]
|
|
8009f9c: 2200 movs r2, #0
|
|
8009f9e: 2180 movs r1, #128 ; 0x80
|
|
8009fa0: 68f8 ldr r0, [r7, #12]
|
|
8009fa2: f000 fecc bl 800ad3e <UART_WaitOnFlagUntilTimeout>
|
|
8009fa6: 4603 mov r3, r0
|
|
8009fa8: 2b00 cmp r3, #0
|
|
8009faa: d001 beq.n 8009fb0 <HAL_UART_Transmit+0xac>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009fac: 2303 movs r3, #3
|
|
8009fae: e039 b.n 800a024 <HAL_UART_Transmit+0x120>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
8009fb0: 69fb ldr r3, [r7, #28]
|
|
8009fb2: 2b00 cmp r3, #0
|
|
8009fb4: d10b bne.n 8009fce <HAL_UART_Transmit+0xca>
|
|
{
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
8009fb6: 69bb ldr r3, [r7, #24]
|
|
8009fb8: 881a ldrh r2, [r3, #0]
|
|
8009fba: 68fb ldr r3, [r7, #12]
|
|
8009fbc: 681b ldr r3, [r3, #0]
|
|
8009fbe: f3c2 0208 ubfx r2, r2, #0, #9
|
|
8009fc2: b292 uxth r2, r2
|
|
8009fc4: 851a strh r2, [r3, #40] ; 0x28
|
|
pdata16bits++;
|
|
8009fc6: 69bb ldr r3, [r7, #24]
|
|
8009fc8: 3302 adds r3, #2
|
|
8009fca: 61bb str r3, [r7, #24]
|
|
8009fcc: e008 b.n 8009fe0 <HAL_UART_Transmit+0xdc>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
8009fce: 69fb ldr r3, [r7, #28]
|
|
8009fd0: 781a ldrb r2, [r3, #0]
|
|
8009fd2: 68fb ldr r3, [r7, #12]
|
|
8009fd4: 681b ldr r3, [r3, #0]
|
|
8009fd6: b292 uxth r2, r2
|
|
8009fd8: 851a strh r2, [r3, #40] ; 0x28
|
|
pdata8bits++;
|
|
8009fda: 69fb ldr r3, [r7, #28]
|
|
8009fdc: 3301 adds r3, #1
|
|
8009fde: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->TxXferCount--;
|
|
8009fe0: 68fb ldr r3, [r7, #12]
|
|
8009fe2: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
8009fe6: b29b uxth r3, r3
|
|
8009fe8: 3b01 subs r3, #1
|
|
8009fea: b29a uxth r2, r3
|
|
8009fec: 68fb ldr r3, [r7, #12]
|
|
8009fee: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
while (huart->TxXferCount > 0U)
|
|
8009ff2: 68fb ldr r3, [r7, #12]
|
|
8009ff4: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
|
|
8009ff8: b29b uxth r3, r3
|
|
8009ffa: 2b00 cmp r3, #0
|
|
8009ffc: d1cb bne.n 8009f96 <HAL_UART_Transmit+0x92>
|
|
}
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8009ffe: 683b ldr r3, [r7, #0]
|
|
800a000: 9300 str r3, [sp, #0]
|
|
800a002: 697b ldr r3, [r7, #20]
|
|
800a004: 2200 movs r2, #0
|
|
800a006: 2140 movs r1, #64 ; 0x40
|
|
800a008: 68f8 ldr r0, [r7, #12]
|
|
800a00a: f000 fe98 bl 800ad3e <UART_WaitOnFlagUntilTimeout>
|
|
800a00e: 4603 mov r3, r0
|
|
800a010: 2b00 cmp r3, #0
|
|
800a012: d001 beq.n 800a018 <HAL_UART_Transmit+0x114>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a014: 2303 movs r3, #3
|
|
800a016: e005 b.n 800a024 <HAL_UART_Transmit+0x120>
|
|
}
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800a018: 68fb ldr r3, [r7, #12]
|
|
800a01a: 2220 movs r2, #32
|
|
800a01c: 679a str r2, [r3, #120] ; 0x78
|
|
|
|
return HAL_OK;
|
|
800a01e: 2300 movs r3, #0
|
|
800a020: e000 b.n 800a024 <HAL_UART_Transmit+0x120>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800a022: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800a024: 4618 mov r0, r3
|
|
800a026: 3720 adds r7, #32
|
|
800a028: 46bd mov sp, r7
|
|
800a02a: bd80 pop {r7, pc}
|
|
|
|
0800a02c <HAL_UART_Receive>:
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800a02c: b580 push {r7, lr}
|
|
800a02e: b08a sub sp, #40 ; 0x28
|
|
800a030: af02 add r7, sp, #8
|
|
800a032: 60f8 str r0, [r7, #12]
|
|
800a034: 60b9 str r1, [r7, #8]
|
|
800a036: 603b str r3, [r7, #0]
|
|
800a038: 4613 mov r3, r2
|
|
800a03a: 80fb strh r3, [r7, #6]
|
|
uint16_t *pdata16bits;
|
|
uint16_t uhMask;
|
|
uint32_t tickstart;
|
|
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
800a03c: 68fb ldr r3, [r7, #12]
|
|
800a03e: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
800a040: 2b20 cmp r3, #32
|
|
800a042: f040 80bf bne.w 800a1c4 <HAL_UART_Receive+0x198>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
800a046: 68bb ldr r3, [r7, #8]
|
|
800a048: 2b00 cmp r3, #0
|
|
800a04a: d002 beq.n 800a052 <HAL_UART_Receive+0x26>
|
|
800a04c: 88fb ldrh r3, [r7, #6]
|
|
800a04e: 2b00 cmp r3, #0
|
|
800a050: d101 bne.n 800a056 <HAL_UART_Receive+0x2a>
|
|
{
|
|
return HAL_ERROR;
|
|
800a052: 2301 movs r3, #1
|
|
800a054: e0b7 b.n 800a1c6 <HAL_UART_Receive+0x19a>
|
|
}
|
|
|
|
__HAL_LOCK(huart);
|
|
800a056: 68fb ldr r3, [r7, #12]
|
|
800a058: f893 3074 ldrb.w r3, [r3, #116] ; 0x74
|
|
800a05c: 2b01 cmp r3, #1
|
|
800a05e: d101 bne.n 800a064 <HAL_UART_Receive+0x38>
|
|
800a060: 2302 movs r3, #2
|
|
800a062: e0b0 b.n 800a1c6 <HAL_UART_Receive+0x19a>
|
|
800a064: 68fb ldr r3, [r7, #12]
|
|
800a066: 2201 movs r2, #1
|
|
800a068: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800a06c: 68fb ldr r3, [r7, #12]
|
|
800a06e: 2200 movs r2, #0
|
|
800a070: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
800a074: 68fb ldr r3, [r7, #12]
|
|
800a076: 2222 movs r2, #34 ; 0x22
|
|
800a078: 67da str r2, [r3, #124] ; 0x7c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800a07a: 68fb ldr r3, [r7, #12]
|
|
800a07c: 2200 movs r2, #0
|
|
800a07e: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
800a080: f7fa fcc3 bl 8004a0a <HAL_GetTick>
|
|
800a084: 6178 str r0, [r7, #20]
|
|
|
|
huart->RxXferSize = Size;
|
|
800a086: 68fb ldr r3, [r7, #12]
|
|
800a088: 88fa ldrh r2, [r7, #6]
|
|
800a08a: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
|
|
huart->RxXferCount = Size;
|
|
800a08e: 68fb ldr r3, [r7, #12]
|
|
800a090: 88fa ldrh r2, [r7, #6]
|
|
800a092: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
|
|
/* Computation of UART mask to apply to RDR register */
|
|
UART_MASK_COMPUTATION(huart);
|
|
800a096: 68fb ldr r3, [r7, #12]
|
|
800a098: 689b ldr r3, [r3, #8]
|
|
800a09a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800a09e: d10e bne.n 800a0be <HAL_UART_Receive+0x92>
|
|
800a0a0: 68fb ldr r3, [r7, #12]
|
|
800a0a2: 691b ldr r3, [r3, #16]
|
|
800a0a4: 2b00 cmp r3, #0
|
|
800a0a6: d105 bne.n 800a0b4 <HAL_UART_Receive+0x88>
|
|
800a0a8: 68fb ldr r3, [r7, #12]
|
|
800a0aa: f240 12ff movw r2, #511 ; 0x1ff
|
|
800a0ae: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
800a0b2: e02d b.n 800a110 <HAL_UART_Receive+0xe4>
|
|
800a0b4: 68fb ldr r3, [r7, #12]
|
|
800a0b6: 22ff movs r2, #255 ; 0xff
|
|
800a0b8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
800a0bc: e028 b.n 800a110 <HAL_UART_Receive+0xe4>
|
|
800a0be: 68fb ldr r3, [r7, #12]
|
|
800a0c0: 689b ldr r3, [r3, #8]
|
|
800a0c2: 2b00 cmp r3, #0
|
|
800a0c4: d10d bne.n 800a0e2 <HAL_UART_Receive+0xb6>
|
|
800a0c6: 68fb ldr r3, [r7, #12]
|
|
800a0c8: 691b ldr r3, [r3, #16]
|
|
800a0ca: 2b00 cmp r3, #0
|
|
800a0cc: d104 bne.n 800a0d8 <HAL_UART_Receive+0xac>
|
|
800a0ce: 68fb ldr r3, [r7, #12]
|
|
800a0d0: 22ff movs r2, #255 ; 0xff
|
|
800a0d2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
800a0d6: e01b b.n 800a110 <HAL_UART_Receive+0xe4>
|
|
800a0d8: 68fb ldr r3, [r7, #12]
|
|
800a0da: 227f movs r2, #127 ; 0x7f
|
|
800a0dc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
800a0e0: e016 b.n 800a110 <HAL_UART_Receive+0xe4>
|
|
800a0e2: 68fb ldr r3, [r7, #12]
|
|
800a0e4: 689b ldr r3, [r3, #8]
|
|
800a0e6: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
|
|
800a0ea: d10d bne.n 800a108 <HAL_UART_Receive+0xdc>
|
|
800a0ec: 68fb ldr r3, [r7, #12]
|
|
800a0ee: 691b ldr r3, [r3, #16]
|
|
800a0f0: 2b00 cmp r3, #0
|
|
800a0f2: d104 bne.n 800a0fe <HAL_UART_Receive+0xd2>
|
|
800a0f4: 68fb ldr r3, [r7, #12]
|
|
800a0f6: 227f movs r2, #127 ; 0x7f
|
|
800a0f8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
800a0fc: e008 b.n 800a110 <HAL_UART_Receive+0xe4>
|
|
800a0fe: 68fb ldr r3, [r7, #12]
|
|
800a100: 223f movs r2, #63 ; 0x3f
|
|
800a102: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
800a106: e003 b.n 800a110 <HAL_UART_Receive+0xe4>
|
|
800a108: 68fb ldr r3, [r7, #12]
|
|
800a10a: 2200 movs r2, #0
|
|
800a10c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
|
|
uhMask = huart->Mask;
|
|
800a110: 68fb ldr r3, [r7, #12]
|
|
800a112: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
|
|
800a116: 827b strh r3, [r7, #18]
|
|
|
|
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
800a118: 68fb ldr r3, [r7, #12]
|
|
800a11a: 689b ldr r3, [r3, #8]
|
|
800a11c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800a120: d108 bne.n 800a134 <HAL_UART_Receive+0x108>
|
|
800a122: 68fb ldr r3, [r7, #12]
|
|
800a124: 691b ldr r3, [r3, #16]
|
|
800a126: 2b00 cmp r3, #0
|
|
800a128: d104 bne.n 800a134 <HAL_UART_Receive+0x108>
|
|
{
|
|
pdata8bits = NULL;
|
|
800a12a: 2300 movs r3, #0
|
|
800a12c: 61fb str r3, [r7, #28]
|
|
pdata16bits = (uint16_t *) pData;
|
|
800a12e: 68bb ldr r3, [r7, #8]
|
|
800a130: 61bb str r3, [r7, #24]
|
|
800a132: e003 b.n 800a13c <HAL_UART_Receive+0x110>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
800a134: 68bb ldr r3, [r7, #8]
|
|
800a136: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
800a138: 2300 movs r3, #0
|
|
800a13a: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800a13c: 68fb ldr r3, [r7, #12]
|
|
800a13e: 2200 movs r2, #0
|
|
800a140: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
/* as long as data have to be received */
|
|
while (huart->RxXferCount > 0U)
|
|
800a144: e033 b.n 800a1ae <HAL_UART_Receive+0x182>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
|
|
800a146: 683b ldr r3, [r7, #0]
|
|
800a148: 9300 str r3, [sp, #0]
|
|
800a14a: 697b ldr r3, [r7, #20]
|
|
800a14c: 2200 movs r2, #0
|
|
800a14e: 2120 movs r1, #32
|
|
800a150: 68f8 ldr r0, [r7, #12]
|
|
800a152: f000 fdf4 bl 800ad3e <UART_WaitOnFlagUntilTimeout>
|
|
800a156: 4603 mov r3, r0
|
|
800a158: 2b00 cmp r3, #0
|
|
800a15a: d001 beq.n 800a160 <HAL_UART_Receive+0x134>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800a15c: 2303 movs r3, #3
|
|
800a15e: e032 b.n 800a1c6 <HAL_UART_Receive+0x19a>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
800a160: 69fb ldr r3, [r7, #28]
|
|
800a162: 2b00 cmp r3, #0
|
|
800a164: d10c bne.n 800a180 <HAL_UART_Receive+0x154>
|
|
{
|
|
*pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
|
|
800a166: 68fb ldr r3, [r7, #12]
|
|
800a168: 681b ldr r3, [r3, #0]
|
|
800a16a: 8c9b ldrh r3, [r3, #36] ; 0x24
|
|
800a16c: b29a uxth r2, r3
|
|
800a16e: 8a7b ldrh r3, [r7, #18]
|
|
800a170: 4013 ands r3, r2
|
|
800a172: b29a uxth r2, r3
|
|
800a174: 69bb ldr r3, [r7, #24]
|
|
800a176: 801a strh r2, [r3, #0]
|
|
pdata16bits++;
|
|
800a178: 69bb ldr r3, [r7, #24]
|
|
800a17a: 3302 adds r3, #2
|
|
800a17c: 61bb str r3, [r7, #24]
|
|
800a17e: e00d b.n 800a19c <HAL_UART_Receive+0x170>
|
|
}
|
|
else
|
|
{
|
|
*pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
|
|
800a180: 68fb ldr r3, [r7, #12]
|
|
800a182: 681b ldr r3, [r3, #0]
|
|
800a184: 8c9b ldrh r3, [r3, #36] ; 0x24
|
|
800a186: b29b uxth r3, r3
|
|
800a188: b2da uxtb r2, r3
|
|
800a18a: 8a7b ldrh r3, [r7, #18]
|
|
800a18c: b2db uxtb r3, r3
|
|
800a18e: 4013 ands r3, r2
|
|
800a190: b2da uxtb r2, r3
|
|
800a192: 69fb ldr r3, [r7, #28]
|
|
800a194: 701a strb r2, [r3, #0]
|
|
pdata8bits++;
|
|
800a196: 69fb ldr r3, [r7, #28]
|
|
800a198: 3301 adds r3, #1
|
|
800a19a: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->RxXferCount--;
|
|
800a19c: 68fb ldr r3, [r7, #12]
|
|
800a19e: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
800a1a2: b29b uxth r3, r3
|
|
800a1a4: 3b01 subs r3, #1
|
|
800a1a6: b29a uxth r2, r3
|
|
800a1a8: 68fb ldr r3, [r7, #12]
|
|
800a1aa: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
while (huart->RxXferCount > 0U)
|
|
800a1ae: 68fb ldr r3, [r7, #12]
|
|
800a1b0: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
800a1b4: b29b uxth r3, r3
|
|
800a1b6: 2b00 cmp r3, #0
|
|
800a1b8: d1c5 bne.n 800a146 <HAL_UART_Receive+0x11a>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800a1ba: 68fb ldr r3, [r7, #12]
|
|
800a1bc: 2220 movs r2, #32
|
|
800a1be: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
return HAL_OK;
|
|
800a1c0: 2300 movs r3, #0
|
|
800a1c2: e000 b.n 800a1c6 <HAL_UART_Receive+0x19a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
800a1c4: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800a1c6: 4618 mov r0, r3
|
|
800a1c8: 3720 adds r7, #32
|
|
800a1ca: 46bd mov sp, r7
|
|
800a1cc: bd80 pop {r7, pc}
|
|
|
|
0800a1ce <HAL_UART_IRQHandler>:
|
|
* @brief Handle UART interrupt request.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
800a1ce: b580 push {r7, lr}
|
|
800a1d0: b088 sub sp, #32
|
|
800a1d2: af00 add r7, sp, #0
|
|
800a1d4: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
800a1d6: 687b ldr r3, [r7, #4]
|
|
800a1d8: 681b ldr r3, [r3, #0]
|
|
800a1da: 69db ldr r3, [r3, #28]
|
|
800a1dc: 61fb str r3, [r7, #28]
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
800a1de: 687b ldr r3, [r7, #4]
|
|
800a1e0: 681b ldr r3, [r3, #0]
|
|
800a1e2: 681b ldr r3, [r3, #0]
|
|
800a1e4: 61bb str r3, [r7, #24]
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
800a1e6: 687b ldr r3, [r7, #4]
|
|
800a1e8: 681b ldr r3, [r3, #0]
|
|
800a1ea: 689b ldr r3, [r3, #8]
|
|
800a1ec: 617b str r3, [r7, #20]
|
|
|
|
uint32_t errorflags;
|
|
uint32_t errorcode;
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
800a1ee: 69fa ldr r2, [r7, #28]
|
|
800a1f0: f640 030f movw r3, #2063 ; 0x80f
|
|
800a1f4: 4013 ands r3, r2
|
|
800a1f6: 613b str r3, [r7, #16]
|
|
if (errorflags == 0U)
|
|
800a1f8: 693b ldr r3, [r7, #16]
|
|
800a1fa: 2b00 cmp r3, #0
|
|
800a1fc: d113 bne.n 800a226 <HAL_UART_IRQHandler+0x58>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
800a1fe: 69fb ldr r3, [r7, #28]
|
|
800a200: f003 0320 and.w r3, r3, #32
|
|
800a204: 2b00 cmp r3, #0
|
|
800a206: d00e beq.n 800a226 <HAL_UART_IRQHandler+0x58>
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
800a208: 69bb ldr r3, [r7, #24]
|
|
800a20a: f003 0320 and.w r3, r3, #32
|
|
800a20e: 2b00 cmp r3, #0
|
|
800a210: d009 beq.n 800a226 <HAL_UART_IRQHandler+0x58>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
800a212: 687b ldr r3, [r7, #4]
|
|
800a214: 6e5b ldr r3, [r3, #100] ; 0x64
|
|
800a216: 2b00 cmp r3, #0
|
|
800a218: f000 81d0 beq.w 800a5bc <HAL_UART_IRQHandler+0x3ee>
|
|
{
|
|
huart->RxISR(huart);
|
|
800a21c: 687b ldr r3, [r7, #4]
|
|
800a21e: 6e5b ldr r3, [r3, #100] ; 0x64
|
|
800a220: 6878 ldr r0, [r7, #4]
|
|
800a222: 4798 blx r3
|
|
}
|
|
return;
|
|
800a224: e1ca b.n 800a5bc <HAL_UART_IRQHandler+0x3ee>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if ((errorflags != 0U)
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
#else
|
|
if ((errorflags != 0U)
|
|
800a226: 693b ldr r3, [r7, #16]
|
|
800a228: 2b00 cmp r3, #0
|
|
800a22a: f000 80e9 beq.w 800a400 <HAL_UART_IRQHandler+0x232>
|
|
&& (((cr3its & USART_CR3_EIE) != 0U)
|
|
800a22e: 697b ldr r3, [r7, #20]
|
|
800a230: f003 0301 and.w r3, r3, #1
|
|
800a234: 2b00 cmp r3, #0
|
|
800a236: d108 bne.n 800a24a <HAL_UART_IRQHandler+0x7c>
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
|
|
800a238: 69ba ldr r2, [r7, #24]
|
|
800a23a: f44f 7390 mov.w r3, #288 ; 0x120
|
|
800a23e: f2c0 4300 movt r3, #1024 ; 0x400
|
|
800a242: 4013 ands r3, r2
|
|
800a244: 2b00 cmp r3, #0
|
|
800a246: f000 80db beq.w 800a400 <HAL_UART_IRQHandler+0x232>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
800a24a: 69fb ldr r3, [r7, #28]
|
|
800a24c: f003 0301 and.w r3, r3, #1
|
|
800a250: 2b00 cmp r3, #0
|
|
800a252: d010 beq.n 800a276 <HAL_UART_IRQHandler+0xa8>
|
|
800a254: 69bb ldr r3, [r7, #24]
|
|
800a256: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
800a25a: 2b00 cmp r3, #0
|
|
800a25c: d00b beq.n 800a276 <HAL_UART_IRQHandler+0xa8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
800a25e: 687b ldr r3, [r7, #4]
|
|
800a260: 681b ldr r3, [r3, #0]
|
|
800a262: 2201 movs r2, #1
|
|
800a264: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
800a266: 687b ldr r3, [r7, #4]
|
|
800a268: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a26c: f043 0201 orr.w r2, r3, #1
|
|
800a270: 687b ldr r3, [r7, #4]
|
|
800a272: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800a276: 69fb ldr r3, [r7, #28]
|
|
800a278: f003 0302 and.w r3, r3, #2
|
|
800a27c: 2b00 cmp r3, #0
|
|
800a27e: d010 beq.n 800a2a2 <HAL_UART_IRQHandler+0xd4>
|
|
800a280: 697b ldr r3, [r7, #20]
|
|
800a282: f003 0301 and.w r3, r3, #1
|
|
800a286: 2b00 cmp r3, #0
|
|
800a288: d00b beq.n 800a2a2 <HAL_UART_IRQHandler+0xd4>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
800a28a: 687b ldr r3, [r7, #4]
|
|
800a28c: 681b ldr r3, [r3, #0]
|
|
800a28e: 2202 movs r2, #2
|
|
800a290: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
800a292: 687b ldr r3, [r7, #4]
|
|
800a294: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a298: f043 0204 orr.w r2, r3, #4
|
|
800a29c: 687b ldr r3, [r7, #4]
|
|
800a29e: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800a2a2: 69fb ldr r3, [r7, #28]
|
|
800a2a4: f003 0304 and.w r3, r3, #4
|
|
800a2a8: 2b00 cmp r3, #0
|
|
800a2aa: d010 beq.n 800a2ce <HAL_UART_IRQHandler+0x100>
|
|
800a2ac: 697b ldr r3, [r7, #20]
|
|
800a2ae: f003 0301 and.w r3, r3, #1
|
|
800a2b2: 2b00 cmp r3, #0
|
|
800a2b4: d00b beq.n 800a2ce <HAL_UART_IRQHandler+0x100>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
800a2b6: 687b ldr r3, [r7, #4]
|
|
800a2b8: 681b ldr r3, [r3, #0]
|
|
800a2ba: 2204 movs r2, #4
|
|
800a2bc: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
800a2be: 687b ldr r3, [r7, #4]
|
|
800a2c0: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a2c4: f043 0202 orr.w r2, r3, #2
|
|
800a2c8: 687b ldr r3, [r7, #4]
|
|
800a2ca: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
800a2ce: 69fb ldr r3, [r7, #28]
|
|
800a2d0: f003 0308 and.w r3, r3, #8
|
|
800a2d4: 2b00 cmp r3, #0
|
|
800a2d6: d015 beq.n 800a304 <HAL_UART_IRQHandler+0x136>
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
800a2d8: 69bb ldr r3, [r7, #24]
|
|
800a2da: f003 0320 and.w r3, r3, #32
|
|
800a2de: 2b00 cmp r3, #0
|
|
800a2e0: d104 bne.n 800a2ec <HAL_UART_IRQHandler+0x11e>
|
|
((cr3its & USART_CR3_EIE) != 0U)))
|
|
800a2e2: 697b ldr r3, [r7, #20]
|
|
800a2e4: f003 0301 and.w r3, r3, #1
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
800a2e8: 2b00 cmp r3, #0
|
|
800a2ea: d00b beq.n 800a304 <HAL_UART_IRQHandler+0x136>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
800a2ec: 687b ldr r3, [r7, #4]
|
|
800a2ee: 681b ldr r3, [r3, #0]
|
|
800a2f0: 2208 movs r2, #8
|
|
800a2f2: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
800a2f4: 687b ldr r3, [r7, #4]
|
|
800a2f6: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a2fa: f043 0208 orr.w r2, r3, #8
|
|
800a2fe: 687b ldr r3, [r7, #4]
|
|
800a300: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
}
|
|
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
800a304: 69fb ldr r3, [r7, #28]
|
|
800a306: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
800a30a: 2b00 cmp r3, #0
|
|
800a30c: d011 beq.n 800a332 <HAL_UART_IRQHandler+0x164>
|
|
800a30e: 69bb ldr r3, [r7, #24]
|
|
800a310: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
|
800a314: 2b00 cmp r3, #0
|
|
800a316: d00c beq.n 800a332 <HAL_UART_IRQHandler+0x164>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
800a318: 687b ldr r3, [r7, #4]
|
|
800a31a: 681b ldr r3, [r3, #0]
|
|
800a31c: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
800a320: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
800a322: 687b ldr r3, [r7, #4]
|
|
800a324: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a328: f043 0220 orr.w r2, r3, #32
|
|
800a32c: 687b ldr r3, [r7, #4]
|
|
800a32e: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
800a332: 687b ldr r3, [r7, #4]
|
|
800a334: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a338: 2b00 cmp r3, #0
|
|
800a33a: f000 8141 beq.w 800a5c0 <HAL_UART_IRQHandler+0x3f2>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
800a33e: 69fb ldr r3, [r7, #28]
|
|
800a340: f003 0320 and.w r3, r3, #32
|
|
800a344: 2b00 cmp r3, #0
|
|
800a346: d00c beq.n 800a362 <HAL_UART_IRQHandler+0x194>
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
800a348: 69bb ldr r3, [r7, #24]
|
|
800a34a: f003 0320 and.w r3, r3, #32
|
|
800a34e: 2b00 cmp r3, #0
|
|
800a350: d007 beq.n 800a362 <HAL_UART_IRQHandler+0x194>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
800a352: 687b ldr r3, [r7, #4]
|
|
800a354: 6e5b ldr r3, [r3, #100] ; 0x64
|
|
800a356: 2b00 cmp r3, #0
|
|
800a358: d003 beq.n 800a362 <HAL_UART_IRQHandler+0x194>
|
|
{
|
|
huart->RxISR(huart);
|
|
800a35a: 687b ldr r3, [r7, #4]
|
|
800a35c: 6e5b ldr r3, [r3, #100] ; 0x64
|
|
800a35e: 6878 ldr r0, [r7, #4]
|
|
800a360: 4798 blx r3
|
|
/* If Error is to be considered as blocking :
|
|
- Receiver Timeout error in Reception
|
|
- Overrun error in Reception
|
|
- any error occurs in DMA mode reception
|
|
*/
|
|
errorcode = huart->ErrorCode;
|
|
800a362: 687b ldr r3, [r7, #4]
|
|
800a364: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a368: 60fb str r3, [r7, #12]
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
800a36a: 687b ldr r3, [r7, #4]
|
|
800a36c: 681b ldr r3, [r3, #0]
|
|
800a36e: 689b ldr r3, [r3, #8]
|
|
800a370: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a374: 2b40 cmp r3, #64 ; 0x40
|
|
800a376: d004 beq.n 800a382 <HAL_UART_IRQHandler+0x1b4>
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
800a378: 68fb ldr r3, [r7, #12]
|
|
800a37a: f003 0328 and.w r3, r3, #40 ; 0x28
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
800a37e: 2b00 cmp r3, #0
|
|
800a380: d034 beq.n 800a3ec <HAL_UART_IRQHandler+0x21e>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
800a382: 6878 ldr r0, [r7, #4]
|
|
800a384: f000 fd57 bl 800ae36 <UART_EndRxTransfer>
|
|
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800a388: 687b ldr r3, [r7, #4]
|
|
800a38a: 681b ldr r3, [r3, #0]
|
|
800a38c: 689b ldr r3, [r3, #8]
|
|
800a38e: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a392: 2b40 cmp r3, #64 ; 0x40
|
|
800a394: d126 bne.n 800a3e4 <HAL_UART_IRQHandler+0x216>
|
|
{
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800a396: 687b ldr r3, [r7, #4]
|
|
800a398: 681b ldr r3, [r3, #0]
|
|
800a39a: 689a ldr r2, [r3, #8]
|
|
800a39c: 687b ldr r3, [r7, #4]
|
|
800a39e: 681b ldr r3, [r3, #0]
|
|
800a3a0: f022 0240 bic.w r2, r2, #64 ; 0x40
|
|
800a3a4: 609a str r2, [r3, #8]
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
if (huart->hdmarx != NULL)
|
|
800a3a6: 687b ldr r3, [r7, #4]
|
|
800a3a8: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800a3aa: 2b00 cmp r3, #0
|
|
800a3ac: d016 beq.n 800a3dc <HAL_UART_IRQHandler+0x20e>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
800a3ae: 687b ldr r3, [r7, #4]
|
|
800a3b0: 6f1a ldr r2, [r3, #112] ; 0x70
|
|
800a3b2: f64a 6395 movw r3, #44693 ; 0xae95
|
|
800a3b6: f6c0 0300 movt r3, #2048 ; 0x800
|
|
800a3ba: 6393 str r3, [r2, #56] ; 0x38
|
|
|
|
/* Abort DMA RX */
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
800a3bc: 687b ldr r3, [r7, #4]
|
|
800a3be: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800a3c0: 4618 mov r0, r3
|
|
800a3c2: f7fc f93e bl 8006642 <HAL_DMA_Abort_IT>
|
|
800a3c6: 4603 mov r3, r0
|
|
800a3c8: 2b00 cmp r3, #0
|
|
800a3ca: d017 beq.n 800a3fc <HAL_UART_IRQHandler+0x22e>
|
|
{
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
800a3cc: 687b ldr r3, [r7, #4]
|
|
800a3ce: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800a3d0: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800a3d2: 687a ldr r2, [r7, #4]
|
|
800a3d4: 6f12 ldr r2, [r2, #112] ; 0x70
|
|
800a3d6: 4610 mov r0, r2
|
|
800a3d8: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800a3da: e00f b.n 800a3fc <HAL_UART_IRQHandler+0x22e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800a3dc: 6878 ldr r0, [r7, #4]
|
|
800a3de: f000 f903 bl 800a5e8 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800a3e2: e00b b.n 800a3fc <HAL_UART_IRQHandler+0x22e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800a3e4: 6878 ldr r0, [r7, #4]
|
|
800a3e6: f000 f8ff bl 800a5e8 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800a3ea: e007 b.n 800a3fc <HAL_UART_IRQHandler+0x22e>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800a3ec: 6878 ldr r0, [r7, #4]
|
|
800a3ee: f000 f8fb bl 800a5e8 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800a3f2: 687b ldr r3, [r7, #4]
|
|
800a3f4: 2200 movs r2, #0
|
|
800a3f6: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
}
|
|
}
|
|
return;
|
|
800a3fa: e0e1 b.n 800a5c0 <HAL_UART_IRQHandler+0x3f2>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800a3fc: bf00 nop
|
|
return;
|
|
800a3fe: e0df b.n 800a5c0 <HAL_UART_IRQHandler+0x3f2>
|
|
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800a400: 687b ldr r3, [r7, #4]
|
|
800a402: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
800a404: 2b01 cmp r3, #1
|
|
800a406: f040 80a5 bne.w 800a554 <HAL_UART_IRQHandler+0x386>
|
|
&&((isrflags & USART_ISR_IDLE) != 0U)
|
|
800a40a: 69fb ldr r3, [r7, #28]
|
|
800a40c: f003 0310 and.w r3, r3, #16
|
|
800a410: 2b00 cmp r3, #0
|
|
800a412: f000 809f beq.w 800a554 <HAL_UART_IRQHandler+0x386>
|
|
&&((cr1its & USART_ISR_IDLE) != 0U))
|
|
800a416: 69bb ldr r3, [r7, #24]
|
|
800a418: f003 0310 and.w r3, r3, #16
|
|
800a41c: 2b00 cmp r3, #0
|
|
800a41e: f000 8099 beq.w 800a554 <HAL_UART_IRQHandler+0x386>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
800a422: 687b ldr r3, [r7, #4]
|
|
800a424: 681b ldr r3, [r3, #0]
|
|
800a426: 2210 movs r2, #16
|
|
800a428: 621a str r2, [r3, #32]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
800a42a: 687b ldr r3, [r7, #4]
|
|
800a42c: 681b ldr r3, [r3, #0]
|
|
800a42e: 689b ldr r3, [r3, #8]
|
|
800a430: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a434: 2b40 cmp r3, #64 ; 0x40
|
|
800a436: d154 bne.n 800a4e2 <HAL_UART_IRQHandler+0x314>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
800a438: 687b ldr r3, [r7, #4]
|
|
800a43a: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800a43c: 681b ldr r3, [r3, #0]
|
|
800a43e: 685b ldr r3, [r3, #4]
|
|
800a440: 813b strh r3, [r7, #8]
|
|
if ( (nb_remaining_rx_data > 0U)
|
|
800a442: 893b ldrh r3, [r7, #8]
|
|
800a444: 2b00 cmp r3, #0
|
|
800a446: f000 80bd beq.w 800a5c4 <HAL_UART_IRQHandler+0x3f6>
|
|
&&(nb_remaining_rx_data < huart->RxXferSize))
|
|
800a44a: 687b ldr r3, [r7, #4]
|
|
800a44c: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
|
|
800a450: 893a ldrh r2, [r7, #8]
|
|
800a452: 429a cmp r2, r3
|
|
800a454: f080 80b6 bcs.w 800a5c4 <HAL_UART_IRQHandler+0x3f6>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
800a458: 687b ldr r3, [r7, #4]
|
|
800a45a: 893a ldrh r2, [r7, #8]
|
|
800a45c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
800a460: 687b ldr r3, [r7, #4]
|
|
800a462: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800a464: 681b ldr r3, [r3, #0]
|
|
800a466: 681b ldr r3, [r3, #0]
|
|
800a468: f003 0320 and.w r3, r3, #32
|
|
800a46c: 2b00 cmp r3, #0
|
|
800a46e: d12a bne.n 800a4c6 <HAL_UART_IRQHandler+0x2f8>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
800a470: 687b ldr r3, [r7, #4]
|
|
800a472: 681b ldr r3, [r3, #0]
|
|
800a474: 681a ldr r2, [r3, #0]
|
|
800a476: 687b ldr r3, [r7, #4]
|
|
800a478: 681b ldr r3, [r3, #0]
|
|
800a47a: f422 7280 bic.w r2, r2, #256 ; 0x100
|
|
800a47e: 601a str r2, [r3, #0]
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800a480: 687b ldr r3, [r7, #4]
|
|
800a482: 681b ldr r3, [r3, #0]
|
|
800a484: 689a ldr r2, [r3, #8]
|
|
800a486: 687b ldr r3, [r7, #4]
|
|
800a488: 681b ldr r3, [r3, #0]
|
|
800a48a: f022 0201 bic.w r2, r2, #1
|
|
800a48e: 609a str r2, [r3, #8]
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800a490: 687b ldr r3, [r7, #4]
|
|
800a492: 681b ldr r3, [r3, #0]
|
|
800a494: 689a ldr r2, [r3, #8]
|
|
800a496: 687b ldr r3, [r7, #4]
|
|
800a498: 681b ldr r3, [r3, #0]
|
|
800a49a: f022 0240 bic.w r2, r2, #64 ; 0x40
|
|
800a49e: 609a str r2, [r3, #8]
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800a4a0: 687b ldr r3, [r7, #4]
|
|
800a4a2: 2220 movs r2, #32
|
|
800a4a4: 67da str r2, [r3, #124] ; 0x7c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800a4a6: 687b ldr r3, [r7, #4]
|
|
800a4a8: 2200 movs r2, #0
|
|
800a4aa: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800a4ac: 687b ldr r3, [r7, #4]
|
|
800a4ae: 681b ldr r3, [r3, #0]
|
|
800a4b0: 681a ldr r2, [r3, #0]
|
|
800a4b2: 687b ldr r3, [r7, #4]
|
|
800a4b4: 681b ldr r3, [r3, #0]
|
|
800a4b6: f022 0210 bic.w r2, r2, #16
|
|
800a4ba: 601a str r2, [r3, #0]
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
800a4bc: 687b ldr r3, [r7, #4]
|
|
800a4be: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800a4c0: 4618 mov r0, r3
|
|
800a4c2: f7fc f880 bl 80065c6 <HAL_DMA_Abort>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
800a4c6: 687b ldr r3, [r7, #4]
|
|
800a4c8: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
|
|
800a4cc: 687b ldr r3, [r7, #4]
|
|
800a4ce: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
800a4d2: b29b uxth r3, r3
|
|
800a4d4: 1ad3 subs r3, r2, r3
|
|
800a4d6: b29b uxth r3, r3
|
|
800a4d8: 4619 mov r1, r3
|
|
800a4da: 6878 ldr r0, [r7, #4]
|
|
800a4dc: f000 f88e bl 800a5fc <HAL_UARTEx_RxEventCallback>
|
|
#endif
|
|
}
|
|
return;
|
|
800a4e0: e070 b.n 800a5c4 <HAL_UART_IRQHandler+0x3f6>
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
800a4e2: 687b ldr r3, [r7, #4]
|
|
800a4e4: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
|
|
800a4e8: 687b ldr r3, [r7, #4]
|
|
800a4ea: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
800a4ee: b29b uxth r3, r3
|
|
800a4f0: 1ad3 subs r3, r2, r3
|
|
800a4f2: 817b strh r3, [r7, #10]
|
|
if ( (huart->RxXferCount > 0U)
|
|
800a4f4: 687b ldr r3, [r7, #4]
|
|
800a4f6: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
|
|
800a4fa: b29b uxth r3, r3
|
|
800a4fc: 2b00 cmp r3, #0
|
|
800a4fe: d063 beq.n 800a5c8 <HAL_UART_IRQHandler+0x3fa>
|
|
&&(nb_rx_data > 0U) )
|
|
800a500: 897b ldrh r3, [r7, #10]
|
|
800a502: 2b00 cmp r3, #0
|
|
800a504: d060 beq.n 800a5c8 <HAL_UART_IRQHandler+0x3fa>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
800a506: 687b ldr r3, [r7, #4]
|
|
800a508: 681b ldr r3, [r3, #0]
|
|
800a50a: 681a ldr r2, [r3, #0]
|
|
800a50c: 687b ldr r3, [r7, #4]
|
|
800a50e: 681b ldr r3, [r3, #0]
|
|
800a510: f422 7290 bic.w r2, r2, #288 ; 0x120
|
|
800a514: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800a516: 687b ldr r3, [r7, #4]
|
|
800a518: 681b ldr r3, [r3, #0]
|
|
800a51a: 689a ldr r2, [r3, #8]
|
|
800a51c: 687b ldr r3, [r7, #4]
|
|
800a51e: 681b ldr r3, [r3, #0]
|
|
800a520: f022 0201 bic.w r2, r2, #1
|
|
800a524: 609a str r2, [r3, #8]
|
|
#endif
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800a526: 687b ldr r3, [r7, #4]
|
|
800a528: 2220 movs r2, #32
|
|
800a52a: 67da str r2, [r3, #124] ; 0x7c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800a52c: 687b ldr r3, [r7, #4]
|
|
800a52e: 2200 movs r2, #0
|
|
800a530: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
800a532: 687b ldr r3, [r7, #4]
|
|
800a534: 2200 movs r2, #0
|
|
800a536: 665a str r2, [r3, #100] ; 0x64
|
|
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800a538: 687b ldr r3, [r7, #4]
|
|
800a53a: 681b ldr r3, [r3, #0]
|
|
800a53c: 681a ldr r2, [r3, #0]
|
|
800a53e: 687b ldr r3, [r7, #4]
|
|
800a540: 681b ldr r3, [r3, #0]
|
|
800a542: f022 0210 bic.w r2, r2, #16
|
|
800a546: 601a str r2, [r3, #0]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
800a548: 897b ldrh r3, [r7, #10]
|
|
800a54a: 4619 mov r1, r3
|
|
800a54c: 6878 ldr r0, [r7, #4]
|
|
800a54e: f000 f855 bl 800a5fc <HAL_UARTEx_RxEventCallback>
|
|
#endif
|
|
}
|
|
return;
|
|
800a552: e039 b.n 800a5c8 <HAL_UART_IRQHandler+0x3fa>
|
|
}
|
|
}
|
|
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
800a554: 69fb ldr r3, [r7, #28]
|
|
800a556: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
800a55a: 2b00 cmp r3, #0
|
|
800a55c: d00d beq.n 800a57a <HAL_UART_IRQHandler+0x3ac>
|
|
800a55e: 697b ldr r3, [r7, #20]
|
|
800a560: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
800a564: 2b00 cmp r3, #0
|
|
800a566: d008 beq.n 800a57a <HAL_UART_IRQHandler+0x3ac>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
800a568: 687b ldr r3, [r7, #4]
|
|
800a56a: 681b ldr r3, [r3, #0]
|
|
800a56c: f44f 1280 mov.w r2, #1048576 ; 0x100000
|
|
800a570: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Wakeup Callback */
|
|
huart->WakeupCallback(huart);
|
|
#else
|
|
/* Call legacy weak Wakeup Callback */
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
800a572: 6878 ldr r0, [r7, #4]
|
|
800a574: f000 fcbd bl 800aef2 <HAL_UARTEx_WakeupCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
800a578: e029 b.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_TXE) != 0U)
|
|
800a57a: 69fb ldr r3, [r7, #28]
|
|
800a57c: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800a580: 2b00 cmp r3, #0
|
|
800a582: d00d beq.n 800a5a0 <HAL_UART_IRQHandler+0x3d2>
|
|
&& ((cr1its & USART_CR1_TXEIE) != 0U))
|
|
800a584: 69bb ldr r3, [r7, #24]
|
|
800a586: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800a58a: 2b00 cmp r3, #0
|
|
800a58c: d008 beq.n 800a5a0 <HAL_UART_IRQHandler+0x3d2>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->TxISR != NULL)
|
|
800a58e: 687b ldr r3, [r7, #4]
|
|
800a590: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
800a592: 2b00 cmp r3, #0
|
|
800a594: d01a beq.n 800a5cc <HAL_UART_IRQHandler+0x3fe>
|
|
{
|
|
huart->TxISR(huart);
|
|
800a596: 687b ldr r3, [r7, #4]
|
|
800a598: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
800a59a: 6878 ldr r0, [r7, #4]
|
|
800a59c: 4798 blx r3
|
|
}
|
|
return;
|
|
800a59e: e015 b.n 800a5cc <HAL_UART_IRQHandler+0x3fe>
|
|
}
|
|
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
800a5a0: 69fb ldr r3, [r7, #28]
|
|
800a5a2: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a5a6: 2b00 cmp r3, #0
|
|
800a5a8: d011 beq.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
800a5aa: 69bb ldr r3, [r7, #24]
|
|
800a5ac: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a5b0: 2b00 cmp r3, #0
|
|
800a5b2: d00c beq.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
800a5b4: 6878 ldr r0, [r7, #4]
|
|
800a5b6: f000 fc83 bl 800aec0 <UART_EndTransmit_IT>
|
|
return;
|
|
800a5ba: e008 b.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
return;
|
|
800a5bc: bf00 nop
|
|
800a5be: e006 b.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
return;
|
|
800a5c0: bf00 nop
|
|
800a5c2: e004 b.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
return;
|
|
800a5c4: bf00 nop
|
|
800a5c6: e002 b.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
return;
|
|
800a5c8: bf00 nop
|
|
800a5ca: e000 b.n 800a5ce <HAL_UART_IRQHandler+0x400>
|
|
return;
|
|
800a5cc: bf00 nop
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
}
|
|
#endif /* USART_CR1_FIFOEN */
|
|
}
|
|
800a5ce: 3720 adds r7, #32
|
|
800a5d0: 46bd mov sp, r7
|
|
800a5d2: bd80 pop {r7, pc}
|
|
|
|
0800a5d4 <HAL_UART_TxCpltCallback>:
|
|
* @brief Tx Transfer completed callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800a5d4: b480 push {r7}
|
|
800a5d6: b083 sub sp, #12
|
|
800a5d8: af00 add r7, sp, #0
|
|
800a5da: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800a5dc: bf00 nop
|
|
800a5de: 370c adds r7, #12
|
|
800a5e0: 46bd mov sp, r7
|
|
800a5e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a5e6: 4770 bx lr
|
|
|
|
0800a5e8 <HAL_UART_ErrorCallback>:
|
|
* @brief UART error callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800a5e8: b480 push {r7}
|
|
800a5ea: b083 sub sp, #12
|
|
800a5ec: af00 add r7, sp, #0
|
|
800a5ee: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800a5f0: bf00 nop
|
|
800a5f2: 370c adds r7, #12
|
|
800a5f4: 46bd mov sp, r7
|
|
800a5f6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a5fa: 4770 bx lr
|
|
|
|
0800a5fc <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
800a5fc: b480 push {r7}
|
|
800a5fe: b083 sub sp, #12
|
|
800a600: af00 add r7, sp, #0
|
|
800a602: 6078 str r0, [r7, #4]
|
|
800a604: 460b mov r3, r1
|
|
800a606: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800a608: bf00 nop
|
|
800a60a: 370c adds r7, #12
|
|
800a60c: 46bd mov sp, r7
|
|
800a60e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a612: 4770 bx lr
|
|
|
|
0800a614 <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800a614: b5b0 push {r4, r5, r7, lr}
|
|
800a616: b088 sub sp, #32
|
|
800a618: af00 add r7, sp, #0
|
|
800a61a: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800a61c: 2300 movs r3, #0
|
|
800a61e: 76bb strb r3, [r7, #26]
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
800a620: 687b ldr r3, [r7, #4]
|
|
800a622: 689a ldr r2, [r3, #8]
|
|
800a624: 687b ldr r3, [r7, #4]
|
|
800a626: 691b ldr r3, [r3, #16]
|
|
800a628: 431a orrs r2, r3
|
|
800a62a: 687b ldr r3, [r7, #4]
|
|
800a62c: 695b ldr r3, [r3, #20]
|
|
800a62e: 431a orrs r2, r3
|
|
800a630: 687b ldr r3, [r7, #4]
|
|
800a632: 69db ldr r3, [r3, #28]
|
|
800a634: 4313 orrs r3, r2
|
|
800a636: 61fb str r3, [r7, #28]
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
800a638: 687b ldr r3, [r7, #4]
|
|
800a63a: 681b ldr r3, [r3, #0]
|
|
800a63c: 681a ldr r2, [r3, #0]
|
|
800a63e: f646 13f3 movw r3, #27123 ; 0x69f3
|
|
800a642: f6ce 73ff movt r3, #61439 ; 0xefff
|
|
800a646: 4013 ands r3, r2
|
|
800a648: 687a ldr r2, [r7, #4]
|
|
800a64a: 6812 ldr r2, [r2, #0]
|
|
800a64c: 69f9 ldr r1, [r7, #28]
|
|
800a64e: 430b orrs r3, r1
|
|
800a650: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
800a652: 687b ldr r3, [r7, #4]
|
|
800a654: 681b ldr r3, [r3, #0]
|
|
800a656: 685b ldr r3, [r3, #4]
|
|
800a658: f423 5140 bic.w r1, r3, #12288 ; 0x3000
|
|
800a65c: 687b ldr r3, [r7, #4]
|
|
800a65e: 68da ldr r2, [r3, #12]
|
|
800a660: 687b ldr r3, [r7, #4]
|
|
800a662: 681b ldr r3, [r3, #0]
|
|
800a664: 430a orrs r2, r1
|
|
800a666: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
800a668: 687b ldr r3, [r7, #4]
|
|
800a66a: 699b ldr r3, [r3, #24]
|
|
800a66c: 61fb str r3, [r7, #28]
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
800a66e: 687b ldr r3, [r7, #4]
|
|
800a670: 681a ldr r2, [r3, #0]
|
|
800a672: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
800a676: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800a67a: 429a cmp r2, r3
|
|
800a67c: d004 beq.n 800a688 <UART_SetConfig+0x74>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
800a67e: 687b ldr r3, [r7, #4]
|
|
800a680: 6a1b ldr r3, [r3, #32]
|
|
800a682: 69fa ldr r2, [r7, #28]
|
|
800a684: 4313 orrs r3, r2
|
|
800a686: 61fb str r3, [r7, #28]
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
800a688: 687b ldr r3, [r7, #4]
|
|
800a68a: 681b ldr r3, [r3, #0]
|
|
800a68c: 689b ldr r3, [r3, #8]
|
|
800a68e: f423 6130 bic.w r1, r3, #2816 ; 0xb00
|
|
800a692: 687b ldr r3, [r7, #4]
|
|
800a694: 681b ldr r3, [r3, #0]
|
|
800a696: 69fa ldr r2, [r7, #28]
|
|
800a698: 430a orrs r2, r1
|
|
800a69a: 609a str r2, [r3, #8]
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
800a69c: 687b ldr r3, [r7, #4]
|
|
800a69e: 681a ldr r2, [r3, #0]
|
|
800a6a0: f44f 5360 mov.w r3, #14336 ; 0x3800
|
|
800a6a4: f2c4 0301 movt r3, #16385 ; 0x4001
|
|
800a6a8: 429a cmp r2, r3
|
|
800a6aa: d124 bne.n 800a6f6 <UART_SetConfig+0xe2>
|
|
800a6ac: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800a6b0: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800a6b4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a6b8: f003 0303 and.w r3, r3, #3
|
|
800a6bc: 2b03 cmp r3, #3
|
|
800a6be: d817 bhi.n 800a6f0 <UART_SetConfig+0xdc>
|
|
800a6c0: a201 add r2, pc, #4 ; (adr r2, 800a6c8 <UART_SetConfig+0xb4>)
|
|
800a6c2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a6c6: bf00 nop
|
|
800a6c8: 0800a6d9 .word 0x0800a6d9
|
|
800a6cc: 0800a6e5 .word 0x0800a6e5
|
|
800a6d0: 0800a6df .word 0x0800a6df
|
|
800a6d4: 0800a6eb .word 0x0800a6eb
|
|
800a6d8: 2301 movs r3, #1
|
|
800a6da: 76fb strb r3, [r7, #27]
|
|
800a6dc: e105 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a6de: 2302 movs r3, #2
|
|
800a6e0: 76fb strb r3, [r7, #27]
|
|
800a6e2: e102 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a6e4: 2304 movs r3, #4
|
|
800a6e6: 76fb strb r3, [r7, #27]
|
|
800a6e8: e0ff b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a6ea: 2308 movs r3, #8
|
|
800a6ec: 76fb strb r3, [r7, #27]
|
|
800a6ee: e0fc b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a6f0: 2310 movs r3, #16
|
|
800a6f2: 76fb strb r3, [r7, #27]
|
|
800a6f4: e0f9 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a6f6: 687b ldr r3, [r7, #4]
|
|
800a6f8: 681a ldr r2, [r3, #0]
|
|
800a6fa: f44f 4388 mov.w r3, #17408 ; 0x4400
|
|
800a6fe: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800a702: 429a cmp r2, r3
|
|
800a704: d135 bne.n 800a772 <UART_SetConfig+0x15e>
|
|
800a706: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800a70a: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800a70e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a712: f003 030c and.w r3, r3, #12
|
|
800a716: 2b0c cmp r3, #12
|
|
800a718: d828 bhi.n 800a76c <UART_SetConfig+0x158>
|
|
800a71a: a201 add r2, pc, #4 ; (adr r2, 800a720 <UART_SetConfig+0x10c>)
|
|
800a71c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a720: 0800a755 .word 0x0800a755
|
|
800a724: 0800a76d .word 0x0800a76d
|
|
800a728: 0800a76d .word 0x0800a76d
|
|
800a72c: 0800a76d .word 0x0800a76d
|
|
800a730: 0800a761 .word 0x0800a761
|
|
800a734: 0800a76d .word 0x0800a76d
|
|
800a738: 0800a76d .word 0x0800a76d
|
|
800a73c: 0800a76d .word 0x0800a76d
|
|
800a740: 0800a75b .word 0x0800a75b
|
|
800a744: 0800a76d .word 0x0800a76d
|
|
800a748: 0800a76d .word 0x0800a76d
|
|
800a74c: 0800a76d .word 0x0800a76d
|
|
800a750: 0800a767 .word 0x0800a767
|
|
800a754: 2300 movs r3, #0
|
|
800a756: 76fb strb r3, [r7, #27]
|
|
800a758: e0c7 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a75a: 2302 movs r3, #2
|
|
800a75c: 76fb strb r3, [r7, #27]
|
|
800a75e: e0c4 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a760: 2304 movs r3, #4
|
|
800a762: 76fb strb r3, [r7, #27]
|
|
800a764: e0c1 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a766: 2308 movs r3, #8
|
|
800a768: 76fb strb r3, [r7, #27]
|
|
800a76a: e0be b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a76c: 2310 movs r3, #16
|
|
800a76e: 76fb strb r3, [r7, #27]
|
|
800a770: e0bb b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a772: 687b ldr r3, [r7, #4]
|
|
800a774: 681a ldr r2, [r3, #0]
|
|
800a776: f44f 4390 mov.w r3, #18432 ; 0x4800
|
|
800a77a: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800a77e: 429a cmp r2, r3
|
|
800a780: d123 bne.n 800a7ca <UART_SetConfig+0x1b6>
|
|
800a782: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800a786: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800a78a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a78e: f003 0330 and.w r3, r3, #48 ; 0x30
|
|
800a792: 2b30 cmp r3, #48 ; 0x30
|
|
800a794: d013 beq.n 800a7be <UART_SetConfig+0x1aa>
|
|
800a796: 2b30 cmp r3, #48 ; 0x30
|
|
800a798: d814 bhi.n 800a7c4 <UART_SetConfig+0x1b0>
|
|
800a79a: 2b20 cmp r3, #32
|
|
800a79c: d009 beq.n 800a7b2 <UART_SetConfig+0x19e>
|
|
800a79e: 2b20 cmp r3, #32
|
|
800a7a0: d810 bhi.n 800a7c4 <UART_SetConfig+0x1b0>
|
|
800a7a2: 2b00 cmp r3, #0
|
|
800a7a4: d002 beq.n 800a7ac <UART_SetConfig+0x198>
|
|
800a7a6: 2b10 cmp r3, #16
|
|
800a7a8: d006 beq.n 800a7b8 <UART_SetConfig+0x1a4>
|
|
800a7aa: e00b b.n 800a7c4 <UART_SetConfig+0x1b0>
|
|
800a7ac: 2300 movs r3, #0
|
|
800a7ae: 76fb strb r3, [r7, #27]
|
|
800a7b0: e09b b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a7b2: 2302 movs r3, #2
|
|
800a7b4: 76fb strb r3, [r7, #27]
|
|
800a7b6: e098 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a7b8: 2304 movs r3, #4
|
|
800a7ba: 76fb strb r3, [r7, #27]
|
|
800a7bc: e095 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a7be: 2308 movs r3, #8
|
|
800a7c0: 76fb strb r3, [r7, #27]
|
|
800a7c2: e092 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a7c4: 2310 movs r3, #16
|
|
800a7c6: 76fb strb r3, [r7, #27]
|
|
800a7c8: e08f b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a7ca: 687b ldr r3, [r7, #4]
|
|
800a7cc: 681a ldr r2, [r3, #0]
|
|
800a7ce: f44f 4398 mov.w r3, #19456 ; 0x4c00
|
|
800a7d2: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800a7d6: 429a cmp r2, r3
|
|
800a7d8: d123 bne.n 800a822 <UART_SetConfig+0x20e>
|
|
800a7da: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800a7de: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800a7e2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a7e6: f003 03c0 and.w r3, r3, #192 ; 0xc0
|
|
800a7ea: 2bc0 cmp r3, #192 ; 0xc0
|
|
800a7ec: d013 beq.n 800a816 <UART_SetConfig+0x202>
|
|
800a7ee: 2bc0 cmp r3, #192 ; 0xc0
|
|
800a7f0: d814 bhi.n 800a81c <UART_SetConfig+0x208>
|
|
800a7f2: 2b80 cmp r3, #128 ; 0x80
|
|
800a7f4: d009 beq.n 800a80a <UART_SetConfig+0x1f6>
|
|
800a7f6: 2b80 cmp r3, #128 ; 0x80
|
|
800a7f8: d810 bhi.n 800a81c <UART_SetConfig+0x208>
|
|
800a7fa: 2b00 cmp r3, #0
|
|
800a7fc: d002 beq.n 800a804 <UART_SetConfig+0x1f0>
|
|
800a7fe: 2b40 cmp r3, #64 ; 0x40
|
|
800a800: d006 beq.n 800a810 <UART_SetConfig+0x1fc>
|
|
800a802: e00b b.n 800a81c <UART_SetConfig+0x208>
|
|
800a804: 2300 movs r3, #0
|
|
800a806: 76fb strb r3, [r7, #27]
|
|
800a808: e06f b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a80a: 2302 movs r3, #2
|
|
800a80c: 76fb strb r3, [r7, #27]
|
|
800a80e: e06c b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a810: 2304 movs r3, #4
|
|
800a812: 76fb strb r3, [r7, #27]
|
|
800a814: e069 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a816: 2308 movs r3, #8
|
|
800a818: 76fb strb r3, [r7, #27]
|
|
800a81a: e066 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a81c: 2310 movs r3, #16
|
|
800a81e: 76fb strb r3, [r7, #27]
|
|
800a820: e063 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a822: 687b ldr r3, [r7, #4]
|
|
800a824: 681a ldr r2, [r3, #0]
|
|
800a826: f44f 43a0 mov.w r3, #20480 ; 0x5000
|
|
800a82a: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800a82e: 429a cmp r2, r3
|
|
800a830: d128 bne.n 800a884 <UART_SetConfig+0x270>
|
|
800a832: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800a836: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800a83a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a83e: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
800a842: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
|
800a846: d017 beq.n 800a878 <UART_SetConfig+0x264>
|
|
800a848: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
|
800a84c: d817 bhi.n 800a87e <UART_SetConfig+0x26a>
|
|
800a84e: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
800a852: d00b beq.n 800a86c <UART_SetConfig+0x258>
|
|
800a854: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
800a858: d811 bhi.n 800a87e <UART_SetConfig+0x26a>
|
|
800a85a: 2b00 cmp r3, #0
|
|
800a85c: d003 beq.n 800a866 <UART_SetConfig+0x252>
|
|
800a85e: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
800a862: d006 beq.n 800a872 <UART_SetConfig+0x25e>
|
|
800a864: e00b b.n 800a87e <UART_SetConfig+0x26a>
|
|
800a866: 2300 movs r3, #0
|
|
800a868: 76fb strb r3, [r7, #27]
|
|
800a86a: e03e b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a86c: 2302 movs r3, #2
|
|
800a86e: 76fb strb r3, [r7, #27]
|
|
800a870: e03b b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a872: 2304 movs r3, #4
|
|
800a874: 76fb strb r3, [r7, #27]
|
|
800a876: e038 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a878: 2308 movs r3, #8
|
|
800a87a: 76fb strb r3, [r7, #27]
|
|
800a87c: e035 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a87e: 2310 movs r3, #16
|
|
800a880: 76fb strb r3, [r7, #27]
|
|
800a882: e032 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a884: 687b ldr r3, [r7, #4]
|
|
800a886: 681a ldr r2, [r3, #0]
|
|
800a888: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
800a88c: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800a890: 429a cmp r2, r3
|
|
800a892: d128 bne.n 800a8e6 <UART_SetConfig+0x2d2>
|
|
800a894: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800a898: f2c4 0302 movt r3, #16386 ; 0x4002
|
|
800a89c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a8a0: f403 6340 and.w r3, r3, #3072 ; 0xc00
|
|
800a8a4: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
|
|
800a8a8: d017 beq.n 800a8da <UART_SetConfig+0x2c6>
|
|
800a8aa: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
|
|
800a8ae: d817 bhi.n 800a8e0 <UART_SetConfig+0x2cc>
|
|
800a8b0: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
800a8b4: d00b beq.n 800a8ce <UART_SetConfig+0x2ba>
|
|
800a8b6: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
800a8ba: d811 bhi.n 800a8e0 <UART_SetConfig+0x2cc>
|
|
800a8bc: 2b00 cmp r3, #0
|
|
800a8be: d003 beq.n 800a8c8 <UART_SetConfig+0x2b4>
|
|
800a8c0: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
800a8c4: d006 beq.n 800a8d4 <UART_SetConfig+0x2c0>
|
|
800a8c6: e00b b.n 800a8e0 <UART_SetConfig+0x2cc>
|
|
800a8c8: 2300 movs r3, #0
|
|
800a8ca: 76fb strb r3, [r7, #27]
|
|
800a8cc: e00d b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a8ce: 2302 movs r3, #2
|
|
800a8d0: 76fb strb r3, [r7, #27]
|
|
800a8d2: e00a b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a8d4: 2304 movs r3, #4
|
|
800a8d6: 76fb strb r3, [r7, #27]
|
|
800a8d8: e007 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a8da: 2308 movs r3, #8
|
|
800a8dc: 76fb strb r3, [r7, #27]
|
|
800a8de: e004 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a8e0: 2310 movs r3, #16
|
|
800a8e2: 76fb strb r3, [r7, #27]
|
|
800a8e4: e001 b.n 800a8ea <UART_SetConfig+0x2d6>
|
|
800a8e6: 2310 movs r3, #16
|
|
800a8e8: 76fb strb r3, [r7, #27]
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
800a8ea: 687b ldr r3, [r7, #4]
|
|
800a8ec: 681a ldr r2, [r3, #0]
|
|
800a8ee: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
800a8f2: f2c4 0300 movt r3, #16384 ; 0x4000
|
|
800a8f6: 429a cmp r2, r3
|
|
800a8f8: d176 bne.n 800a9e8 <UART_SetConfig+0x3d4>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
800a8fa: 7efb ldrb r3, [r7, #27]
|
|
800a8fc: 2b08 cmp r3, #8
|
|
800a8fe: d827 bhi.n 800a950 <UART_SetConfig+0x33c>
|
|
800a900: a201 add r2, pc, #4 ; (adr r2, 800a908 <UART_SetConfig+0x2f4>)
|
|
800a902: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a906: bf00 nop
|
|
800a908: 0800a92d .word 0x0800a92d
|
|
800a90c: 0800a951 .word 0x0800a951
|
|
800a910: 0800a935 .word 0x0800a935
|
|
800a914: 0800a951 .word 0x0800a951
|
|
800a918: 0800a941 .word 0x0800a941
|
|
800a91c: 0800a951 .word 0x0800a951
|
|
800a920: 0800a951 .word 0x0800a951
|
|
800a924: 0800a951 .word 0x0800a951
|
|
800a928: 0800a949 .word 0x0800a949
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
800a92c: f7fe f9b7 bl 8008c9e <HAL_RCC_GetPCLK1Freq>
|
|
800a930: 6178 str r0, [r7, #20]
|
|
break;
|
|
800a932: e012 b.n 800a95a <UART_SetConfig+0x346>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
800a934: f44f 5310 mov.w r3, #9216 ; 0x2400
|
|
800a938: f2c0 03f4 movt r3, #244 ; 0xf4
|
|
800a93c: 617b str r3, [r7, #20]
|
|
break;
|
|
800a93e: e00c b.n 800a95a <UART_SetConfig+0x346>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800a940: f7fe f8f4 bl 8008b2c <HAL_RCC_GetSysClockFreq>
|
|
800a944: 6178 str r0, [r7, #20]
|
|
break;
|
|
800a946: e008 b.n 800a95a <UART_SetConfig+0x346>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800a948: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
800a94c: 617b str r3, [r7, #20]
|
|
break;
|
|
800a94e: e004 b.n 800a95a <UART_SetConfig+0x346>
|
|
default:
|
|
pclk = 0U;
|
|
800a950: 2300 movs r3, #0
|
|
800a952: 617b str r3, [r7, #20]
|
|
ret = HAL_ERROR;
|
|
800a954: 2301 movs r3, #1
|
|
800a956: 76bb strb r3, [r7, #26]
|
|
break;
|
|
800a958: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
800a95a: 697b ldr r3, [r7, #20]
|
|
800a95c: 2b00 cmp r3, #0
|
|
800a95e: f000 80f8 beq.w 800ab52 <UART_SetConfig+0x53e>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
#else
|
|
/* No Prescaler applicable */
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
800a962: 687b ldr r3, [r7, #4]
|
|
800a964: 685a ldr r2, [r3, #4]
|
|
800a966: 4613 mov r3, r2
|
|
800a968: 005b lsls r3, r3, #1
|
|
800a96a: 4413 add r3, r2
|
|
800a96c: 697a ldr r2, [r7, #20]
|
|
800a96e: 429a cmp r2, r3
|
|
800a970: d305 bcc.n 800a97e <UART_SetConfig+0x36a>
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
|
800a972: 687b ldr r3, [r7, #4]
|
|
800a974: 685b ldr r3, [r3, #4]
|
|
800a976: 031b lsls r3, r3, #12
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
800a978: 697a ldr r2, [r7, #20]
|
|
800a97a: 429a cmp r2, r3
|
|
800a97c: d902 bls.n 800a984 <UART_SetConfig+0x370>
|
|
{
|
|
ret = HAL_ERROR;
|
|
800a97e: 2301 movs r3, #1
|
|
800a980: 76bb strb r3, [r7, #26]
|
|
800a982: e0e6 b.n 800ab52 <UART_SetConfig+0x53e>
|
|
}
|
|
else
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
|
800a984: 697b ldr r3, [r7, #20]
|
|
800a986: 4618 mov r0, r3
|
|
800a988: f04f 0100 mov.w r1, #0
|
|
800a98c: f04f 0200 mov.w r2, #0
|
|
800a990: f04f 0300 mov.w r3, #0
|
|
800a994: 020b lsls r3, r1, #8
|
|
800a996: ea43 6310 orr.w r3, r3, r0, lsr #24
|
|
800a99a: 0202 lsls r2, r0, #8
|
|
800a99c: 6879 ldr r1, [r7, #4]
|
|
800a99e: 6849 ldr r1, [r1, #4]
|
|
800a9a0: 0849 lsrs r1, r1, #1
|
|
800a9a2: 4608 mov r0, r1
|
|
800a9a4: f04f 0100 mov.w r1, #0
|
|
800a9a8: 1814 adds r4, r2, r0
|
|
800a9aa: eb43 0501 adc.w r5, r3, r1
|
|
800a9ae: 687b ldr r3, [r7, #4]
|
|
800a9b0: 685b ldr r3, [r3, #4]
|
|
800a9b2: 461a mov r2, r3
|
|
800a9b4: f04f 0300 mov.w r3, #0
|
|
800a9b8: 4620 mov r0, r4
|
|
800a9ba: 4629 mov r1, r5
|
|
800a9bc: f7f6 f994 bl 8000ce8 <__aeabi_uldivmod>
|
|
800a9c0: 4602 mov r2, r0
|
|
800a9c2: 460b mov r3, r1
|
|
800a9c4: 4613 mov r3, r2
|
|
800a9c6: 613b str r3, [r7, #16]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
800a9c8: 693b ldr r3, [r7, #16]
|
|
800a9ca: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
|
800a9ce: d308 bcc.n 800a9e2 <UART_SetConfig+0x3ce>
|
|
800a9d0: 693b ldr r3, [r7, #16]
|
|
800a9d2: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
|
800a9d6: d204 bcs.n 800a9e2 <UART_SetConfig+0x3ce>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
800a9d8: 687b ldr r3, [r7, #4]
|
|
800a9da: 681b ldr r3, [r3, #0]
|
|
800a9dc: 693a ldr r2, [r7, #16]
|
|
800a9de: 60da str r2, [r3, #12]
|
|
800a9e0: e0b7 b.n 800ab52 <UART_SetConfig+0x53e>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800a9e2: 2301 movs r3, #1
|
|
800a9e4: 76bb strb r3, [r7, #26]
|
|
800a9e6: e0b4 b.n 800ab52 <UART_SetConfig+0x53e>
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
800a9e8: 687b ldr r3, [r7, #4]
|
|
800a9ea: 69db ldr r3, [r3, #28]
|
|
800a9ec: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
|
|
800a9f0: d15f bne.n 800aab2 <UART_SetConfig+0x49e>
|
|
{
|
|
switch (clocksource)
|
|
800a9f2: 7efb ldrb r3, [r7, #27]
|
|
800a9f4: 2b08 cmp r3, #8
|
|
800a9f6: d82b bhi.n 800aa50 <UART_SetConfig+0x43c>
|
|
800a9f8: a201 add r2, pc, #4 ; (adr r2, 800aa00 <UART_SetConfig+0x3ec>)
|
|
800a9fa: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800a9fe: bf00 nop
|
|
800aa00: 0800aa25 .word 0x0800aa25
|
|
800aa04: 0800aa2d .word 0x0800aa2d
|
|
800aa08: 0800aa35 .word 0x0800aa35
|
|
800aa0c: 0800aa51 .word 0x0800aa51
|
|
800aa10: 0800aa41 .word 0x0800aa41
|
|
800aa14: 0800aa51 .word 0x0800aa51
|
|
800aa18: 0800aa51 .word 0x0800aa51
|
|
800aa1c: 0800aa51 .word 0x0800aa51
|
|
800aa20: 0800aa49 .word 0x0800aa49
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
800aa24: f7fe f93b bl 8008c9e <HAL_RCC_GetPCLK1Freq>
|
|
800aa28: 6178 str r0, [r7, #20]
|
|
break;
|
|
800aa2a: e016 b.n 800aa5a <UART_SetConfig+0x446>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800aa2c: f7fe f94f bl 8008cce <HAL_RCC_GetPCLK2Freq>
|
|
800aa30: 6178 str r0, [r7, #20]
|
|
break;
|
|
800aa32: e012 b.n 800aa5a <UART_SetConfig+0x446>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
800aa34: f44f 5310 mov.w r3, #9216 ; 0x2400
|
|
800aa38: f2c0 03f4 movt r3, #244 ; 0xf4
|
|
800aa3c: 617b str r3, [r7, #20]
|
|
break;
|
|
800aa3e: e00c b.n 800aa5a <UART_SetConfig+0x446>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800aa40: f7fe f874 bl 8008b2c <HAL_RCC_GetSysClockFreq>
|
|
800aa44: 6178 str r0, [r7, #20]
|
|
break;
|
|
800aa46: e008 b.n 800aa5a <UART_SetConfig+0x446>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800aa48: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
800aa4c: 617b str r3, [r7, #20]
|
|
break;
|
|
800aa4e: e004 b.n 800aa5a <UART_SetConfig+0x446>
|
|
default:
|
|
pclk = 0U;
|
|
800aa50: 2300 movs r3, #0
|
|
800aa52: 617b str r3, [r7, #20]
|
|
ret = HAL_ERROR;
|
|
800aa54: 2301 movs r3, #1
|
|
800aa56: 76bb strb r3, [r7, #26]
|
|
break;
|
|
800aa58: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
800aa5a: 697b ldr r3, [r7, #20]
|
|
800aa5c: 2b00 cmp r3, #0
|
|
800aa5e: d078 beq.n 800ab52 <UART_SetConfig+0x53e>
|
|
{
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
800aa60: 697b ldr r3, [r7, #20]
|
|
800aa62: 005a lsls r2, r3, #1
|
|
800aa64: 687b ldr r3, [r7, #4]
|
|
800aa66: 685b ldr r3, [r3, #4]
|
|
800aa68: 085b lsrs r3, r3, #1
|
|
800aa6a: 441a add r2, r3
|
|
800aa6c: 687b ldr r3, [r7, #4]
|
|
800aa6e: 685b ldr r3, [r3, #4]
|
|
800aa70: fbb2 f3f3 udiv r3, r2, r3
|
|
800aa74: b29b uxth r3, r3
|
|
800aa76: 613b str r3, [r7, #16]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
800aa78: 693b ldr r3, [r7, #16]
|
|
800aa7a: 2b0f cmp r3, #15
|
|
800aa7c: d916 bls.n 800aaac <UART_SetConfig+0x498>
|
|
800aa7e: 693b ldr r3, [r7, #16]
|
|
800aa80: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
800aa84: d212 bcs.n 800aaac <UART_SetConfig+0x498>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
800aa86: 693b ldr r3, [r7, #16]
|
|
800aa88: b29b uxth r3, r3
|
|
800aa8a: f023 030f bic.w r3, r3, #15
|
|
800aa8e: 81fb strh r3, [r7, #14]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
800aa90: 693b ldr r3, [r7, #16]
|
|
800aa92: 085b lsrs r3, r3, #1
|
|
800aa94: b29b uxth r3, r3
|
|
800aa96: f003 0307 and.w r3, r3, #7
|
|
800aa9a: b29a uxth r2, r3
|
|
800aa9c: 89fb ldrh r3, [r7, #14]
|
|
800aa9e: 4313 orrs r3, r2
|
|
800aaa0: 81fb strh r3, [r7, #14]
|
|
huart->Instance->BRR = brrtemp;
|
|
800aaa2: 687b ldr r3, [r7, #4]
|
|
800aaa4: 681b ldr r3, [r3, #0]
|
|
800aaa6: 89fa ldrh r2, [r7, #14]
|
|
800aaa8: 60da str r2, [r3, #12]
|
|
800aaaa: e052 b.n 800ab52 <UART_SetConfig+0x53e>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800aaac: 2301 movs r3, #1
|
|
800aaae: 76bb strb r3, [r7, #26]
|
|
800aab0: e04f b.n 800ab52 <UART_SetConfig+0x53e>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
800aab2: 7efb ldrb r3, [r7, #27]
|
|
800aab4: 2b08 cmp r3, #8
|
|
800aab6: d82b bhi.n 800ab10 <UART_SetConfig+0x4fc>
|
|
800aab8: a201 add r2, pc, #4 ; (adr r2, 800aac0 <UART_SetConfig+0x4ac>)
|
|
800aaba: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800aabe: bf00 nop
|
|
800aac0: 0800aae5 .word 0x0800aae5
|
|
800aac4: 0800aaed .word 0x0800aaed
|
|
800aac8: 0800aaf5 .word 0x0800aaf5
|
|
800aacc: 0800ab11 .word 0x0800ab11
|
|
800aad0: 0800ab01 .word 0x0800ab01
|
|
800aad4: 0800ab11 .word 0x0800ab11
|
|
800aad8: 0800ab11 .word 0x0800ab11
|
|
800aadc: 0800ab11 .word 0x0800ab11
|
|
800aae0: 0800ab09 .word 0x0800ab09
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
800aae4: f7fe f8db bl 8008c9e <HAL_RCC_GetPCLK1Freq>
|
|
800aae8: 6178 str r0, [r7, #20]
|
|
break;
|
|
800aaea: e016 b.n 800ab1a <UART_SetConfig+0x506>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800aaec: f7fe f8ef bl 8008cce <HAL_RCC_GetPCLK2Freq>
|
|
800aaf0: 6178 str r0, [r7, #20]
|
|
break;
|
|
800aaf2: e012 b.n 800ab1a <UART_SetConfig+0x506>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
800aaf4: f44f 5310 mov.w r3, #9216 ; 0x2400
|
|
800aaf8: f2c0 03f4 movt r3, #244 ; 0xf4
|
|
800aafc: 617b str r3, [r7, #20]
|
|
break;
|
|
800aafe: e00c b.n 800ab1a <UART_SetConfig+0x506>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800ab00: f7fe f814 bl 8008b2c <HAL_RCC_GetSysClockFreq>
|
|
800ab04: 6178 str r0, [r7, #20]
|
|
break;
|
|
800ab06: e008 b.n 800ab1a <UART_SetConfig+0x506>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
800ab08: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
800ab0c: 617b str r3, [r7, #20]
|
|
break;
|
|
800ab0e: e004 b.n 800ab1a <UART_SetConfig+0x506>
|
|
default:
|
|
pclk = 0U;
|
|
800ab10: 2300 movs r3, #0
|
|
800ab12: 617b str r3, [r7, #20]
|
|
ret = HAL_ERROR;
|
|
800ab14: 2301 movs r3, #1
|
|
800ab16: 76bb strb r3, [r7, #26]
|
|
break;
|
|
800ab18: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
800ab1a: 697b ldr r3, [r7, #20]
|
|
800ab1c: 2b00 cmp r3, #0
|
|
800ab1e: d018 beq.n 800ab52 <UART_SetConfig+0x53e>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
800ab20: 687b ldr r3, [r7, #4]
|
|
800ab22: 685b ldr r3, [r3, #4]
|
|
800ab24: 085a lsrs r2, r3, #1
|
|
800ab26: 697b ldr r3, [r7, #20]
|
|
800ab28: 441a add r2, r3
|
|
800ab2a: 687b ldr r3, [r7, #4]
|
|
800ab2c: 685b ldr r3, [r3, #4]
|
|
800ab2e: fbb2 f3f3 udiv r3, r2, r3
|
|
800ab32: b29b uxth r3, r3
|
|
800ab34: 613b str r3, [r7, #16]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
800ab36: 693b ldr r3, [r7, #16]
|
|
800ab38: 2b0f cmp r3, #15
|
|
800ab3a: d908 bls.n 800ab4e <UART_SetConfig+0x53a>
|
|
800ab3c: 693b ldr r3, [r7, #16]
|
|
800ab3e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
800ab42: d204 bcs.n 800ab4e <UART_SetConfig+0x53a>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
800ab44: 687b ldr r3, [r7, #4]
|
|
800ab46: 681b ldr r3, [r3, #0]
|
|
800ab48: 693a ldr r2, [r7, #16]
|
|
800ab4a: 60da str r2, [r3, #12]
|
|
800ab4c: e001 b.n 800ab52 <UART_SetConfig+0x53e>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800ab4e: 2301 movs r3, #1
|
|
800ab50: 76bb strb r3, [r7, #26]
|
|
huart->NbTxDataToProcess = 1;
|
|
huart->NbRxDataToProcess = 1;
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
800ab52: 687b ldr r3, [r7, #4]
|
|
800ab54: 2200 movs r2, #0
|
|
800ab56: 665a str r2, [r3, #100] ; 0x64
|
|
huart->TxISR = NULL;
|
|
800ab58: 687b ldr r3, [r7, #4]
|
|
800ab5a: 2200 movs r2, #0
|
|
800ab5c: 669a str r2, [r3, #104] ; 0x68
|
|
|
|
return ret;
|
|
800ab5e: 7ebb ldrb r3, [r7, #26]
|
|
}
|
|
800ab60: 4618 mov r0, r3
|
|
800ab62: 3720 adds r7, #32
|
|
800ab64: 46bd mov sp, r7
|
|
800ab66: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
0800ab68 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800ab68: b480 push {r7}
|
|
800ab6a: b083 sub sp, #12
|
|
800ab6c: af00 add r7, sp, #0
|
|
800ab6e: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
800ab70: 687b ldr r3, [r7, #4]
|
|
800ab72: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800ab74: f003 0301 and.w r3, r3, #1
|
|
800ab78: 2b00 cmp r3, #0
|
|
800ab7a: d00a beq.n 800ab92 <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
800ab7c: 687b ldr r3, [r7, #4]
|
|
800ab7e: 681b ldr r3, [r3, #0]
|
|
800ab80: 685b ldr r3, [r3, #4]
|
|
800ab82: f423 3100 bic.w r1, r3, #131072 ; 0x20000
|
|
800ab86: 687b ldr r3, [r7, #4]
|
|
800ab88: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
800ab8a: 687b ldr r3, [r7, #4]
|
|
800ab8c: 681b ldr r3, [r3, #0]
|
|
800ab8e: 430a orrs r2, r1
|
|
800ab90: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
800ab92: 687b ldr r3, [r7, #4]
|
|
800ab94: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800ab96: f003 0302 and.w r3, r3, #2
|
|
800ab9a: 2b00 cmp r3, #0
|
|
800ab9c: d00a beq.n 800abb4 <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
800ab9e: 687b ldr r3, [r7, #4]
|
|
800aba0: 681b ldr r3, [r3, #0]
|
|
800aba2: 685b ldr r3, [r3, #4]
|
|
800aba4: f423 3180 bic.w r1, r3, #65536 ; 0x10000
|
|
800aba8: 687b ldr r3, [r7, #4]
|
|
800abaa: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800abac: 687b ldr r3, [r7, #4]
|
|
800abae: 681b ldr r3, [r3, #0]
|
|
800abb0: 430a orrs r2, r1
|
|
800abb2: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
800abb4: 687b ldr r3, [r7, #4]
|
|
800abb6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800abb8: f003 0304 and.w r3, r3, #4
|
|
800abbc: 2b00 cmp r3, #0
|
|
800abbe: d00a beq.n 800abd6 <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
800abc0: 687b ldr r3, [r7, #4]
|
|
800abc2: 681b ldr r3, [r3, #0]
|
|
800abc4: 685b ldr r3, [r3, #4]
|
|
800abc6: f423 2180 bic.w r1, r3, #262144 ; 0x40000
|
|
800abca: 687b ldr r3, [r7, #4]
|
|
800abcc: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
800abce: 687b ldr r3, [r7, #4]
|
|
800abd0: 681b ldr r3, [r3, #0]
|
|
800abd2: 430a orrs r2, r1
|
|
800abd4: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
800abd6: 687b ldr r3, [r7, #4]
|
|
800abd8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800abda: f003 0308 and.w r3, r3, #8
|
|
800abde: 2b00 cmp r3, #0
|
|
800abe0: d00a beq.n 800abf8 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
800abe2: 687b ldr r3, [r7, #4]
|
|
800abe4: 681b ldr r3, [r3, #0]
|
|
800abe6: 685b ldr r3, [r3, #4]
|
|
800abe8: f423 4100 bic.w r1, r3, #32768 ; 0x8000
|
|
800abec: 687b ldr r3, [r7, #4]
|
|
800abee: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
800abf0: 687b ldr r3, [r7, #4]
|
|
800abf2: 681b ldr r3, [r3, #0]
|
|
800abf4: 430a orrs r2, r1
|
|
800abf6: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
800abf8: 687b ldr r3, [r7, #4]
|
|
800abfa: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800abfc: f003 0310 and.w r3, r3, #16
|
|
800ac00: 2b00 cmp r3, #0
|
|
800ac02: d00a beq.n 800ac1a <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
800ac04: 687b ldr r3, [r7, #4]
|
|
800ac06: 681b ldr r3, [r3, #0]
|
|
800ac08: 689b ldr r3, [r3, #8]
|
|
800ac0a: f423 5180 bic.w r1, r3, #4096 ; 0x1000
|
|
800ac0e: 687b ldr r3, [r7, #4]
|
|
800ac10: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
800ac12: 687b ldr r3, [r7, #4]
|
|
800ac14: 681b ldr r3, [r3, #0]
|
|
800ac16: 430a orrs r2, r1
|
|
800ac18: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
800ac1a: 687b ldr r3, [r7, #4]
|
|
800ac1c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800ac1e: f003 0320 and.w r3, r3, #32
|
|
800ac22: 2b00 cmp r3, #0
|
|
800ac24: d00a beq.n 800ac3c <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
800ac26: 687b ldr r3, [r7, #4]
|
|
800ac28: 681b ldr r3, [r3, #0]
|
|
800ac2a: 689b ldr r3, [r3, #8]
|
|
800ac2c: f423 5100 bic.w r1, r3, #8192 ; 0x2000
|
|
800ac30: 687b ldr r3, [r7, #4]
|
|
800ac32: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
800ac34: 687b ldr r3, [r7, #4]
|
|
800ac36: 681b ldr r3, [r3, #0]
|
|
800ac38: 430a orrs r2, r1
|
|
800ac3a: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
800ac3c: 687b ldr r3, [r7, #4]
|
|
800ac3e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800ac40: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800ac44: 2b00 cmp r3, #0
|
|
800ac46: d01a beq.n 800ac7e <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
800ac48: 687b ldr r3, [r7, #4]
|
|
800ac4a: 681b ldr r3, [r3, #0]
|
|
800ac4c: 685b ldr r3, [r3, #4]
|
|
800ac4e: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
|
|
800ac52: 687b ldr r3, [r7, #4]
|
|
800ac54: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
800ac56: 687b ldr r3, [r7, #4]
|
|
800ac58: 681b ldr r3, [r3, #0]
|
|
800ac5a: 430a orrs r2, r1
|
|
800ac5c: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
800ac5e: 687b ldr r3, [r7, #4]
|
|
800ac60: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800ac62: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
|
800ac66: d10a bne.n 800ac7e <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
800ac68: 687b ldr r3, [r7, #4]
|
|
800ac6a: 681b ldr r3, [r3, #0]
|
|
800ac6c: 685b ldr r3, [r3, #4]
|
|
800ac6e: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
|
|
800ac72: 687b ldr r3, [r7, #4]
|
|
800ac74: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
800ac76: 687b ldr r3, [r7, #4]
|
|
800ac78: 681b ldr r3, [r3, #0]
|
|
800ac7a: 430a orrs r2, r1
|
|
800ac7c: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
800ac7e: 687b ldr r3, [r7, #4]
|
|
800ac80: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800ac82: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800ac86: 2b00 cmp r3, #0
|
|
800ac88: d00a beq.n 800aca0 <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
800ac8a: 687b ldr r3, [r7, #4]
|
|
800ac8c: 681b ldr r3, [r3, #0]
|
|
800ac8e: 685b ldr r3, [r3, #4]
|
|
800ac90: f423 2100 bic.w r1, r3, #524288 ; 0x80000
|
|
800ac94: 687b ldr r3, [r7, #4]
|
|
800ac96: 6c9a ldr r2, [r3, #72] ; 0x48
|
|
800ac98: 687b ldr r3, [r7, #4]
|
|
800ac9a: 681b ldr r3, [r3, #0]
|
|
800ac9c: 430a orrs r2, r1
|
|
800ac9e: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
800aca0: bf00 nop
|
|
800aca2: 370c adds r7, #12
|
|
800aca4: 46bd mov sp, r7
|
|
800aca6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800acaa: 4770 bx lr
|
|
|
|
0800acac <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
800acac: b580 push {r7, lr}
|
|
800acae: b086 sub sp, #24
|
|
800acb0: af02 add r7, sp, #8
|
|
800acb2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800acb4: 687b ldr r3, [r7, #4]
|
|
800acb6: 2200 movs r2, #0
|
|
800acb8: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
800acbc: f7f9 fea5 bl 8004a0a <HAL_GetTick>
|
|
800acc0: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
800acc2: 687b ldr r3, [r7, #4]
|
|
800acc4: 681b ldr r3, [r3, #0]
|
|
800acc6: 681b ldr r3, [r3, #0]
|
|
800acc8: f003 0308 and.w r3, r3, #8
|
|
800accc: 2b08 cmp r3, #8
|
|
800acce: d10e bne.n 800acee <UART_CheckIdleState+0x42>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
800acd0: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
|
|
800acd4: 9300 str r3, [sp, #0]
|
|
800acd6: 68fb ldr r3, [r7, #12]
|
|
800acd8: 2200 movs r2, #0
|
|
800acda: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
|
800acde: 6878 ldr r0, [r7, #4]
|
|
800ace0: f000 f82d bl 800ad3e <UART_WaitOnFlagUntilTimeout>
|
|
800ace4: 4603 mov r3, r0
|
|
800ace6: 2b00 cmp r3, #0
|
|
800ace8: d001 beq.n 800acee <UART_CheckIdleState+0x42>
|
|
{
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
800acea: 2303 movs r3, #3
|
|
800acec: e023 b.n 800ad36 <UART_CheckIdleState+0x8a>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
800acee: 687b ldr r3, [r7, #4]
|
|
800acf0: 681b ldr r3, [r3, #0]
|
|
800acf2: 681b ldr r3, [r3, #0]
|
|
800acf4: f003 0304 and.w r3, r3, #4
|
|
800acf8: 2b04 cmp r3, #4
|
|
800acfa: d10e bne.n 800ad1a <UART_CheckIdleState+0x6e>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
800acfc: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
|
|
800ad00: 9300 str r3, [sp, #0]
|
|
800ad02: 68fb ldr r3, [r7, #12]
|
|
800ad04: 2200 movs r2, #0
|
|
800ad06: f44f 0180 mov.w r1, #4194304 ; 0x400000
|
|
800ad0a: 6878 ldr r0, [r7, #4]
|
|
800ad0c: f000 f817 bl 800ad3e <UART_WaitOnFlagUntilTimeout>
|
|
800ad10: 4603 mov r3, r0
|
|
800ad12: 2b00 cmp r3, #0
|
|
800ad14: d001 beq.n 800ad1a <UART_CheckIdleState+0x6e>
|
|
{
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
800ad16: 2303 movs r3, #3
|
|
800ad18: e00d b.n 800ad36 <UART_CheckIdleState+0x8a>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800ad1a: 687b ldr r3, [r7, #4]
|
|
800ad1c: 2220 movs r2, #32
|
|
800ad1e: 679a str r2, [r3, #120] ; 0x78
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800ad20: 687b ldr r3, [r7, #4]
|
|
800ad22: 2220 movs r2, #32
|
|
800ad24: 67da str r2, [r3, #124] ; 0x7c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800ad26: 687b ldr r3, [r7, #4]
|
|
800ad28: 2200 movs r2, #0
|
|
800ad2a: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800ad2c: 687b ldr r3, [r7, #4]
|
|
800ad2e: 2200 movs r2, #0
|
|
800ad30: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
return HAL_OK;
|
|
800ad34: 2300 movs r3, #0
|
|
}
|
|
800ad36: 4618 mov r0, r3
|
|
800ad38: 3710 adds r7, #16
|
|
800ad3a: 46bd mov sp, r7
|
|
800ad3c: bd80 pop {r7, pc}
|
|
|
|
0800ad3e <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
800ad3e: b580 push {r7, lr}
|
|
800ad40: b084 sub sp, #16
|
|
800ad42: af00 add r7, sp, #0
|
|
800ad44: 60f8 str r0, [r7, #12]
|
|
800ad46: 60b9 str r1, [r7, #8]
|
|
800ad48: 603b str r3, [r7, #0]
|
|
800ad4a: 4613 mov r3, r2
|
|
800ad4c: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
800ad4e: e05e b.n 800ae0e <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800ad50: 69bb ldr r3, [r7, #24]
|
|
800ad52: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
|
|
800ad56: d05a beq.n 800ae0e <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
800ad58: f7f9 fe57 bl 8004a0a <HAL_GetTick>
|
|
800ad5c: 4602 mov r2, r0
|
|
800ad5e: 683b ldr r3, [r7, #0]
|
|
800ad60: 1ad3 subs r3, r2, r3
|
|
800ad62: 69ba ldr r2, [r7, #24]
|
|
800ad64: 429a cmp r2, r3
|
|
800ad66: d302 bcc.n 800ad6e <UART_WaitOnFlagUntilTimeout+0x30>
|
|
800ad68: 69bb ldr r3, [r7, #24]
|
|
800ad6a: 2b00 cmp r3, #0
|
|
800ad6c: d11b bne.n 800ada6 <UART_WaitOnFlagUntilTimeout+0x68>
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
|
|
#else
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
800ad6e: 68fb ldr r3, [r7, #12]
|
|
800ad70: 681b ldr r3, [r3, #0]
|
|
800ad72: 681a ldr r2, [r3, #0]
|
|
800ad74: 68fb ldr r3, [r7, #12]
|
|
800ad76: 681b ldr r3, [r3, #0]
|
|
800ad78: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
|
|
800ad7c: 601a str r2, [r3, #0]
|
|
#endif /* USART_CR1_FIFOEN */
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800ad7e: 68fb ldr r3, [r7, #12]
|
|
800ad80: 681b ldr r3, [r3, #0]
|
|
800ad82: 689a ldr r2, [r3, #8]
|
|
800ad84: 68fb ldr r3, [r7, #12]
|
|
800ad86: 681b ldr r3, [r3, #0]
|
|
800ad88: f022 0201 bic.w r2, r2, #1
|
|
800ad8c: 609a str r2, [r3, #8]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800ad8e: 68fb ldr r3, [r7, #12]
|
|
800ad90: 2220 movs r2, #32
|
|
800ad92: 679a str r2, [r3, #120] ; 0x78
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800ad94: 68fb ldr r3, [r7, #12]
|
|
800ad96: 2220 movs r2, #32
|
|
800ad98: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800ad9a: 68fb ldr r3, [r7, #12]
|
|
800ad9c: 2200 movs r2, #0
|
|
800ad9e: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
return HAL_TIMEOUT;
|
|
800ada2: 2303 movs r3, #3
|
|
800ada4: e043 b.n 800ae2e <UART_WaitOnFlagUntilTimeout+0xf0>
|
|
}
|
|
|
|
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
|
800ada6: 68fb ldr r3, [r7, #12]
|
|
800ada8: 681b ldr r3, [r3, #0]
|
|
800adaa: 681b ldr r3, [r3, #0]
|
|
800adac: f003 0304 and.w r3, r3, #4
|
|
800adb0: 2b00 cmp r3, #0
|
|
800adb2: d02c beq.n 800ae0e <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
800adb4: 68fb ldr r3, [r7, #12]
|
|
800adb6: 681b ldr r3, [r3, #0]
|
|
800adb8: 69db ldr r3, [r3, #28]
|
|
800adba: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
800adbe: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
800adc2: d124 bne.n 800ae0e <UART_WaitOnFlagUntilTimeout+0xd0>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
800adc4: 68fb ldr r3, [r7, #12]
|
|
800adc6: 681b ldr r3, [r3, #0]
|
|
800adc8: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
800adcc: 621a str r2, [r3, #32]
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
|
|
#else
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
800adce: 68fb ldr r3, [r7, #12]
|
|
800add0: 681b ldr r3, [r3, #0]
|
|
800add2: 681a ldr r2, [r3, #0]
|
|
800add4: 68fb ldr r3, [r7, #12]
|
|
800add6: 681b ldr r3, [r3, #0]
|
|
800add8: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
|
|
800addc: 601a str r2, [r3, #0]
|
|
#endif
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800adde: 68fb ldr r3, [r7, #12]
|
|
800ade0: 681b ldr r3, [r3, #0]
|
|
800ade2: 689a ldr r2, [r3, #8]
|
|
800ade4: 68fb ldr r3, [r7, #12]
|
|
800ade6: 681b ldr r3, [r3, #0]
|
|
800ade8: f022 0201 bic.w r2, r2, #1
|
|
800adec: 609a str r2, [r3, #8]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800adee: 68fb ldr r3, [r7, #12]
|
|
800adf0: 2220 movs r2, #32
|
|
800adf2: 679a str r2, [r3, #120] ; 0x78
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800adf4: 68fb ldr r3, [r7, #12]
|
|
800adf6: 2220 movs r2, #32
|
|
800adf8: 67da str r2, [r3, #124] ; 0x7c
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
800adfa: 68fb ldr r3, [r7, #12]
|
|
800adfc: 2220 movs r2, #32
|
|
800adfe: f8c3 2080 str.w r2, [r3, #128] ; 0x80
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
800ae02: 68fb ldr r3, [r7, #12]
|
|
800ae04: 2200 movs r2, #0
|
|
800ae06: f883 2074 strb.w r2, [r3, #116] ; 0x74
|
|
|
|
return HAL_TIMEOUT;
|
|
800ae0a: 2303 movs r3, #3
|
|
800ae0c: e00f b.n 800ae2e <UART_WaitOnFlagUntilTimeout+0xf0>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
800ae0e: 68fb ldr r3, [r7, #12]
|
|
800ae10: 681b ldr r3, [r3, #0]
|
|
800ae12: 69da ldr r2, [r3, #28]
|
|
800ae14: 68bb ldr r3, [r7, #8]
|
|
800ae16: 4013 ands r3, r2
|
|
800ae18: 68ba ldr r2, [r7, #8]
|
|
800ae1a: 429a cmp r2, r3
|
|
800ae1c: bf0c ite eq
|
|
800ae1e: 2301 moveq r3, #1
|
|
800ae20: 2300 movne r3, #0
|
|
800ae22: b2db uxtb r3, r3
|
|
800ae24: 461a mov r2, r3
|
|
800ae26: 79fb ldrb r3, [r7, #7]
|
|
800ae28: 429a cmp r2, r3
|
|
800ae2a: d091 beq.n 800ad50 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800ae2c: 2300 movs r3, #0
|
|
}
|
|
800ae2e: 4618 mov r0, r3
|
|
800ae30: 3710 adds r7, #16
|
|
800ae32: 46bd mov sp, r7
|
|
800ae34: bd80 pop {r7, pc}
|
|
|
|
0800ae36 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
800ae36: b480 push {r7}
|
|
800ae38: b083 sub sp, #12
|
|
800ae3a: af00 add r7, sp, #0
|
|
800ae3c: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
800ae3e: 687b ldr r3, [r7, #4]
|
|
800ae40: 681b ldr r3, [r3, #0]
|
|
800ae42: 681a ldr r2, [r3, #0]
|
|
800ae44: 687b ldr r3, [r7, #4]
|
|
800ae46: 681b ldr r3, [r3, #0]
|
|
800ae48: f422 7290 bic.w r2, r2, #288 ; 0x120
|
|
800ae4c: 601a str r2, [r3, #0]
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800ae4e: 687b ldr r3, [r7, #4]
|
|
800ae50: 681b ldr r3, [r3, #0]
|
|
800ae52: 689a ldr r2, [r3, #8]
|
|
800ae54: 687b ldr r3, [r7, #4]
|
|
800ae56: 681b ldr r3, [r3, #0]
|
|
800ae58: f022 0201 bic.w r2, r2, #1
|
|
800ae5c: 609a str r2, [r3, #8]
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800ae5e: 687b ldr r3, [r7, #4]
|
|
800ae60: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
800ae62: 2b01 cmp r3, #1
|
|
800ae64: d107 bne.n 800ae76 <UART_EndRxTransfer+0x40>
|
|
{
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800ae66: 687b ldr r3, [r7, #4]
|
|
800ae68: 681b ldr r3, [r3, #0]
|
|
800ae6a: 681a ldr r2, [r3, #0]
|
|
800ae6c: 687b ldr r3, [r7, #4]
|
|
800ae6e: 681b ldr r3, [r3, #0]
|
|
800ae70: f022 0210 bic.w r2, r2, #16
|
|
800ae74: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800ae76: 687b ldr r3, [r7, #4]
|
|
800ae78: 2220 movs r2, #32
|
|
800ae7a: 67da str r2, [r3, #124] ; 0x7c
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
800ae7c: 687b ldr r3, [r7, #4]
|
|
800ae7e: 2200 movs r2, #0
|
|
800ae80: 661a str r2, [r3, #96] ; 0x60
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
800ae82: 687b ldr r3, [r7, #4]
|
|
800ae84: 2200 movs r2, #0
|
|
800ae86: 665a str r2, [r3, #100] ; 0x64
|
|
}
|
|
800ae88: bf00 nop
|
|
800ae8a: 370c adds r7, #12
|
|
800ae8c: 46bd mov sp, r7
|
|
800ae8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ae92: 4770 bx lr
|
|
|
|
0800ae94 <UART_DMAAbortOnError>:
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800ae94: b580 push {r7, lr}
|
|
800ae96: b084 sub sp, #16
|
|
800ae98: af00 add r7, sp, #0
|
|
800ae9a: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
800ae9c: 687b ldr r3, [r7, #4]
|
|
800ae9e: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800aea0: 60fb str r3, [r7, #12]
|
|
huart->RxXferCount = 0U;
|
|
800aea2: 68fb ldr r3, [r7, #12]
|
|
800aea4: 2200 movs r2, #0
|
|
800aea6: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
|
|
huart->TxXferCount = 0U;
|
|
800aeaa: 68fb ldr r3, [r7, #12]
|
|
800aeac: 2200 movs r2, #0
|
|
800aeae: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800aeb2: 68f8 ldr r0, [r7, #12]
|
|
800aeb4: f7ff fb98 bl 800a5e8 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800aeb8: bf00 nop
|
|
800aeba: 3710 adds r7, #16
|
|
800aebc: 46bd mov sp, r7
|
|
800aebe: bd80 pop {r7, pc}
|
|
|
|
0800aec0 <UART_EndTransmit_IT>:
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
800aec0: b580 push {r7, lr}
|
|
800aec2: b082 sub sp, #8
|
|
800aec4: af00 add r7, sp, #0
|
|
800aec6: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
800aec8: 687b ldr r3, [r7, #4]
|
|
800aeca: 681b ldr r3, [r3, #0]
|
|
800aecc: 681a ldr r2, [r3, #0]
|
|
800aece: 687b ldr r3, [r7, #4]
|
|
800aed0: 681b ldr r3, [r3, #0]
|
|
800aed2: f022 0240 bic.w r2, r2, #64 ; 0x40
|
|
800aed6: 601a str r2, [r3, #0]
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800aed8: 687b ldr r3, [r7, #4]
|
|
800aeda: 2220 movs r2, #32
|
|
800aedc: 679a str r2, [r3, #120] ; 0x78
|
|
|
|
/* Cleat TxISR function pointer */
|
|
huart->TxISR = NULL;
|
|
800aede: 687b ldr r3, [r7, #4]
|
|
800aee0: 2200 movs r2, #0
|
|
800aee2: 669a str r2, [r3, #104] ; 0x68
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
800aee4: 6878 ldr r0, [r7, #4]
|
|
800aee6: f7ff fb75 bl 800a5d4 <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800aeea: bf00 nop
|
|
800aeec: 3708 adds r7, #8
|
|
800aeee: 46bd mov sp, r7
|
|
800aef0: bd80 pop {r7, pc}
|
|
|
|
0800aef2 <HAL_UARTEx_WakeupCallback>:
|
|
* @brief UART wakeup from Stop mode callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800aef2: b480 push {r7}
|
|
800aef4: b083 sub sp, #12
|
|
800aef6: af00 add r7, sp, #0
|
|
800aef8: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
800aefa: bf00 nop
|
|
800aefc: 370c adds r7, #12
|
|
800aefe: 46bd mov sp, r7
|
|
800af00: f85d 7b04 ldr.w r7, [sp], #4
|
|
800af04: 4770 bx lr
|
|
...
|
|
|
|
0800af08 <__errno>:
|
|
800af08: 4b01 ldr r3, [pc, #4] ; (800af10 <__errno+0x8>)
|
|
800af0a: 6818 ldr r0, [r3, #0]
|
|
800af0c: 4770 bx lr
|
|
800af0e: bf00 nop
|
|
800af10: 20000278 .word 0x20000278
|
|
|
|
0800af14 <__libc_init_array>:
|
|
800af14: b570 push {r4, r5, r6, lr}
|
|
800af16: 4d0d ldr r5, [pc, #52] ; (800af4c <__libc_init_array+0x38>)
|
|
800af18: 4c0d ldr r4, [pc, #52] ; (800af50 <__libc_init_array+0x3c>)
|
|
800af1a: 1b64 subs r4, r4, r5
|
|
800af1c: 10a4 asrs r4, r4, #2
|
|
800af1e: 2600 movs r6, #0
|
|
800af20: 42a6 cmp r6, r4
|
|
800af22: d109 bne.n 800af38 <__libc_init_array+0x24>
|
|
800af24: 4d0b ldr r5, [pc, #44] ; (800af54 <__libc_init_array+0x40>)
|
|
800af26: 4c0c ldr r4, [pc, #48] ; (800af58 <__libc_init_array+0x44>)
|
|
800af28: f003 f96a bl 800e200 <_init>
|
|
800af2c: 1b64 subs r4, r4, r5
|
|
800af2e: 10a4 asrs r4, r4, #2
|
|
800af30: 2600 movs r6, #0
|
|
800af32: 42a6 cmp r6, r4
|
|
800af34: d105 bne.n 800af42 <__libc_init_array+0x2e>
|
|
800af36: bd70 pop {r4, r5, r6, pc}
|
|
800af38: f855 3b04 ldr.w r3, [r5], #4
|
|
800af3c: 4798 blx r3
|
|
800af3e: 3601 adds r6, #1
|
|
800af40: e7ee b.n 800af20 <__libc_init_array+0xc>
|
|
800af42: f855 3b04 ldr.w r3, [r5], #4
|
|
800af46: 4798 blx r3
|
|
800af48: 3601 adds r6, #1
|
|
800af4a: e7f2 b.n 800af32 <__libc_init_array+0x1e>
|
|
800af4c: 0800e7e0 .word 0x0800e7e0
|
|
800af50: 0800e7e0 .word 0x0800e7e0
|
|
800af54: 0800e7e0 .word 0x0800e7e0
|
|
800af58: 0800e7e4 .word 0x0800e7e4
|
|
|
|
0800af5c <memcpy>:
|
|
800af5c: 440a add r2, r1
|
|
800af5e: 4291 cmp r1, r2
|
|
800af60: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
|
|
800af64: d100 bne.n 800af68 <memcpy+0xc>
|
|
800af66: 4770 bx lr
|
|
800af68: b510 push {r4, lr}
|
|
800af6a: f811 4b01 ldrb.w r4, [r1], #1
|
|
800af6e: f803 4f01 strb.w r4, [r3, #1]!
|
|
800af72: 4291 cmp r1, r2
|
|
800af74: d1f9 bne.n 800af6a <memcpy+0xe>
|
|
800af76: bd10 pop {r4, pc}
|
|
|
|
0800af78 <memset>:
|
|
800af78: 4402 add r2, r0
|
|
800af7a: 4603 mov r3, r0
|
|
800af7c: 4293 cmp r3, r2
|
|
800af7e: d100 bne.n 800af82 <memset+0xa>
|
|
800af80: 4770 bx lr
|
|
800af82: f803 1b01 strb.w r1, [r3], #1
|
|
800af86: e7f9 b.n 800af7c <memset+0x4>
|
|
|
|
0800af88 <__cvt>:
|
|
800af88: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800af8c: ec55 4b10 vmov r4, r5, d0
|
|
800af90: 2d00 cmp r5, #0
|
|
800af92: 460e mov r6, r1
|
|
800af94: 4619 mov r1, r3
|
|
800af96: 462b mov r3, r5
|
|
800af98: bfbb ittet lt
|
|
800af9a: f105 4300 addlt.w r3, r5, #2147483648 ; 0x80000000
|
|
800af9e: 461d movlt r5, r3
|
|
800afa0: 2300 movge r3, #0
|
|
800afa2: 232d movlt r3, #45 ; 0x2d
|
|
800afa4: 700b strb r3, [r1, #0]
|
|
800afa6: 9b0d ldr r3, [sp, #52] ; 0x34
|
|
800afa8: f8dd a030 ldr.w sl, [sp, #48] ; 0x30
|
|
800afac: 4691 mov r9, r2
|
|
800afae: f023 0820 bic.w r8, r3, #32
|
|
800afb2: bfbc itt lt
|
|
800afb4: 4622 movlt r2, r4
|
|
800afb6: 4614 movlt r4, r2
|
|
800afb8: f1b8 0f46 cmp.w r8, #70 ; 0x46
|
|
800afbc: d005 beq.n 800afca <__cvt+0x42>
|
|
800afbe: f1b8 0f45 cmp.w r8, #69 ; 0x45
|
|
800afc2: d100 bne.n 800afc6 <__cvt+0x3e>
|
|
800afc4: 3601 adds r6, #1
|
|
800afc6: 2102 movs r1, #2
|
|
800afc8: e000 b.n 800afcc <__cvt+0x44>
|
|
800afca: 2103 movs r1, #3
|
|
800afcc: ab03 add r3, sp, #12
|
|
800afce: 9301 str r3, [sp, #4]
|
|
800afd0: ab02 add r3, sp, #8
|
|
800afd2: 9300 str r3, [sp, #0]
|
|
800afd4: ec45 4b10 vmov d0, r4, r5
|
|
800afd8: 4653 mov r3, sl
|
|
800afda: 4632 mov r2, r6
|
|
800afdc: f000 fe70 bl 800bcc0 <_dtoa_r>
|
|
800afe0: f1b8 0f47 cmp.w r8, #71 ; 0x47
|
|
800afe4: 4607 mov r7, r0
|
|
800afe6: d102 bne.n 800afee <__cvt+0x66>
|
|
800afe8: f019 0f01 tst.w r9, #1
|
|
800afec: d022 beq.n 800b034 <__cvt+0xac>
|
|
800afee: f1b8 0f46 cmp.w r8, #70 ; 0x46
|
|
800aff2: eb07 0906 add.w r9, r7, r6
|
|
800aff6: d110 bne.n 800b01a <__cvt+0x92>
|
|
800aff8: 783b ldrb r3, [r7, #0]
|
|
800affa: 2b30 cmp r3, #48 ; 0x30
|
|
800affc: d10a bne.n 800b014 <__cvt+0x8c>
|
|
800affe: 2200 movs r2, #0
|
|
800b000: 2300 movs r3, #0
|
|
800b002: 4620 mov r0, r4
|
|
800b004: 4629 mov r1, r5
|
|
800b006: f7f5 fd5f bl 8000ac8 <__aeabi_dcmpeq>
|
|
800b00a: b918 cbnz r0, 800b014 <__cvt+0x8c>
|
|
800b00c: f1c6 0601 rsb r6, r6, #1
|
|
800b010: f8ca 6000 str.w r6, [sl]
|
|
800b014: f8da 3000 ldr.w r3, [sl]
|
|
800b018: 4499 add r9, r3
|
|
800b01a: 2200 movs r2, #0
|
|
800b01c: 2300 movs r3, #0
|
|
800b01e: 4620 mov r0, r4
|
|
800b020: 4629 mov r1, r5
|
|
800b022: f7f5 fd51 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800b026: b108 cbz r0, 800b02c <__cvt+0xa4>
|
|
800b028: f8cd 900c str.w r9, [sp, #12]
|
|
800b02c: 2230 movs r2, #48 ; 0x30
|
|
800b02e: 9b03 ldr r3, [sp, #12]
|
|
800b030: 454b cmp r3, r9
|
|
800b032: d307 bcc.n 800b044 <__cvt+0xbc>
|
|
800b034: 9b03 ldr r3, [sp, #12]
|
|
800b036: 9a0e ldr r2, [sp, #56] ; 0x38
|
|
800b038: 1bdb subs r3, r3, r7
|
|
800b03a: 4638 mov r0, r7
|
|
800b03c: 6013 str r3, [r2, #0]
|
|
800b03e: b004 add sp, #16
|
|
800b040: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800b044: 1c59 adds r1, r3, #1
|
|
800b046: 9103 str r1, [sp, #12]
|
|
800b048: 701a strb r2, [r3, #0]
|
|
800b04a: e7f0 b.n 800b02e <__cvt+0xa6>
|
|
|
|
0800b04c <__exponent>:
|
|
800b04c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
800b04e: 4603 mov r3, r0
|
|
800b050: 2900 cmp r1, #0
|
|
800b052: bfb8 it lt
|
|
800b054: 4249 neglt r1, r1
|
|
800b056: f803 2b02 strb.w r2, [r3], #2
|
|
800b05a: bfb4 ite lt
|
|
800b05c: 222d movlt r2, #45 ; 0x2d
|
|
800b05e: 222b movge r2, #43 ; 0x2b
|
|
800b060: 2909 cmp r1, #9
|
|
800b062: 7042 strb r2, [r0, #1]
|
|
800b064: dd2a ble.n 800b0bc <__exponent+0x70>
|
|
800b066: f10d 0407 add.w r4, sp, #7
|
|
800b06a: 46a4 mov ip, r4
|
|
800b06c: 270a movs r7, #10
|
|
800b06e: 46a6 mov lr, r4
|
|
800b070: 460a mov r2, r1
|
|
800b072: fb91 f6f7 sdiv r6, r1, r7
|
|
800b076: fb07 1516 mls r5, r7, r6, r1
|
|
800b07a: 3530 adds r5, #48 ; 0x30
|
|
800b07c: 2a63 cmp r2, #99 ; 0x63
|
|
800b07e: f104 34ff add.w r4, r4, #4294967295 ; 0xffffffff
|
|
800b082: f80e 5c01 strb.w r5, [lr, #-1]
|
|
800b086: 4631 mov r1, r6
|
|
800b088: dcf1 bgt.n 800b06e <__exponent+0x22>
|
|
800b08a: 3130 adds r1, #48 ; 0x30
|
|
800b08c: f1ae 0502 sub.w r5, lr, #2
|
|
800b090: f804 1c01 strb.w r1, [r4, #-1]
|
|
800b094: 1c44 adds r4, r0, #1
|
|
800b096: 4629 mov r1, r5
|
|
800b098: 4561 cmp r1, ip
|
|
800b09a: d30a bcc.n 800b0b2 <__exponent+0x66>
|
|
800b09c: f10d 0209 add.w r2, sp, #9
|
|
800b0a0: eba2 020e sub.w r2, r2, lr
|
|
800b0a4: 4565 cmp r5, ip
|
|
800b0a6: bf88 it hi
|
|
800b0a8: 2200 movhi r2, #0
|
|
800b0aa: 4413 add r3, r2
|
|
800b0ac: 1a18 subs r0, r3, r0
|
|
800b0ae: b003 add sp, #12
|
|
800b0b0: bdf0 pop {r4, r5, r6, r7, pc}
|
|
800b0b2: f811 2b01 ldrb.w r2, [r1], #1
|
|
800b0b6: f804 2f01 strb.w r2, [r4, #1]!
|
|
800b0ba: e7ed b.n 800b098 <__exponent+0x4c>
|
|
800b0bc: 2330 movs r3, #48 ; 0x30
|
|
800b0be: 3130 adds r1, #48 ; 0x30
|
|
800b0c0: 7083 strb r3, [r0, #2]
|
|
800b0c2: 70c1 strb r1, [r0, #3]
|
|
800b0c4: 1d03 adds r3, r0, #4
|
|
800b0c6: e7f1 b.n 800b0ac <__exponent+0x60>
|
|
|
|
0800b0c8 <_printf_float>:
|
|
800b0c8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800b0cc: ed2d 8b02 vpush {d8}
|
|
800b0d0: b08d sub sp, #52 ; 0x34
|
|
800b0d2: 460c mov r4, r1
|
|
800b0d4: f8dd 8060 ldr.w r8, [sp, #96] ; 0x60
|
|
800b0d8: 4616 mov r6, r2
|
|
800b0da: 461f mov r7, r3
|
|
800b0dc: 4605 mov r5, r0
|
|
800b0de: f001 fda5 bl 800cc2c <_localeconv_r>
|
|
800b0e2: f8d0 a000 ldr.w sl, [r0]
|
|
800b0e6: 4650 mov r0, sl
|
|
800b0e8: f7f5 f872 bl 80001d0 <strlen>
|
|
800b0ec: 2300 movs r3, #0
|
|
800b0ee: 930a str r3, [sp, #40] ; 0x28
|
|
800b0f0: 6823 ldr r3, [r4, #0]
|
|
800b0f2: 9305 str r3, [sp, #20]
|
|
800b0f4: f8d8 3000 ldr.w r3, [r8]
|
|
800b0f8: f894 b018 ldrb.w fp, [r4, #24]
|
|
800b0fc: 3307 adds r3, #7
|
|
800b0fe: f023 0307 bic.w r3, r3, #7
|
|
800b102: f103 0208 add.w r2, r3, #8
|
|
800b106: f8c8 2000 str.w r2, [r8]
|
|
800b10a: e9d3 2300 ldrd r2, r3, [r3]
|
|
800b10e: e9c4 2312 strd r2, r3, [r4, #72] ; 0x48
|
|
800b112: e9d4 8912 ldrd r8, r9, [r4, #72] ; 0x48
|
|
800b116: f029 4300 bic.w r3, r9, #2147483648 ; 0x80000000
|
|
800b11a: 9307 str r3, [sp, #28]
|
|
800b11c: f8cd 8018 str.w r8, [sp, #24]
|
|
800b120: ee08 0a10 vmov s16, r0
|
|
800b124: 4b9f ldr r3, [pc, #636] ; (800b3a4 <_printf_float+0x2dc>)
|
|
800b126: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
800b12a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
800b12e: f7f5 fcfd bl 8000b2c <__aeabi_dcmpun>
|
|
800b132: bb88 cbnz r0, 800b198 <_printf_float+0xd0>
|
|
800b134: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
800b138: 4b9a ldr r3, [pc, #616] ; (800b3a4 <_printf_float+0x2dc>)
|
|
800b13a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
800b13e: f7f5 fcd7 bl 8000af0 <__aeabi_dcmple>
|
|
800b142: bb48 cbnz r0, 800b198 <_printf_float+0xd0>
|
|
800b144: 2200 movs r2, #0
|
|
800b146: 2300 movs r3, #0
|
|
800b148: 4640 mov r0, r8
|
|
800b14a: 4649 mov r1, r9
|
|
800b14c: f7f5 fcc6 bl 8000adc <__aeabi_dcmplt>
|
|
800b150: b110 cbz r0, 800b158 <_printf_float+0x90>
|
|
800b152: 232d movs r3, #45 ; 0x2d
|
|
800b154: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
800b158: 4b93 ldr r3, [pc, #588] ; (800b3a8 <_printf_float+0x2e0>)
|
|
800b15a: 4894 ldr r0, [pc, #592] ; (800b3ac <_printf_float+0x2e4>)
|
|
800b15c: f1bb 0f47 cmp.w fp, #71 ; 0x47
|
|
800b160: bf94 ite ls
|
|
800b162: 4698 movls r8, r3
|
|
800b164: 4680 movhi r8, r0
|
|
800b166: 2303 movs r3, #3
|
|
800b168: 6123 str r3, [r4, #16]
|
|
800b16a: 9b05 ldr r3, [sp, #20]
|
|
800b16c: f023 0204 bic.w r2, r3, #4
|
|
800b170: 6022 str r2, [r4, #0]
|
|
800b172: f04f 0900 mov.w r9, #0
|
|
800b176: 9700 str r7, [sp, #0]
|
|
800b178: 4633 mov r3, r6
|
|
800b17a: aa0b add r2, sp, #44 ; 0x2c
|
|
800b17c: 4621 mov r1, r4
|
|
800b17e: 4628 mov r0, r5
|
|
800b180: f000 f9d8 bl 800b534 <_printf_common>
|
|
800b184: 3001 adds r0, #1
|
|
800b186: f040 8090 bne.w 800b2aa <_printf_float+0x1e2>
|
|
800b18a: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800b18e: b00d add sp, #52 ; 0x34
|
|
800b190: ecbd 8b02 vpop {d8}
|
|
800b194: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800b198: 4642 mov r2, r8
|
|
800b19a: 464b mov r3, r9
|
|
800b19c: 4640 mov r0, r8
|
|
800b19e: 4649 mov r1, r9
|
|
800b1a0: f7f5 fcc4 bl 8000b2c <__aeabi_dcmpun>
|
|
800b1a4: b140 cbz r0, 800b1b8 <_printf_float+0xf0>
|
|
800b1a6: 464b mov r3, r9
|
|
800b1a8: 2b00 cmp r3, #0
|
|
800b1aa: bfbc itt lt
|
|
800b1ac: 232d movlt r3, #45 ; 0x2d
|
|
800b1ae: f884 3043 strblt.w r3, [r4, #67] ; 0x43
|
|
800b1b2: 487f ldr r0, [pc, #508] ; (800b3b0 <_printf_float+0x2e8>)
|
|
800b1b4: 4b7f ldr r3, [pc, #508] ; (800b3b4 <_printf_float+0x2ec>)
|
|
800b1b6: e7d1 b.n 800b15c <_printf_float+0x94>
|
|
800b1b8: 6863 ldr r3, [r4, #4]
|
|
800b1ba: f00b 02df and.w r2, fp, #223 ; 0xdf
|
|
800b1be: 9206 str r2, [sp, #24]
|
|
800b1c0: 1c5a adds r2, r3, #1
|
|
800b1c2: d13f bne.n 800b244 <_printf_float+0x17c>
|
|
800b1c4: 2306 movs r3, #6
|
|
800b1c6: 6063 str r3, [r4, #4]
|
|
800b1c8: 9b05 ldr r3, [sp, #20]
|
|
800b1ca: 6861 ldr r1, [r4, #4]
|
|
800b1cc: f443 6280 orr.w r2, r3, #1024 ; 0x400
|
|
800b1d0: 2300 movs r3, #0
|
|
800b1d2: 9303 str r3, [sp, #12]
|
|
800b1d4: ab0a add r3, sp, #40 ; 0x28
|
|
800b1d6: e9cd b301 strd fp, r3, [sp, #4]
|
|
800b1da: ab09 add r3, sp, #36 ; 0x24
|
|
800b1dc: ec49 8b10 vmov d0, r8, r9
|
|
800b1e0: 9300 str r3, [sp, #0]
|
|
800b1e2: 6022 str r2, [r4, #0]
|
|
800b1e4: f10d 0323 add.w r3, sp, #35 ; 0x23
|
|
800b1e8: 4628 mov r0, r5
|
|
800b1ea: f7ff fecd bl 800af88 <__cvt>
|
|
800b1ee: 9b06 ldr r3, [sp, #24]
|
|
800b1f0: 9909 ldr r1, [sp, #36] ; 0x24
|
|
800b1f2: 2b47 cmp r3, #71 ; 0x47
|
|
800b1f4: 4680 mov r8, r0
|
|
800b1f6: d108 bne.n 800b20a <_printf_float+0x142>
|
|
800b1f8: 1cc8 adds r0, r1, #3
|
|
800b1fa: db02 blt.n 800b202 <_printf_float+0x13a>
|
|
800b1fc: 6863 ldr r3, [r4, #4]
|
|
800b1fe: 4299 cmp r1, r3
|
|
800b200: dd41 ble.n 800b286 <_printf_float+0x1be>
|
|
800b202: f1ab 0b02 sub.w fp, fp, #2
|
|
800b206: fa5f fb8b uxtb.w fp, fp
|
|
800b20a: f1bb 0f65 cmp.w fp, #101 ; 0x65
|
|
800b20e: d820 bhi.n 800b252 <_printf_float+0x18a>
|
|
800b210: 3901 subs r1, #1
|
|
800b212: 465a mov r2, fp
|
|
800b214: f104 0050 add.w r0, r4, #80 ; 0x50
|
|
800b218: 9109 str r1, [sp, #36] ; 0x24
|
|
800b21a: f7ff ff17 bl 800b04c <__exponent>
|
|
800b21e: 9a0a ldr r2, [sp, #40] ; 0x28
|
|
800b220: 1813 adds r3, r2, r0
|
|
800b222: 2a01 cmp r2, #1
|
|
800b224: 4681 mov r9, r0
|
|
800b226: 6123 str r3, [r4, #16]
|
|
800b228: dc02 bgt.n 800b230 <_printf_float+0x168>
|
|
800b22a: 6822 ldr r2, [r4, #0]
|
|
800b22c: 07d2 lsls r2, r2, #31
|
|
800b22e: d501 bpl.n 800b234 <_printf_float+0x16c>
|
|
800b230: 3301 adds r3, #1
|
|
800b232: 6123 str r3, [r4, #16]
|
|
800b234: f89d 3023 ldrb.w r3, [sp, #35] ; 0x23
|
|
800b238: 2b00 cmp r3, #0
|
|
800b23a: d09c beq.n 800b176 <_printf_float+0xae>
|
|
800b23c: 232d movs r3, #45 ; 0x2d
|
|
800b23e: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
800b242: e798 b.n 800b176 <_printf_float+0xae>
|
|
800b244: 9a06 ldr r2, [sp, #24]
|
|
800b246: 2a47 cmp r2, #71 ; 0x47
|
|
800b248: d1be bne.n 800b1c8 <_printf_float+0x100>
|
|
800b24a: 2b00 cmp r3, #0
|
|
800b24c: d1bc bne.n 800b1c8 <_printf_float+0x100>
|
|
800b24e: 2301 movs r3, #1
|
|
800b250: e7b9 b.n 800b1c6 <_printf_float+0xfe>
|
|
800b252: f1bb 0f66 cmp.w fp, #102 ; 0x66
|
|
800b256: d118 bne.n 800b28a <_printf_float+0x1c2>
|
|
800b258: 2900 cmp r1, #0
|
|
800b25a: 6863 ldr r3, [r4, #4]
|
|
800b25c: dd0b ble.n 800b276 <_printf_float+0x1ae>
|
|
800b25e: 6121 str r1, [r4, #16]
|
|
800b260: b913 cbnz r3, 800b268 <_printf_float+0x1a0>
|
|
800b262: 6822 ldr r2, [r4, #0]
|
|
800b264: 07d0 lsls r0, r2, #31
|
|
800b266: d502 bpl.n 800b26e <_printf_float+0x1a6>
|
|
800b268: 3301 adds r3, #1
|
|
800b26a: 440b add r3, r1
|
|
800b26c: 6123 str r3, [r4, #16]
|
|
800b26e: 65a1 str r1, [r4, #88] ; 0x58
|
|
800b270: f04f 0900 mov.w r9, #0
|
|
800b274: e7de b.n 800b234 <_printf_float+0x16c>
|
|
800b276: b913 cbnz r3, 800b27e <_printf_float+0x1b6>
|
|
800b278: 6822 ldr r2, [r4, #0]
|
|
800b27a: 07d2 lsls r2, r2, #31
|
|
800b27c: d501 bpl.n 800b282 <_printf_float+0x1ba>
|
|
800b27e: 3302 adds r3, #2
|
|
800b280: e7f4 b.n 800b26c <_printf_float+0x1a4>
|
|
800b282: 2301 movs r3, #1
|
|
800b284: e7f2 b.n 800b26c <_printf_float+0x1a4>
|
|
800b286: f04f 0b67 mov.w fp, #103 ; 0x67
|
|
800b28a: 9b0a ldr r3, [sp, #40] ; 0x28
|
|
800b28c: 4299 cmp r1, r3
|
|
800b28e: db05 blt.n 800b29c <_printf_float+0x1d4>
|
|
800b290: 6823 ldr r3, [r4, #0]
|
|
800b292: 6121 str r1, [r4, #16]
|
|
800b294: 07d8 lsls r0, r3, #31
|
|
800b296: d5ea bpl.n 800b26e <_printf_float+0x1a6>
|
|
800b298: 1c4b adds r3, r1, #1
|
|
800b29a: e7e7 b.n 800b26c <_printf_float+0x1a4>
|
|
800b29c: 2900 cmp r1, #0
|
|
800b29e: bfd4 ite le
|
|
800b2a0: f1c1 0202 rsble r2, r1, #2
|
|
800b2a4: 2201 movgt r2, #1
|
|
800b2a6: 4413 add r3, r2
|
|
800b2a8: e7e0 b.n 800b26c <_printf_float+0x1a4>
|
|
800b2aa: 6823 ldr r3, [r4, #0]
|
|
800b2ac: 055a lsls r2, r3, #21
|
|
800b2ae: d407 bmi.n 800b2c0 <_printf_float+0x1f8>
|
|
800b2b0: 6923 ldr r3, [r4, #16]
|
|
800b2b2: 4642 mov r2, r8
|
|
800b2b4: 4631 mov r1, r6
|
|
800b2b6: 4628 mov r0, r5
|
|
800b2b8: 47b8 blx r7
|
|
800b2ba: 3001 adds r0, #1
|
|
800b2bc: d12c bne.n 800b318 <_printf_float+0x250>
|
|
800b2be: e764 b.n 800b18a <_printf_float+0xc2>
|
|
800b2c0: f1bb 0f65 cmp.w fp, #101 ; 0x65
|
|
800b2c4: f240 80e0 bls.w 800b488 <_printf_float+0x3c0>
|
|
800b2c8: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48
|
|
800b2cc: 2200 movs r2, #0
|
|
800b2ce: 2300 movs r3, #0
|
|
800b2d0: f7f5 fbfa bl 8000ac8 <__aeabi_dcmpeq>
|
|
800b2d4: 2800 cmp r0, #0
|
|
800b2d6: d034 beq.n 800b342 <_printf_float+0x27a>
|
|
800b2d8: 4a37 ldr r2, [pc, #220] ; (800b3b8 <_printf_float+0x2f0>)
|
|
800b2da: 2301 movs r3, #1
|
|
800b2dc: 4631 mov r1, r6
|
|
800b2de: 4628 mov r0, r5
|
|
800b2e0: 47b8 blx r7
|
|
800b2e2: 3001 adds r0, #1
|
|
800b2e4: f43f af51 beq.w 800b18a <_printf_float+0xc2>
|
|
800b2e8: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24
|
|
800b2ec: 429a cmp r2, r3
|
|
800b2ee: db02 blt.n 800b2f6 <_printf_float+0x22e>
|
|
800b2f0: 6823 ldr r3, [r4, #0]
|
|
800b2f2: 07d8 lsls r0, r3, #31
|
|
800b2f4: d510 bpl.n 800b318 <_printf_float+0x250>
|
|
800b2f6: ee18 3a10 vmov r3, s16
|
|
800b2fa: 4652 mov r2, sl
|
|
800b2fc: 4631 mov r1, r6
|
|
800b2fe: 4628 mov r0, r5
|
|
800b300: 47b8 blx r7
|
|
800b302: 3001 adds r0, #1
|
|
800b304: f43f af41 beq.w 800b18a <_printf_float+0xc2>
|
|
800b308: f04f 0800 mov.w r8, #0
|
|
800b30c: f104 091a add.w r9, r4, #26
|
|
800b310: 9b0a ldr r3, [sp, #40] ; 0x28
|
|
800b312: 3b01 subs r3, #1
|
|
800b314: 4543 cmp r3, r8
|
|
800b316: dc09 bgt.n 800b32c <_printf_float+0x264>
|
|
800b318: 6823 ldr r3, [r4, #0]
|
|
800b31a: 079b lsls r3, r3, #30
|
|
800b31c: f100 8105 bmi.w 800b52a <_printf_float+0x462>
|
|
800b320: 68e0 ldr r0, [r4, #12]
|
|
800b322: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
800b324: 4298 cmp r0, r3
|
|
800b326: bfb8 it lt
|
|
800b328: 4618 movlt r0, r3
|
|
800b32a: e730 b.n 800b18e <_printf_float+0xc6>
|
|
800b32c: 2301 movs r3, #1
|
|
800b32e: 464a mov r2, r9
|
|
800b330: 4631 mov r1, r6
|
|
800b332: 4628 mov r0, r5
|
|
800b334: 47b8 blx r7
|
|
800b336: 3001 adds r0, #1
|
|
800b338: f43f af27 beq.w 800b18a <_printf_float+0xc2>
|
|
800b33c: f108 0801 add.w r8, r8, #1
|
|
800b340: e7e6 b.n 800b310 <_printf_float+0x248>
|
|
800b342: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800b344: 2b00 cmp r3, #0
|
|
800b346: dc39 bgt.n 800b3bc <_printf_float+0x2f4>
|
|
800b348: 4a1b ldr r2, [pc, #108] ; (800b3b8 <_printf_float+0x2f0>)
|
|
800b34a: 2301 movs r3, #1
|
|
800b34c: 4631 mov r1, r6
|
|
800b34e: 4628 mov r0, r5
|
|
800b350: 47b8 blx r7
|
|
800b352: 3001 adds r0, #1
|
|
800b354: f43f af19 beq.w 800b18a <_printf_float+0xc2>
|
|
800b358: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24
|
|
800b35c: 4313 orrs r3, r2
|
|
800b35e: d102 bne.n 800b366 <_printf_float+0x29e>
|
|
800b360: 6823 ldr r3, [r4, #0]
|
|
800b362: 07d9 lsls r1, r3, #31
|
|
800b364: d5d8 bpl.n 800b318 <_printf_float+0x250>
|
|
800b366: ee18 3a10 vmov r3, s16
|
|
800b36a: 4652 mov r2, sl
|
|
800b36c: 4631 mov r1, r6
|
|
800b36e: 4628 mov r0, r5
|
|
800b370: 47b8 blx r7
|
|
800b372: 3001 adds r0, #1
|
|
800b374: f43f af09 beq.w 800b18a <_printf_float+0xc2>
|
|
800b378: f04f 0900 mov.w r9, #0
|
|
800b37c: f104 0a1a add.w sl, r4, #26
|
|
800b380: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800b382: 425b negs r3, r3
|
|
800b384: 454b cmp r3, r9
|
|
800b386: dc01 bgt.n 800b38c <_printf_float+0x2c4>
|
|
800b388: 9b0a ldr r3, [sp, #40] ; 0x28
|
|
800b38a: e792 b.n 800b2b2 <_printf_float+0x1ea>
|
|
800b38c: 2301 movs r3, #1
|
|
800b38e: 4652 mov r2, sl
|
|
800b390: 4631 mov r1, r6
|
|
800b392: 4628 mov r0, r5
|
|
800b394: 47b8 blx r7
|
|
800b396: 3001 adds r0, #1
|
|
800b398: f43f aef7 beq.w 800b18a <_printf_float+0xc2>
|
|
800b39c: f109 0901 add.w r9, r9, #1
|
|
800b3a0: e7ee b.n 800b380 <_printf_float+0x2b8>
|
|
800b3a2: bf00 nop
|
|
800b3a4: 7fefffff .word 0x7fefffff
|
|
800b3a8: 0800e3f8 .word 0x0800e3f8
|
|
800b3ac: 0800e3fc .word 0x0800e3fc
|
|
800b3b0: 0800e404 .word 0x0800e404
|
|
800b3b4: 0800e400 .word 0x0800e400
|
|
800b3b8: 0800e408 .word 0x0800e408
|
|
800b3bc: 9a0a ldr r2, [sp, #40] ; 0x28
|
|
800b3be: 6da3 ldr r3, [r4, #88] ; 0x58
|
|
800b3c0: 429a cmp r2, r3
|
|
800b3c2: bfa8 it ge
|
|
800b3c4: 461a movge r2, r3
|
|
800b3c6: 2a00 cmp r2, #0
|
|
800b3c8: 4691 mov r9, r2
|
|
800b3ca: dc37 bgt.n 800b43c <_printf_float+0x374>
|
|
800b3cc: f04f 0b00 mov.w fp, #0
|
|
800b3d0: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
800b3d4: f104 021a add.w r2, r4, #26
|
|
800b3d8: 6da3 ldr r3, [r4, #88] ; 0x58
|
|
800b3da: 9305 str r3, [sp, #20]
|
|
800b3dc: eba3 0309 sub.w r3, r3, r9
|
|
800b3e0: 455b cmp r3, fp
|
|
800b3e2: dc33 bgt.n 800b44c <_printf_float+0x384>
|
|
800b3e4: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24
|
|
800b3e8: 429a cmp r2, r3
|
|
800b3ea: db3b blt.n 800b464 <_printf_float+0x39c>
|
|
800b3ec: 6823 ldr r3, [r4, #0]
|
|
800b3ee: 07da lsls r2, r3, #31
|
|
800b3f0: d438 bmi.n 800b464 <_printf_float+0x39c>
|
|
800b3f2: 9a0a ldr r2, [sp, #40] ; 0x28
|
|
800b3f4: 9b05 ldr r3, [sp, #20]
|
|
800b3f6: 9909 ldr r1, [sp, #36] ; 0x24
|
|
800b3f8: 1ad3 subs r3, r2, r3
|
|
800b3fa: eba2 0901 sub.w r9, r2, r1
|
|
800b3fe: 4599 cmp r9, r3
|
|
800b400: bfa8 it ge
|
|
800b402: 4699 movge r9, r3
|
|
800b404: f1b9 0f00 cmp.w r9, #0
|
|
800b408: dc35 bgt.n 800b476 <_printf_float+0x3ae>
|
|
800b40a: f04f 0800 mov.w r8, #0
|
|
800b40e: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
800b412: f104 0a1a add.w sl, r4, #26
|
|
800b416: e9dd 2309 ldrd r2, r3, [sp, #36] ; 0x24
|
|
800b41a: 1a9b subs r3, r3, r2
|
|
800b41c: eba3 0309 sub.w r3, r3, r9
|
|
800b420: 4543 cmp r3, r8
|
|
800b422: f77f af79 ble.w 800b318 <_printf_float+0x250>
|
|
800b426: 2301 movs r3, #1
|
|
800b428: 4652 mov r2, sl
|
|
800b42a: 4631 mov r1, r6
|
|
800b42c: 4628 mov r0, r5
|
|
800b42e: 47b8 blx r7
|
|
800b430: 3001 adds r0, #1
|
|
800b432: f43f aeaa beq.w 800b18a <_printf_float+0xc2>
|
|
800b436: f108 0801 add.w r8, r8, #1
|
|
800b43a: e7ec b.n 800b416 <_printf_float+0x34e>
|
|
800b43c: 4613 mov r3, r2
|
|
800b43e: 4631 mov r1, r6
|
|
800b440: 4642 mov r2, r8
|
|
800b442: 4628 mov r0, r5
|
|
800b444: 47b8 blx r7
|
|
800b446: 3001 adds r0, #1
|
|
800b448: d1c0 bne.n 800b3cc <_printf_float+0x304>
|
|
800b44a: e69e b.n 800b18a <_printf_float+0xc2>
|
|
800b44c: 2301 movs r3, #1
|
|
800b44e: 4631 mov r1, r6
|
|
800b450: 4628 mov r0, r5
|
|
800b452: 9205 str r2, [sp, #20]
|
|
800b454: 47b8 blx r7
|
|
800b456: 3001 adds r0, #1
|
|
800b458: f43f ae97 beq.w 800b18a <_printf_float+0xc2>
|
|
800b45c: 9a05 ldr r2, [sp, #20]
|
|
800b45e: f10b 0b01 add.w fp, fp, #1
|
|
800b462: e7b9 b.n 800b3d8 <_printf_float+0x310>
|
|
800b464: ee18 3a10 vmov r3, s16
|
|
800b468: 4652 mov r2, sl
|
|
800b46a: 4631 mov r1, r6
|
|
800b46c: 4628 mov r0, r5
|
|
800b46e: 47b8 blx r7
|
|
800b470: 3001 adds r0, #1
|
|
800b472: d1be bne.n 800b3f2 <_printf_float+0x32a>
|
|
800b474: e689 b.n 800b18a <_printf_float+0xc2>
|
|
800b476: 9a05 ldr r2, [sp, #20]
|
|
800b478: 464b mov r3, r9
|
|
800b47a: 4442 add r2, r8
|
|
800b47c: 4631 mov r1, r6
|
|
800b47e: 4628 mov r0, r5
|
|
800b480: 47b8 blx r7
|
|
800b482: 3001 adds r0, #1
|
|
800b484: d1c1 bne.n 800b40a <_printf_float+0x342>
|
|
800b486: e680 b.n 800b18a <_printf_float+0xc2>
|
|
800b488: 9a0a ldr r2, [sp, #40] ; 0x28
|
|
800b48a: 2a01 cmp r2, #1
|
|
800b48c: dc01 bgt.n 800b492 <_printf_float+0x3ca>
|
|
800b48e: 07db lsls r3, r3, #31
|
|
800b490: d538 bpl.n 800b504 <_printf_float+0x43c>
|
|
800b492: 2301 movs r3, #1
|
|
800b494: 4642 mov r2, r8
|
|
800b496: 4631 mov r1, r6
|
|
800b498: 4628 mov r0, r5
|
|
800b49a: 47b8 blx r7
|
|
800b49c: 3001 adds r0, #1
|
|
800b49e: f43f ae74 beq.w 800b18a <_printf_float+0xc2>
|
|
800b4a2: ee18 3a10 vmov r3, s16
|
|
800b4a6: 4652 mov r2, sl
|
|
800b4a8: 4631 mov r1, r6
|
|
800b4aa: 4628 mov r0, r5
|
|
800b4ac: 47b8 blx r7
|
|
800b4ae: 3001 adds r0, #1
|
|
800b4b0: f43f ae6b beq.w 800b18a <_printf_float+0xc2>
|
|
800b4b4: e9d4 0112 ldrd r0, r1, [r4, #72] ; 0x48
|
|
800b4b8: 2200 movs r2, #0
|
|
800b4ba: 2300 movs r3, #0
|
|
800b4bc: f7f5 fb04 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800b4c0: b9d8 cbnz r0, 800b4fa <_printf_float+0x432>
|
|
800b4c2: 9b0a ldr r3, [sp, #40] ; 0x28
|
|
800b4c4: f108 0201 add.w r2, r8, #1
|
|
800b4c8: 3b01 subs r3, #1
|
|
800b4ca: 4631 mov r1, r6
|
|
800b4cc: 4628 mov r0, r5
|
|
800b4ce: 47b8 blx r7
|
|
800b4d0: 3001 adds r0, #1
|
|
800b4d2: d10e bne.n 800b4f2 <_printf_float+0x42a>
|
|
800b4d4: e659 b.n 800b18a <_printf_float+0xc2>
|
|
800b4d6: 2301 movs r3, #1
|
|
800b4d8: 4652 mov r2, sl
|
|
800b4da: 4631 mov r1, r6
|
|
800b4dc: 4628 mov r0, r5
|
|
800b4de: 47b8 blx r7
|
|
800b4e0: 3001 adds r0, #1
|
|
800b4e2: f43f ae52 beq.w 800b18a <_printf_float+0xc2>
|
|
800b4e6: f108 0801 add.w r8, r8, #1
|
|
800b4ea: 9b0a ldr r3, [sp, #40] ; 0x28
|
|
800b4ec: 3b01 subs r3, #1
|
|
800b4ee: 4543 cmp r3, r8
|
|
800b4f0: dcf1 bgt.n 800b4d6 <_printf_float+0x40e>
|
|
800b4f2: 464b mov r3, r9
|
|
800b4f4: f104 0250 add.w r2, r4, #80 ; 0x50
|
|
800b4f8: e6dc b.n 800b2b4 <_printf_float+0x1ec>
|
|
800b4fa: f04f 0800 mov.w r8, #0
|
|
800b4fe: f104 0a1a add.w sl, r4, #26
|
|
800b502: e7f2 b.n 800b4ea <_printf_float+0x422>
|
|
800b504: 2301 movs r3, #1
|
|
800b506: 4642 mov r2, r8
|
|
800b508: e7df b.n 800b4ca <_printf_float+0x402>
|
|
800b50a: 2301 movs r3, #1
|
|
800b50c: 464a mov r2, r9
|
|
800b50e: 4631 mov r1, r6
|
|
800b510: 4628 mov r0, r5
|
|
800b512: 47b8 blx r7
|
|
800b514: 3001 adds r0, #1
|
|
800b516: f43f ae38 beq.w 800b18a <_printf_float+0xc2>
|
|
800b51a: f108 0801 add.w r8, r8, #1
|
|
800b51e: 68e3 ldr r3, [r4, #12]
|
|
800b520: 990b ldr r1, [sp, #44] ; 0x2c
|
|
800b522: 1a5b subs r3, r3, r1
|
|
800b524: 4543 cmp r3, r8
|
|
800b526: dcf0 bgt.n 800b50a <_printf_float+0x442>
|
|
800b528: e6fa b.n 800b320 <_printf_float+0x258>
|
|
800b52a: f04f 0800 mov.w r8, #0
|
|
800b52e: f104 0919 add.w r9, r4, #25
|
|
800b532: e7f4 b.n 800b51e <_printf_float+0x456>
|
|
|
|
0800b534 <_printf_common>:
|
|
800b534: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800b538: 4616 mov r6, r2
|
|
800b53a: 4699 mov r9, r3
|
|
800b53c: 688a ldr r2, [r1, #8]
|
|
800b53e: 690b ldr r3, [r1, #16]
|
|
800b540: f8dd 8020 ldr.w r8, [sp, #32]
|
|
800b544: 4293 cmp r3, r2
|
|
800b546: bfb8 it lt
|
|
800b548: 4613 movlt r3, r2
|
|
800b54a: 6033 str r3, [r6, #0]
|
|
800b54c: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
|
|
800b550: 4607 mov r7, r0
|
|
800b552: 460c mov r4, r1
|
|
800b554: b10a cbz r2, 800b55a <_printf_common+0x26>
|
|
800b556: 3301 adds r3, #1
|
|
800b558: 6033 str r3, [r6, #0]
|
|
800b55a: 6823 ldr r3, [r4, #0]
|
|
800b55c: 0699 lsls r1, r3, #26
|
|
800b55e: bf42 ittt mi
|
|
800b560: 6833 ldrmi r3, [r6, #0]
|
|
800b562: 3302 addmi r3, #2
|
|
800b564: 6033 strmi r3, [r6, #0]
|
|
800b566: 6825 ldr r5, [r4, #0]
|
|
800b568: f015 0506 ands.w r5, r5, #6
|
|
800b56c: d106 bne.n 800b57c <_printf_common+0x48>
|
|
800b56e: f104 0a19 add.w sl, r4, #25
|
|
800b572: 68e3 ldr r3, [r4, #12]
|
|
800b574: 6832 ldr r2, [r6, #0]
|
|
800b576: 1a9b subs r3, r3, r2
|
|
800b578: 42ab cmp r3, r5
|
|
800b57a: dc26 bgt.n 800b5ca <_printf_common+0x96>
|
|
800b57c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43
|
|
800b580: 1e13 subs r3, r2, #0
|
|
800b582: 6822 ldr r2, [r4, #0]
|
|
800b584: bf18 it ne
|
|
800b586: 2301 movne r3, #1
|
|
800b588: 0692 lsls r2, r2, #26
|
|
800b58a: d42b bmi.n 800b5e4 <_printf_common+0xb0>
|
|
800b58c: f104 0243 add.w r2, r4, #67 ; 0x43
|
|
800b590: 4649 mov r1, r9
|
|
800b592: 4638 mov r0, r7
|
|
800b594: 47c0 blx r8
|
|
800b596: 3001 adds r0, #1
|
|
800b598: d01e beq.n 800b5d8 <_printf_common+0xa4>
|
|
800b59a: 6823 ldr r3, [r4, #0]
|
|
800b59c: 68e5 ldr r5, [r4, #12]
|
|
800b59e: 6832 ldr r2, [r6, #0]
|
|
800b5a0: f003 0306 and.w r3, r3, #6
|
|
800b5a4: 2b04 cmp r3, #4
|
|
800b5a6: bf08 it eq
|
|
800b5a8: 1aad subeq r5, r5, r2
|
|
800b5aa: 68a3 ldr r3, [r4, #8]
|
|
800b5ac: 6922 ldr r2, [r4, #16]
|
|
800b5ae: bf0c ite eq
|
|
800b5b0: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
800b5b4: 2500 movne r5, #0
|
|
800b5b6: 4293 cmp r3, r2
|
|
800b5b8: bfc4 itt gt
|
|
800b5ba: 1a9b subgt r3, r3, r2
|
|
800b5bc: 18ed addgt r5, r5, r3
|
|
800b5be: 2600 movs r6, #0
|
|
800b5c0: 341a adds r4, #26
|
|
800b5c2: 42b5 cmp r5, r6
|
|
800b5c4: d11a bne.n 800b5fc <_printf_common+0xc8>
|
|
800b5c6: 2000 movs r0, #0
|
|
800b5c8: e008 b.n 800b5dc <_printf_common+0xa8>
|
|
800b5ca: 2301 movs r3, #1
|
|
800b5cc: 4652 mov r2, sl
|
|
800b5ce: 4649 mov r1, r9
|
|
800b5d0: 4638 mov r0, r7
|
|
800b5d2: 47c0 blx r8
|
|
800b5d4: 3001 adds r0, #1
|
|
800b5d6: d103 bne.n 800b5e0 <_printf_common+0xac>
|
|
800b5d8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800b5dc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800b5e0: 3501 adds r5, #1
|
|
800b5e2: e7c6 b.n 800b572 <_printf_common+0x3e>
|
|
800b5e4: 18e1 adds r1, r4, r3
|
|
800b5e6: 1c5a adds r2, r3, #1
|
|
800b5e8: 2030 movs r0, #48 ; 0x30
|
|
800b5ea: f881 0043 strb.w r0, [r1, #67] ; 0x43
|
|
800b5ee: 4422 add r2, r4
|
|
800b5f0: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
|
|
800b5f4: f882 1043 strb.w r1, [r2, #67] ; 0x43
|
|
800b5f8: 3302 adds r3, #2
|
|
800b5fa: e7c7 b.n 800b58c <_printf_common+0x58>
|
|
800b5fc: 2301 movs r3, #1
|
|
800b5fe: 4622 mov r2, r4
|
|
800b600: 4649 mov r1, r9
|
|
800b602: 4638 mov r0, r7
|
|
800b604: 47c0 blx r8
|
|
800b606: 3001 adds r0, #1
|
|
800b608: d0e6 beq.n 800b5d8 <_printf_common+0xa4>
|
|
800b60a: 3601 adds r6, #1
|
|
800b60c: e7d9 b.n 800b5c2 <_printf_common+0x8e>
|
|
...
|
|
|
|
0800b610 <_printf_i>:
|
|
800b610: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800b614: 460c mov r4, r1
|
|
800b616: 4691 mov r9, r2
|
|
800b618: 7e27 ldrb r7, [r4, #24]
|
|
800b61a: 990c ldr r1, [sp, #48] ; 0x30
|
|
800b61c: 2f78 cmp r7, #120 ; 0x78
|
|
800b61e: 4680 mov r8, r0
|
|
800b620: 469a mov sl, r3
|
|
800b622: f104 0243 add.w r2, r4, #67 ; 0x43
|
|
800b626: d807 bhi.n 800b638 <_printf_i+0x28>
|
|
800b628: 2f62 cmp r7, #98 ; 0x62
|
|
800b62a: d80a bhi.n 800b642 <_printf_i+0x32>
|
|
800b62c: 2f00 cmp r7, #0
|
|
800b62e: f000 80d8 beq.w 800b7e2 <_printf_i+0x1d2>
|
|
800b632: 2f58 cmp r7, #88 ; 0x58
|
|
800b634: f000 80a3 beq.w 800b77e <_printf_i+0x16e>
|
|
800b638: f104 0642 add.w r6, r4, #66 ; 0x42
|
|
800b63c: f884 7042 strb.w r7, [r4, #66] ; 0x42
|
|
800b640: e03a b.n 800b6b8 <_printf_i+0xa8>
|
|
800b642: f1a7 0363 sub.w r3, r7, #99 ; 0x63
|
|
800b646: 2b15 cmp r3, #21
|
|
800b648: d8f6 bhi.n 800b638 <_printf_i+0x28>
|
|
800b64a: a001 add r0, pc, #4 ; (adr r0, 800b650 <_printf_i+0x40>)
|
|
800b64c: f850 f023 ldr.w pc, [r0, r3, lsl #2]
|
|
800b650: 0800b6a9 .word 0x0800b6a9
|
|
800b654: 0800b6bd .word 0x0800b6bd
|
|
800b658: 0800b639 .word 0x0800b639
|
|
800b65c: 0800b639 .word 0x0800b639
|
|
800b660: 0800b639 .word 0x0800b639
|
|
800b664: 0800b639 .word 0x0800b639
|
|
800b668: 0800b6bd .word 0x0800b6bd
|
|
800b66c: 0800b639 .word 0x0800b639
|
|
800b670: 0800b639 .word 0x0800b639
|
|
800b674: 0800b639 .word 0x0800b639
|
|
800b678: 0800b639 .word 0x0800b639
|
|
800b67c: 0800b7c9 .word 0x0800b7c9
|
|
800b680: 0800b6ed .word 0x0800b6ed
|
|
800b684: 0800b7ab .word 0x0800b7ab
|
|
800b688: 0800b639 .word 0x0800b639
|
|
800b68c: 0800b639 .word 0x0800b639
|
|
800b690: 0800b7eb .word 0x0800b7eb
|
|
800b694: 0800b639 .word 0x0800b639
|
|
800b698: 0800b6ed .word 0x0800b6ed
|
|
800b69c: 0800b639 .word 0x0800b639
|
|
800b6a0: 0800b639 .word 0x0800b639
|
|
800b6a4: 0800b7b3 .word 0x0800b7b3
|
|
800b6a8: 680b ldr r3, [r1, #0]
|
|
800b6aa: 1d1a adds r2, r3, #4
|
|
800b6ac: 681b ldr r3, [r3, #0]
|
|
800b6ae: 600a str r2, [r1, #0]
|
|
800b6b0: f104 0642 add.w r6, r4, #66 ; 0x42
|
|
800b6b4: f884 3042 strb.w r3, [r4, #66] ; 0x42
|
|
800b6b8: 2301 movs r3, #1
|
|
800b6ba: e0a3 b.n 800b804 <_printf_i+0x1f4>
|
|
800b6bc: 6825 ldr r5, [r4, #0]
|
|
800b6be: 6808 ldr r0, [r1, #0]
|
|
800b6c0: 062e lsls r6, r5, #24
|
|
800b6c2: f100 0304 add.w r3, r0, #4
|
|
800b6c6: d50a bpl.n 800b6de <_printf_i+0xce>
|
|
800b6c8: 6805 ldr r5, [r0, #0]
|
|
800b6ca: 600b str r3, [r1, #0]
|
|
800b6cc: 2d00 cmp r5, #0
|
|
800b6ce: da03 bge.n 800b6d8 <_printf_i+0xc8>
|
|
800b6d0: 232d movs r3, #45 ; 0x2d
|
|
800b6d2: 426d negs r5, r5
|
|
800b6d4: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
800b6d8: 485e ldr r0, [pc, #376] ; (800b854 <_printf_i+0x244>)
|
|
800b6da: 230a movs r3, #10
|
|
800b6dc: e019 b.n 800b712 <_printf_i+0x102>
|
|
800b6de: f015 0f40 tst.w r5, #64 ; 0x40
|
|
800b6e2: 6805 ldr r5, [r0, #0]
|
|
800b6e4: 600b str r3, [r1, #0]
|
|
800b6e6: bf18 it ne
|
|
800b6e8: b22d sxthne r5, r5
|
|
800b6ea: e7ef b.n 800b6cc <_printf_i+0xbc>
|
|
800b6ec: 680b ldr r3, [r1, #0]
|
|
800b6ee: 6825 ldr r5, [r4, #0]
|
|
800b6f0: 1d18 adds r0, r3, #4
|
|
800b6f2: 6008 str r0, [r1, #0]
|
|
800b6f4: 0628 lsls r0, r5, #24
|
|
800b6f6: d501 bpl.n 800b6fc <_printf_i+0xec>
|
|
800b6f8: 681d ldr r5, [r3, #0]
|
|
800b6fa: e002 b.n 800b702 <_printf_i+0xf2>
|
|
800b6fc: 0669 lsls r1, r5, #25
|
|
800b6fe: d5fb bpl.n 800b6f8 <_printf_i+0xe8>
|
|
800b700: 881d ldrh r5, [r3, #0]
|
|
800b702: 4854 ldr r0, [pc, #336] ; (800b854 <_printf_i+0x244>)
|
|
800b704: 2f6f cmp r7, #111 ; 0x6f
|
|
800b706: bf0c ite eq
|
|
800b708: 2308 moveq r3, #8
|
|
800b70a: 230a movne r3, #10
|
|
800b70c: 2100 movs r1, #0
|
|
800b70e: f884 1043 strb.w r1, [r4, #67] ; 0x43
|
|
800b712: 6866 ldr r6, [r4, #4]
|
|
800b714: 60a6 str r6, [r4, #8]
|
|
800b716: 2e00 cmp r6, #0
|
|
800b718: bfa2 ittt ge
|
|
800b71a: 6821 ldrge r1, [r4, #0]
|
|
800b71c: f021 0104 bicge.w r1, r1, #4
|
|
800b720: 6021 strge r1, [r4, #0]
|
|
800b722: b90d cbnz r5, 800b728 <_printf_i+0x118>
|
|
800b724: 2e00 cmp r6, #0
|
|
800b726: d04d beq.n 800b7c4 <_printf_i+0x1b4>
|
|
800b728: 4616 mov r6, r2
|
|
800b72a: fbb5 f1f3 udiv r1, r5, r3
|
|
800b72e: fb03 5711 mls r7, r3, r1, r5
|
|
800b732: 5dc7 ldrb r7, [r0, r7]
|
|
800b734: f806 7d01 strb.w r7, [r6, #-1]!
|
|
800b738: 462f mov r7, r5
|
|
800b73a: 42bb cmp r3, r7
|
|
800b73c: 460d mov r5, r1
|
|
800b73e: d9f4 bls.n 800b72a <_printf_i+0x11a>
|
|
800b740: 2b08 cmp r3, #8
|
|
800b742: d10b bne.n 800b75c <_printf_i+0x14c>
|
|
800b744: 6823 ldr r3, [r4, #0]
|
|
800b746: 07df lsls r7, r3, #31
|
|
800b748: d508 bpl.n 800b75c <_printf_i+0x14c>
|
|
800b74a: 6923 ldr r3, [r4, #16]
|
|
800b74c: 6861 ldr r1, [r4, #4]
|
|
800b74e: 4299 cmp r1, r3
|
|
800b750: bfde ittt le
|
|
800b752: 2330 movle r3, #48 ; 0x30
|
|
800b754: f806 3c01 strble.w r3, [r6, #-1]
|
|
800b758: f106 36ff addle.w r6, r6, #4294967295 ; 0xffffffff
|
|
800b75c: 1b92 subs r2, r2, r6
|
|
800b75e: 6122 str r2, [r4, #16]
|
|
800b760: f8cd a000 str.w sl, [sp]
|
|
800b764: 464b mov r3, r9
|
|
800b766: aa03 add r2, sp, #12
|
|
800b768: 4621 mov r1, r4
|
|
800b76a: 4640 mov r0, r8
|
|
800b76c: f7ff fee2 bl 800b534 <_printf_common>
|
|
800b770: 3001 adds r0, #1
|
|
800b772: d14c bne.n 800b80e <_printf_i+0x1fe>
|
|
800b774: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800b778: b004 add sp, #16
|
|
800b77a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800b77e: 4835 ldr r0, [pc, #212] ; (800b854 <_printf_i+0x244>)
|
|
800b780: f884 7045 strb.w r7, [r4, #69] ; 0x45
|
|
800b784: 6823 ldr r3, [r4, #0]
|
|
800b786: 680e ldr r6, [r1, #0]
|
|
800b788: 061f lsls r7, r3, #24
|
|
800b78a: f856 5b04 ldr.w r5, [r6], #4
|
|
800b78e: 600e str r6, [r1, #0]
|
|
800b790: d514 bpl.n 800b7bc <_printf_i+0x1ac>
|
|
800b792: 07d9 lsls r1, r3, #31
|
|
800b794: bf44 itt mi
|
|
800b796: f043 0320 orrmi.w r3, r3, #32
|
|
800b79a: 6023 strmi r3, [r4, #0]
|
|
800b79c: b91d cbnz r5, 800b7a6 <_printf_i+0x196>
|
|
800b79e: 6823 ldr r3, [r4, #0]
|
|
800b7a0: f023 0320 bic.w r3, r3, #32
|
|
800b7a4: 6023 str r3, [r4, #0]
|
|
800b7a6: 2310 movs r3, #16
|
|
800b7a8: e7b0 b.n 800b70c <_printf_i+0xfc>
|
|
800b7aa: 6823 ldr r3, [r4, #0]
|
|
800b7ac: f043 0320 orr.w r3, r3, #32
|
|
800b7b0: 6023 str r3, [r4, #0]
|
|
800b7b2: 2378 movs r3, #120 ; 0x78
|
|
800b7b4: 4828 ldr r0, [pc, #160] ; (800b858 <_printf_i+0x248>)
|
|
800b7b6: f884 3045 strb.w r3, [r4, #69] ; 0x45
|
|
800b7ba: e7e3 b.n 800b784 <_printf_i+0x174>
|
|
800b7bc: 065e lsls r6, r3, #25
|
|
800b7be: bf48 it mi
|
|
800b7c0: b2ad uxthmi r5, r5
|
|
800b7c2: e7e6 b.n 800b792 <_printf_i+0x182>
|
|
800b7c4: 4616 mov r6, r2
|
|
800b7c6: e7bb b.n 800b740 <_printf_i+0x130>
|
|
800b7c8: 680b ldr r3, [r1, #0]
|
|
800b7ca: 6826 ldr r6, [r4, #0]
|
|
800b7cc: 6960 ldr r0, [r4, #20]
|
|
800b7ce: 1d1d adds r5, r3, #4
|
|
800b7d0: 600d str r5, [r1, #0]
|
|
800b7d2: 0635 lsls r5, r6, #24
|
|
800b7d4: 681b ldr r3, [r3, #0]
|
|
800b7d6: d501 bpl.n 800b7dc <_printf_i+0x1cc>
|
|
800b7d8: 6018 str r0, [r3, #0]
|
|
800b7da: e002 b.n 800b7e2 <_printf_i+0x1d2>
|
|
800b7dc: 0671 lsls r1, r6, #25
|
|
800b7de: d5fb bpl.n 800b7d8 <_printf_i+0x1c8>
|
|
800b7e0: 8018 strh r0, [r3, #0]
|
|
800b7e2: 2300 movs r3, #0
|
|
800b7e4: 6123 str r3, [r4, #16]
|
|
800b7e6: 4616 mov r6, r2
|
|
800b7e8: e7ba b.n 800b760 <_printf_i+0x150>
|
|
800b7ea: 680b ldr r3, [r1, #0]
|
|
800b7ec: 1d1a adds r2, r3, #4
|
|
800b7ee: 600a str r2, [r1, #0]
|
|
800b7f0: 681e ldr r6, [r3, #0]
|
|
800b7f2: 6862 ldr r2, [r4, #4]
|
|
800b7f4: 2100 movs r1, #0
|
|
800b7f6: 4630 mov r0, r6
|
|
800b7f8: f7f4 fcf2 bl 80001e0 <memchr>
|
|
800b7fc: b108 cbz r0, 800b802 <_printf_i+0x1f2>
|
|
800b7fe: 1b80 subs r0, r0, r6
|
|
800b800: 6060 str r0, [r4, #4]
|
|
800b802: 6863 ldr r3, [r4, #4]
|
|
800b804: 6123 str r3, [r4, #16]
|
|
800b806: 2300 movs r3, #0
|
|
800b808: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
800b80c: e7a8 b.n 800b760 <_printf_i+0x150>
|
|
800b80e: 6923 ldr r3, [r4, #16]
|
|
800b810: 4632 mov r2, r6
|
|
800b812: 4649 mov r1, r9
|
|
800b814: 4640 mov r0, r8
|
|
800b816: 47d0 blx sl
|
|
800b818: 3001 adds r0, #1
|
|
800b81a: d0ab beq.n 800b774 <_printf_i+0x164>
|
|
800b81c: 6823 ldr r3, [r4, #0]
|
|
800b81e: 079b lsls r3, r3, #30
|
|
800b820: d413 bmi.n 800b84a <_printf_i+0x23a>
|
|
800b822: 68e0 ldr r0, [r4, #12]
|
|
800b824: 9b03 ldr r3, [sp, #12]
|
|
800b826: 4298 cmp r0, r3
|
|
800b828: bfb8 it lt
|
|
800b82a: 4618 movlt r0, r3
|
|
800b82c: e7a4 b.n 800b778 <_printf_i+0x168>
|
|
800b82e: 2301 movs r3, #1
|
|
800b830: 4632 mov r2, r6
|
|
800b832: 4649 mov r1, r9
|
|
800b834: 4640 mov r0, r8
|
|
800b836: 47d0 blx sl
|
|
800b838: 3001 adds r0, #1
|
|
800b83a: d09b beq.n 800b774 <_printf_i+0x164>
|
|
800b83c: 3501 adds r5, #1
|
|
800b83e: 68e3 ldr r3, [r4, #12]
|
|
800b840: 9903 ldr r1, [sp, #12]
|
|
800b842: 1a5b subs r3, r3, r1
|
|
800b844: 42ab cmp r3, r5
|
|
800b846: dcf2 bgt.n 800b82e <_printf_i+0x21e>
|
|
800b848: e7eb b.n 800b822 <_printf_i+0x212>
|
|
800b84a: 2500 movs r5, #0
|
|
800b84c: f104 0619 add.w r6, r4, #25
|
|
800b850: e7f5 b.n 800b83e <_printf_i+0x22e>
|
|
800b852: bf00 nop
|
|
800b854: 0800e40a .word 0x0800e40a
|
|
800b858: 0800e41b .word 0x0800e41b
|
|
|
|
0800b85c <iprintf>:
|
|
800b85c: b40f push {r0, r1, r2, r3}
|
|
800b85e: 4b0a ldr r3, [pc, #40] ; (800b888 <iprintf+0x2c>)
|
|
800b860: b513 push {r0, r1, r4, lr}
|
|
800b862: 681c ldr r4, [r3, #0]
|
|
800b864: b124 cbz r4, 800b870 <iprintf+0x14>
|
|
800b866: 69a3 ldr r3, [r4, #24]
|
|
800b868: b913 cbnz r3, 800b870 <iprintf+0x14>
|
|
800b86a: 4620 mov r0, r4
|
|
800b86c: f001 f92e bl 800cacc <__sinit>
|
|
800b870: ab05 add r3, sp, #20
|
|
800b872: 9a04 ldr r2, [sp, #16]
|
|
800b874: 68a1 ldr r1, [r4, #8]
|
|
800b876: 9301 str r3, [sp, #4]
|
|
800b878: 4620 mov r0, r4
|
|
800b87a: f002 f809 bl 800d890 <_vfiprintf_r>
|
|
800b87e: b002 add sp, #8
|
|
800b880: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
800b884: b004 add sp, #16
|
|
800b886: 4770 bx lr
|
|
800b888: 20000278 .word 0x20000278
|
|
|
|
0800b88c <_puts_r>:
|
|
800b88c: b570 push {r4, r5, r6, lr}
|
|
800b88e: 460e mov r6, r1
|
|
800b890: 4605 mov r5, r0
|
|
800b892: b118 cbz r0, 800b89c <_puts_r+0x10>
|
|
800b894: 6983 ldr r3, [r0, #24]
|
|
800b896: b90b cbnz r3, 800b89c <_puts_r+0x10>
|
|
800b898: f001 f918 bl 800cacc <__sinit>
|
|
800b89c: 69ab ldr r3, [r5, #24]
|
|
800b89e: 68ac ldr r4, [r5, #8]
|
|
800b8a0: b913 cbnz r3, 800b8a8 <_puts_r+0x1c>
|
|
800b8a2: 4628 mov r0, r5
|
|
800b8a4: f001 f912 bl 800cacc <__sinit>
|
|
800b8a8: 4b2c ldr r3, [pc, #176] ; (800b95c <_puts_r+0xd0>)
|
|
800b8aa: 429c cmp r4, r3
|
|
800b8ac: d120 bne.n 800b8f0 <_puts_r+0x64>
|
|
800b8ae: 686c ldr r4, [r5, #4]
|
|
800b8b0: 6e63 ldr r3, [r4, #100] ; 0x64
|
|
800b8b2: 07db lsls r3, r3, #31
|
|
800b8b4: d405 bmi.n 800b8c2 <_puts_r+0x36>
|
|
800b8b6: 89a3 ldrh r3, [r4, #12]
|
|
800b8b8: 0598 lsls r0, r3, #22
|
|
800b8ba: d402 bmi.n 800b8c2 <_puts_r+0x36>
|
|
800b8bc: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
800b8be: f001 f9ba bl 800cc36 <__retarget_lock_acquire_recursive>
|
|
800b8c2: 89a3 ldrh r3, [r4, #12]
|
|
800b8c4: 0719 lsls r1, r3, #28
|
|
800b8c6: d51d bpl.n 800b904 <_puts_r+0x78>
|
|
800b8c8: 6923 ldr r3, [r4, #16]
|
|
800b8ca: b1db cbz r3, 800b904 <_puts_r+0x78>
|
|
800b8cc: 3e01 subs r6, #1
|
|
800b8ce: 68a3 ldr r3, [r4, #8]
|
|
800b8d0: f816 1f01 ldrb.w r1, [r6, #1]!
|
|
800b8d4: 3b01 subs r3, #1
|
|
800b8d6: 60a3 str r3, [r4, #8]
|
|
800b8d8: bb39 cbnz r1, 800b92a <_puts_r+0x9e>
|
|
800b8da: 2b00 cmp r3, #0
|
|
800b8dc: da38 bge.n 800b950 <_puts_r+0xc4>
|
|
800b8de: 4622 mov r2, r4
|
|
800b8e0: 210a movs r1, #10
|
|
800b8e2: 4628 mov r0, r5
|
|
800b8e4: f000 f880 bl 800b9e8 <__swbuf_r>
|
|
800b8e8: 3001 adds r0, #1
|
|
800b8ea: d011 beq.n 800b910 <_puts_r+0x84>
|
|
800b8ec: 250a movs r5, #10
|
|
800b8ee: e011 b.n 800b914 <_puts_r+0x88>
|
|
800b8f0: 4b1b ldr r3, [pc, #108] ; (800b960 <_puts_r+0xd4>)
|
|
800b8f2: 429c cmp r4, r3
|
|
800b8f4: d101 bne.n 800b8fa <_puts_r+0x6e>
|
|
800b8f6: 68ac ldr r4, [r5, #8]
|
|
800b8f8: e7da b.n 800b8b0 <_puts_r+0x24>
|
|
800b8fa: 4b1a ldr r3, [pc, #104] ; (800b964 <_puts_r+0xd8>)
|
|
800b8fc: 429c cmp r4, r3
|
|
800b8fe: bf08 it eq
|
|
800b900: 68ec ldreq r4, [r5, #12]
|
|
800b902: e7d5 b.n 800b8b0 <_puts_r+0x24>
|
|
800b904: 4621 mov r1, r4
|
|
800b906: 4628 mov r0, r5
|
|
800b908: f000 f8c0 bl 800ba8c <__swsetup_r>
|
|
800b90c: 2800 cmp r0, #0
|
|
800b90e: d0dd beq.n 800b8cc <_puts_r+0x40>
|
|
800b910: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff
|
|
800b914: 6e63 ldr r3, [r4, #100] ; 0x64
|
|
800b916: 07da lsls r2, r3, #31
|
|
800b918: d405 bmi.n 800b926 <_puts_r+0x9a>
|
|
800b91a: 89a3 ldrh r3, [r4, #12]
|
|
800b91c: 059b lsls r3, r3, #22
|
|
800b91e: d402 bmi.n 800b926 <_puts_r+0x9a>
|
|
800b920: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
800b922: f001 f989 bl 800cc38 <__retarget_lock_release_recursive>
|
|
800b926: 4628 mov r0, r5
|
|
800b928: bd70 pop {r4, r5, r6, pc}
|
|
800b92a: 2b00 cmp r3, #0
|
|
800b92c: da04 bge.n 800b938 <_puts_r+0xac>
|
|
800b92e: 69a2 ldr r2, [r4, #24]
|
|
800b930: 429a cmp r2, r3
|
|
800b932: dc06 bgt.n 800b942 <_puts_r+0xb6>
|
|
800b934: 290a cmp r1, #10
|
|
800b936: d004 beq.n 800b942 <_puts_r+0xb6>
|
|
800b938: 6823 ldr r3, [r4, #0]
|
|
800b93a: 1c5a adds r2, r3, #1
|
|
800b93c: 6022 str r2, [r4, #0]
|
|
800b93e: 7019 strb r1, [r3, #0]
|
|
800b940: e7c5 b.n 800b8ce <_puts_r+0x42>
|
|
800b942: 4622 mov r2, r4
|
|
800b944: 4628 mov r0, r5
|
|
800b946: f000 f84f bl 800b9e8 <__swbuf_r>
|
|
800b94a: 3001 adds r0, #1
|
|
800b94c: d1bf bne.n 800b8ce <_puts_r+0x42>
|
|
800b94e: e7df b.n 800b910 <_puts_r+0x84>
|
|
800b950: 6823 ldr r3, [r4, #0]
|
|
800b952: 250a movs r5, #10
|
|
800b954: 1c5a adds r2, r3, #1
|
|
800b956: 6022 str r2, [r4, #0]
|
|
800b958: 701d strb r5, [r3, #0]
|
|
800b95a: e7db b.n 800b914 <_puts_r+0x88>
|
|
800b95c: 0800e620 .word 0x0800e620
|
|
800b960: 0800e640 .word 0x0800e640
|
|
800b964: 0800e600 .word 0x0800e600
|
|
|
|
0800b968 <puts>:
|
|
800b968: 4b02 ldr r3, [pc, #8] ; (800b974 <puts+0xc>)
|
|
800b96a: 4601 mov r1, r0
|
|
800b96c: 6818 ldr r0, [r3, #0]
|
|
800b96e: f7ff bf8d b.w 800b88c <_puts_r>
|
|
800b972: bf00 nop
|
|
800b974: 20000278 .word 0x20000278
|
|
|
|
0800b978 <siprintf>:
|
|
800b978: b40e push {r1, r2, r3}
|
|
800b97a: b500 push {lr}
|
|
800b97c: b09c sub sp, #112 ; 0x70
|
|
800b97e: ab1d add r3, sp, #116 ; 0x74
|
|
800b980: 9002 str r0, [sp, #8]
|
|
800b982: 9006 str r0, [sp, #24]
|
|
800b984: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
|
|
800b988: 4809 ldr r0, [pc, #36] ; (800b9b0 <siprintf+0x38>)
|
|
800b98a: 9107 str r1, [sp, #28]
|
|
800b98c: 9104 str r1, [sp, #16]
|
|
800b98e: 4909 ldr r1, [pc, #36] ; (800b9b4 <siprintf+0x3c>)
|
|
800b990: f853 2b04 ldr.w r2, [r3], #4
|
|
800b994: 9105 str r1, [sp, #20]
|
|
800b996: 6800 ldr r0, [r0, #0]
|
|
800b998: 9301 str r3, [sp, #4]
|
|
800b99a: a902 add r1, sp, #8
|
|
800b99c: f001 fe4e bl 800d63c <_svfiprintf_r>
|
|
800b9a0: 9b02 ldr r3, [sp, #8]
|
|
800b9a2: 2200 movs r2, #0
|
|
800b9a4: 701a strb r2, [r3, #0]
|
|
800b9a6: b01c add sp, #112 ; 0x70
|
|
800b9a8: f85d eb04 ldr.w lr, [sp], #4
|
|
800b9ac: b003 add sp, #12
|
|
800b9ae: 4770 bx lr
|
|
800b9b0: 20000278 .word 0x20000278
|
|
800b9b4: ffff0208 .word 0xffff0208
|
|
|
|
0800b9b8 <strstr>:
|
|
800b9b8: b5f0 push {r4, r5, r6, r7, lr}
|
|
800b9ba: 780c ldrb r4, [r1, #0]
|
|
800b9bc: b164 cbz r4, 800b9d8 <strstr+0x20>
|
|
800b9be: 4603 mov r3, r0
|
|
800b9c0: 781a ldrb r2, [r3, #0]
|
|
800b9c2: 4618 mov r0, r3
|
|
800b9c4: 1c5e adds r6, r3, #1
|
|
800b9c6: b90a cbnz r2, 800b9cc <strstr+0x14>
|
|
800b9c8: 4610 mov r0, r2
|
|
800b9ca: e005 b.n 800b9d8 <strstr+0x20>
|
|
800b9cc: 4294 cmp r4, r2
|
|
800b9ce: d108 bne.n 800b9e2 <strstr+0x2a>
|
|
800b9d0: 460d mov r5, r1
|
|
800b9d2: f815 2f01 ldrb.w r2, [r5, #1]!
|
|
800b9d6: b902 cbnz r2, 800b9da <strstr+0x22>
|
|
800b9d8: bdf0 pop {r4, r5, r6, r7, pc}
|
|
800b9da: f813 7f01 ldrb.w r7, [r3, #1]!
|
|
800b9de: 4297 cmp r7, r2
|
|
800b9e0: d0f7 beq.n 800b9d2 <strstr+0x1a>
|
|
800b9e2: 4633 mov r3, r6
|
|
800b9e4: e7ec b.n 800b9c0 <strstr+0x8>
|
|
...
|
|
|
|
0800b9e8 <__swbuf_r>:
|
|
800b9e8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800b9ea: 460e mov r6, r1
|
|
800b9ec: 4614 mov r4, r2
|
|
800b9ee: 4605 mov r5, r0
|
|
800b9f0: b118 cbz r0, 800b9fa <__swbuf_r+0x12>
|
|
800b9f2: 6983 ldr r3, [r0, #24]
|
|
800b9f4: b90b cbnz r3, 800b9fa <__swbuf_r+0x12>
|
|
800b9f6: f001 f869 bl 800cacc <__sinit>
|
|
800b9fa: 4b21 ldr r3, [pc, #132] ; (800ba80 <__swbuf_r+0x98>)
|
|
800b9fc: 429c cmp r4, r3
|
|
800b9fe: d12b bne.n 800ba58 <__swbuf_r+0x70>
|
|
800ba00: 686c ldr r4, [r5, #4]
|
|
800ba02: 69a3 ldr r3, [r4, #24]
|
|
800ba04: 60a3 str r3, [r4, #8]
|
|
800ba06: 89a3 ldrh r3, [r4, #12]
|
|
800ba08: 071a lsls r2, r3, #28
|
|
800ba0a: d52f bpl.n 800ba6c <__swbuf_r+0x84>
|
|
800ba0c: 6923 ldr r3, [r4, #16]
|
|
800ba0e: b36b cbz r3, 800ba6c <__swbuf_r+0x84>
|
|
800ba10: 6923 ldr r3, [r4, #16]
|
|
800ba12: 6820 ldr r0, [r4, #0]
|
|
800ba14: 1ac0 subs r0, r0, r3
|
|
800ba16: 6963 ldr r3, [r4, #20]
|
|
800ba18: b2f6 uxtb r6, r6
|
|
800ba1a: 4283 cmp r3, r0
|
|
800ba1c: 4637 mov r7, r6
|
|
800ba1e: dc04 bgt.n 800ba2a <__swbuf_r+0x42>
|
|
800ba20: 4621 mov r1, r4
|
|
800ba22: 4628 mov r0, r5
|
|
800ba24: f000 ffbe bl 800c9a4 <_fflush_r>
|
|
800ba28: bb30 cbnz r0, 800ba78 <__swbuf_r+0x90>
|
|
800ba2a: 68a3 ldr r3, [r4, #8]
|
|
800ba2c: 3b01 subs r3, #1
|
|
800ba2e: 60a3 str r3, [r4, #8]
|
|
800ba30: 6823 ldr r3, [r4, #0]
|
|
800ba32: 1c5a adds r2, r3, #1
|
|
800ba34: 6022 str r2, [r4, #0]
|
|
800ba36: 701e strb r6, [r3, #0]
|
|
800ba38: 6963 ldr r3, [r4, #20]
|
|
800ba3a: 3001 adds r0, #1
|
|
800ba3c: 4283 cmp r3, r0
|
|
800ba3e: d004 beq.n 800ba4a <__swbuf_r+0x62>
|
|
800ba40: 89a3 ldrh r3, [r4, #12]
|
|
800ba42: 07db lsls r3, r3, #31
|
|
800ba44: d506 bpl.n 800ba54 <__swbuf_r+0x6c>
|
|
800ba46: 2e0a cmp r6, #10
|
|
800ba48: d104 bne.n 800ba54 <__swbuf_r+0x6c>
|
|
800ba4a: 4621 mov r1, r4
|
|
800ba4c: 4628 mov r0, r5
|
|
800ba4e: f000 ffa9 bl 800c9a4 <_fflush_r>
|
|
800ba52: b988 cbnz r0, 800ba78 <__swbuf_r+0x90>
|
|
800ba54: 4638 mov r0, r7
|
|
800ba56: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
800ba58: 4b0a ldr r3, [pc, #40] ; (800ba84 <__swbuf_r+0x9c>)
|
|
800ba5a: 429c cmp r4, r3
|
|
800ba5c: d101 bne.n 800ba62 <__swbuf_r+0x7a>
|
|
800ba5e: 68ac ldr r4, [r5, #8]
|
|
800ba60: e7cf b.n 800ba02 <__swbuf_r+0x1a>
|
|
800ba62: 4b09 ldr r3, [pc, #36] ; (800ba88 <__swbuf_r+0xa0>)
|
|
800ba64: 429c cmp r4, r3
|
|
800ba66: bf08 it eq
|
|
800ba68: 68ec ldreq r4, [r5, #12]
|
|
800ba6a: e7ca b.n 800ba02 <__swbuf_r+0x1a>
|
|
800ba6c: 4621 mov r1, r4
|
|
800ba6e: 4628 mov r0, r5
|
|
800ba70: f000 f80c bl 800ba8c <__swsetup_r>
|
|
800ba74: 2800 cmp r0, #0
|
|
800ba76: d0cb beq.n 800ba10 <__swbuf_r+0x28>
|
|
800ba78: f04f 37ff mov.w r7, #4294967295 ; 0xffffffff
|
|
800ba7c: e7ea b.n 800ba54 <__swbuf_r+0x6c>
|
|
800ba7e: bf00 nop
|
|
800ba80: 0800e620 .word 0x0800e620
|
|
800ba84: 0800e640 .word 0x0800e640
|
|
800ba88: 0800e600 .word 0x0800e600
|
|
|
|
0800ba8c <__swsetup_r>:
|
|
800ba8c: 4b32 ldr r3, [pc, #200] ; (800bb58 <__swsetup_r+0xcc>)
|
|
800ba8e: b570 push {r4, r5, r6, lr}
|
|
800ba90: 681d ldr r5, [r3, #0]
|
|
800ba92: 4606 mov r6, r0
|
|
800ba94: 460c mov r4, r1
|
|
800ba96: b125 cbz r5, 800baa2 <__swsetup_r+0x16>
|
|
800ba98: 69ab ldr r3, [r5, #24]
|
|
800ba9a: b913 cbnz r3, 800baa2 <__swsetup_r+0x16>
|
|
800ba9c: 4628 mov r0, r5
|
|
800ba9e: f001 f815 bl 800cacc <__sinit>
|
|
800baa2: 4b2e ldr r3, [pc, #184] ; (800bb5c <__swsetup_r+0xd0>)
|
|
800baa4: 429c cmp r4, r3
|
|
800baa6: d10f bne.n 800bac8 <__swsetup_r+0x3c>
|
|
800baa8: 686c ldr r4, [r5, #4]
|
|
800baaa: 89a3 ldrh r3, [r4, #12]
|
|
800baac: f9b4 200c ldrsh.w r2, [r4, #12]
|
|
800bab0: 0719 lsls r1, r3, #28
|
|
800bab2: d42c bmi.n 800bb0e <__swsetup_r+0x82>
|
|
800bab4: 06dd lsls r5, r3, #27
|
|
800bab6: d411 bmi.n 800badc <__swsetup_r+0x50>
|
|
800bab8: 2309 movs r3, #9
|
|
800baba: 6033 str r3, [r6, #0]
|
|
800babc: f042 0340 orr.w r3, r2, #64 ; 0x40
|
|
800bac0: 81a3 strh r3, [r4, #12]
|
|
800bac2: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800bac6: e03e b.n 800bb46 <__swsetup_r+0xba>
|
|
800bac8: 4b25 ldr r3, [pc, #148] ; (800bb60 <__swsetup_r+0xd4>)
|
|
800baca: 429c cmp r4, r3
|
|
800bacc: d101 bne.n 800bad2 <__swsetup_r+0x46>
|
|
800bace: 68ac ldr r4, [r5, #8]
|
|
800bad0: e7eb b.n 800baaa <__swsetup_r+0x1e>
|
|
800bad2: 4b24 ldr r3, [pc, #144] ; (800bb64 <__swsetup_r+0xd8>)
|
|
800bad4: 429c cmp r4, r3
|
|
800bad6: bf08 it eq
|
|
800bad8: 68ec ldreq r4, [r5, #12]
|
|
800bada: e7e6 b.n 800baaa <__swsetup_r+0x1e>
|
|
800badc: 0758 lsls r0, r3, #29
|
|
800bade: d512 bpl.n 800bb06 <__swsetup_r+0x7a>
|
|
800bae0: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
800bae2: b141 cbz r1, 800baf6 <__swsetup_r+0x6a>
|
|
800bae4: f104 0344 add.w r3, r4, #68 ; 0x44
|
|
800bae8: 4299 cmp r1, r3
|
|
800baea: d002 beq.n 800baf2 <__swsetup_r+0x66>
|
|
800baec: 4630 mov r0, r6
|
|
800baee: f001 fc9f bl 800d430 <_free_r>
|
|
800baf2: 2300 movs r3, #0
|
|
800baf4: 6363 str r3, [r4, #52] ; 0x34
|
|
800baf6: 89a3 ldrh r3, [r4, #12]
|
|
800baf8: f023 0324 bic.w r3, r3, #36 ; 0x24
|
|
800bafc: 81a3 strh r3, [r4, #12]
|
|
800bafe: 2300 movs r3, #0
|
|
800bb00: 6063 str r3, [r4, #4]
|
|
800bb02: 6923 ldr r3, [r4, #16]
|
|
800bb04: 6023 str r3, [r4, #0]
|
|
800bb06: 89a3 ldrh r3, [r4, #12]
|
|
800bb08: f043 0308 orr.w r3, r3, #8
|
|
800bb0c: 81a3 strh r3, [r4, #12]
|
|
800bb0e: 6923 ldr r3, [r4, #16]
|
|
800bb10: b94b cbnz r3, 800bb26 <__swsetup_r+0x9a>
|
|
800bb12: 89a3 ldrh r3, [r4, #12]
|
|
800bb14: f403 7320 and.w r3, r3, #640 ; 0x280
|
|
800bb18: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
800bb1c: d003 beq.n 800bb26 <__swsetup_r+0x9a>
|
|
800bb1e: 4621 mov r1, r4
|
|
800bb20: 4630 mov r0, r6
|
|
800bb22: f001 f8af bl 800cc84 <__smakebuf_r>
|
|
800bb26: 89a0 ldrh r0, [r4, #12]
|
|
800bb28: f9b4 200c ldrsh.w r2, [r4, #12]
|
|
800bb2c: f010 0301 ands.w r3, r0, #1
|
|
800bb30: d00a beq.n 800bb48 <__swsetup_r+0xbc>
|
|
800bb32: 2300 movs r3, #0
|
|
800bb34: 60a3 str r3, [r4, #8]
|
|
800bb36: 6963 ldr r3, [r4, #20]
|
|
800bb38: 425b negs r3, r3
|
|
800bb3a: 61a3 str r3, [r4, #24]
|
|
800bb3c: 6923 ldr r3, [r4, #16]
|
|
800bb3e: b943 cbnz r3, 800bb52 <__swsetup_r+0xc6>
|
|
800bb40: f010 0080 ands.w r0, r0, #128 ; 0x80
|
|
800bb44: d1ba bne.n 800babc <__swsetup_r+0x30>
|
|
800bb46: bd70 pop {r4, r5, r6, pc}
|
|
800bb48: 0781 lsls r1, r0, #30
|
|
800bb4a: bf58 it pl
|
|
800bb4c: 6963 ldrpl r3, [r4, #20]
|
|
800bb4e: 60a3 str r3, [r4, #8]
|
|
800bb50: e7f4 b.n 800bb3c <__swsetup_r+0xb0>
|
|
800bb52: 2000 movs r0, #0
|
|
800bb54: e7f7 b.n 800bb46 <__swsetup_r+0xba>
|
|
800bb56: bf00 nop
|
|
800bb58: 20000278 .word 0x20000278
|
|
800bb5c: 0800e620 .word 0x0800e620
|
|
800bb60: 0800e640 .word 0x0800e640
|
|
800bb64: 0800e600 .word 0x0800e600
|
|
|
|
0800bb68 <__assert_func>:
|
|
800bb68: b51f push {r0, r1, r2, r3, r4, lr}
|
|
800bb6a: 4614 mov r4, r2
|
|
800bb6c: 461a mov r2, r3
|
|
800bb6e: 4b09 ldr r3, [pc, #36] ; (800bb94 <__assert_func+0x2c>)
|
|
800bb70: 681b ldr r3, [r3, #0]
|
|
800bb72: 4605 mov r5, r0
|
|
800bb74: 68d8 ldr r0, [r3, #12]
|
|
800bb76: b14c cbz r4, 800bb8c <__assert_func+0x24>
|
|
800bb78: 4b07 ldr r3, [pc, #28] ; (800bb98 <__assert_func+0x30>)
|
|
800bb7a: 9100 str r1, [sp, #0]
|
|
800bb7c: e9cd 3401 strd r3, r4, [sp, #4]
|
|
800bb80: 4906 ldr r1, [pc, #24] ; (800bb9c <__assert_func+0x34>)
|
|
800bb82: 462b mov r3, r5
|
|
800bb84: f001 f820 bl 800cbc8 <fiprintf>
|
|
800bb88: f002 f818 bl 800dbbc <abort>
|
|
800bb8c: 4b04 ldr r3, [pc, #16] ; (800bba0 <__assert_func+0x38>)
|
|
800bb8e: 461c mov r4, r3
|
|
800bb90: e7f3 b.n 800bb7a <__assert_func+0x12>
|
|
800bb92: bf00 nop
|
|
800bb94: 20000278 .word 0x20000278
|
|
800bb98: 0800e42c .word 0x0800e42c
|
|
800bb9c: 0800e439 .word 0x0800e439
|
|
800bba0: 0800e467 .word 0x0800e467
|
|
|
|
0800bba4 <quorem>:
|
|
800bba4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800bba8: 6903 ldr r3, [r0, #16]
|
|
800bbaa: 690c ldr r4, [r1, #16]
|
|
800bbac: 42a3 cmp r3, r4
|
|
800bbae: 4607 mov r7, r0
|
|
800bbb0: f2c0 8081 blt.w 800bcb6 <quorem+0x112>
|
|
800bbb4: 3c01 subs r4, #1
|
|
800bbb6: f101 0814 add.w r8, r1, #20
|
|
800bbba: f100 0514 add.w r5, r0, #20
|
|
800bbbe: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
800bbc2: 9301 str r3, [sp, #4]
|
|
800bbc4: f858 3024 ldr.w r3, [r8, r4, lsl #2]
|
|
800bbc8: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
800bbcc: 3301 adds r3, #1
|
|
800bbce: 429a cmp r2, r3
|
|
800bbd0: ea4f 0b84 mov.w fp, r4, lsl #2
|
|
800bbd4: eb08 0984 add.w r9, r8, r4, lsl #2
|
|
800bbd8: fbb2 f6f3 udiv r6, r2, r3
|
|
800bbdc: d331 bcc.n 800bc42 <quorem+0x9e>
|
|
800bbde: f04f 0e00 mov.w lr, #0
|
|
800bbe2: 4640 mov r0, r8
|
|
800bbe4: 46ac mov ip, r5
|
|
800bbe6: 46f2 mov sl, lr
|
|
800bbe8: f850 2b04 ldr.w r2, [r0], #4
|
|
800bbec: b293 uxth r3, r2
|
|
800bbee: fb06 e303 mla r3, r6, r3, lr
|
|
800bbf2: ea4f 4e13 mov.w lr, r3, lsr #16
|
|
800bbf6: b29b uxth r3, r3
|
|
800bbf8: ebaa 0303 sub.w r3, sl, r3
|
|
800bbfc: 0c12 lsrs r2, r2, #16
|
|
800bbfe: f8dc a000 ldr.w sl, [ip]
|
|
800bc02: fb06 e202 mla r2, r6, r2, lr
|
|
800bc06: fa13 f38a uxtah r3, r3, sl
|
|
800bc0a: ea4f 4e12 mov.w lr, r2, lsr #16
|
|
800bc0e: fa1f fa82 uxth.w sl, r2
|
|
800bc12: f8dc 2000 ldr.w r2, [ip]
|
|
800bc16: ebca 4212 rsb r2, sl, r2, lsr #16
|
|
800bc1a: eb02 4223 add.w r2, r2, r3, asr #16
|
|
800bc1e: b29b uxth r3, r3
|
|
800bc20: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
800bc24: 4581 cmp r9, r0
|
|
800bc26: f84c 3b04 str.w r3, [ip], #4
|
|
800bc2a: ea4f 4a22 mov.w sl, r2, asr #16
|
|
800bc2e: d2db bcs.n 800bbe8 <quorem+0x44>
|
|
800bc30: f855 300b ldr.w r3, [r5, fp]
|
|
800bc34: b92b cbnz r3, 800bc42 <quorem+0x9e>
|
|
800bc36: 9b01 ldr r3, [sp, #4]
|
|
800bc38: 3b04 subs r3, #4
|
|
800bc3a: 429d cmp r5, r3
|
|
800bc3c: 461a mov r2, r3
|
|
800bc3e: d32e bcc.n 800bc9e <quorem+0xfa>
|
|
800bc40: 613c str r4, [r7, #16]
|
|
800bc42: 4638 mov r0, r7
|
|
800bc44: f001 fae4 bl 800d210 <__mcmp>
|
|
800bc48: 2800 cmp r0, #0
|
|
800bc4a: db24 blt.n 800bc96 <quorem+0xf2>
|
|
800bc4c: 3601 adds r6, #1
|
|
800bc4e: 4628 mov r0, r5
|
|
800bc50: f04f 0c00 mov.w ip, #0
|
|
800bc54: f858 2b04 ldr.w r2, [r8], #4
|
|
800bc58: f8d0 e000 ldr.w lr, [r0]
|
|
800bc5c: b293 uxth r3, r2
|
|
800bc5e: ebac 0303 sub.w r3, ip, r3
|
|
800bc62: 0c12 lsrs r2, r2, #16
|
|
800bc64: fa13 f38e uxtah r3, r3, lr
|
|
800bc68: ebc2 421e rsb r2, r2, lr, lsr #16
|
|
800bc6c: eb02 4223 add.w r2, r2, r3, asr #16
|
|
800bc70: b29b uxth r3, r3
|
|
800bc72: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
800bc76: 45c1 cmp r9, r8
|
|
800bc78: f840 3b04 str.w r3, [r0], #4
|
|
800bc7c: ea4f 4c22 mov.w ip, r2, asr #16
|
|
800bc80: d2e8 bcs.n 800bc54 <quorem+0xb0>
|
|
800bc82: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
800bc86: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
800bc8a: b922 cbnz r2, 800bc96 <quorem+0xf2>
|
|
800bc8c: 3b04 subs r3, #4
|
|
800bc8e: 429d cmp r5, r3
|
|
800bc90: 461a mov r2, r3
|
|
800bc92: d30a bcc.n 800bcaa <quorem+0x106>
|
|
800bc94: 613c str r4, [r7, #16]
|
|
800bc96: 4630 mov r0, r6
|
|
800bc98: b003 add sp, #12
|
|
800bc9a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800bc9e: 6812 ldr r2, [r2, #0]
|
|
800bca0: 3b04 subs r3, #4
|
|
800bca2: 2a00 cmp r2, #0
|
|
800bca4: d1cc bne.n 800bc40 <quorem+0x9c>
|
|
800bca6: 3c01 subs r4, #1
|
|
800bca8: e7c7 b.n 800bc3a <quorem+0x96>
|
|
800bcaa: 6812 ldr r2, [r2, #0]
|
|
800bcac: 3b04 subs r3, #4
|
|
800bcae: 2a00 cmp r2, #0
|
|
800bcb0: d1f0 bne.n 800bc94 <quorem+0xf0>
|
|
800bcb2: 3c01 subs r4, #1
|
|
800bcb4: e7eb b.n 800bc8e <quorem+0xea>
|
|
800bcb6: 2000 movs r0, #0
|
|
800bcb8: e7ee b.n 800bc98 <quorem+0xf4>
|
|
800bcba: 0000 movs r0, r0
|
|
800bcbc: 0000 movs r0, r0
|
|
...
|
|
|
|
0800bcc0 <_dtoa_r>:
|
|
800bcc0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800bcc4: ed2d 8b02 vpush {d8}
|
|
800bcc8: ec57 6b10 vmov r6, r7, d0
|
|
800bccc: b095 sub sp, #84 ; 0x54
|
|
800bcce: 6a45 ldr r5, [r0, #36] ; 0x24
|
|
800bcd0: f8dd 8080 ldr.w r8, [sp, #128] ; 0x80
|
|
800bcd4: 9105 str r1, [sp, #20]
|
|
800bcd6: e9cd 6702 strd r6, r7, [sp, #8]
|
|
800bcda: 4604 mov r4, r0
|
|
800bcdc: 9209 str r2, [sp, #36] ; 0x24
|
|
800bcde: 930f str r3, [sp, #60] ; 0x3c
|
|
800bce0: b975 cbnz r5, 800bd00 <_dtoa_r+0x40>
|
|
800bce2: 2010 movs r0, #16
|
|
800bce4: f001 f80e bl 800cd04 <malloc>
|
|
800bce8: 4602 mov r2, r0
|
|
800bcea: 6260 str r0, [r4, #36] ; 0x24
|
|
800bcec: b920 cbnz r0, 800bcf8 <_dtoa_r+0x38>
|
|
800bcee: 4bb2 ldr r3, [pc, #712] ; (800bfb8 <_dtoa_r+0x2f8>)
|
|
800bcf0: 21ea movs r1, #234 ; 0xea
|
|
800bcf2: 48b2 ldr r0, [pc, #712] ; (800bfbc <_dtoa_r+0x2fc>)
|
|
800bcf4: f7ff ff38 bl 800bb68 <__assert_func>
|
|
800bcf8: e9c0 5501 strd r5, r5, [r0, #4]
|
|
800bcfc: 6005 str r5, [r0, #0]
|
|
800bcfe: 60c5 str r5, [r0, #12]
|
|
800bd00: 6a63 ldr r3, [r4, #36] ; 0x24
|
|
800bd02: 6819 ldr r1, [r3, #0]
|
|
800bd04: b151 cbz r1, 800bd1c <_dtoa_r+0x5c>
|
|
800bd06: 685a ldr r2, [r3, #4]
|
|
800bd08: 604a str r2, [r1, #4]
|
|
800bd0a: 2301 movs r3, #1
|
|
800bd0c: 4093 lsls r3, r2
|
|
800bd0e: 608b str r3, [r1, #8]
|
|
800bd10: 4620 mov r0, r4
|
|
800bd12: f001 f83f bl 800cd94 <_Bfree>
|
|
800bd16: 6a63 ldr r3, [r4, #36] ; 0x24
|
|
800bd18: 2200 movs r2, #0
|
|
800bd1a: 601a str r2, [r3, #0]
|
|
800bd1c: 1e3b subs r3, r7, #0
|
|
800bd1e: bfb9 ittee lt
|
|
800bd20: f023 4300 biclt.w r3, r3, #2147483648 ; 0x80000000
|
|
800bd24: 9303 strlt r3, [sp, #12]
|
|
800bd26: 2300 movge r3, #0
|
|
800bd28: f8c8 3000 strge.w r3, [r8]
|
|
800bd2c: f8dd 900c ldr.w r9, [sp, #12]
|
|
800bd30: 4ba3 ldr r3, [pc, #652] ; (800bfc0 <_dtoa_r+0x300>)
|
|
800bd32: bfbc itt lt
|
|
800bd34: 2201 movlt r2, #1
|
|
800bd36: f8c8 2000 strlt.w r2, [r8]
|
|
800bd3a: ea33 0309 bics.w r3, r3, r9
|
|
800bd3e: d11b bne.n 800bd78 <_dtoa_r+0xb8>
|
|
800bd40: 9a0f ldr r2, [sp, #60] ; 0x3c
|
|
800bd42: f242 730f movw r3, #9999 ; 0x270f
|
|
800bd46: 6013 str r3, [r2, #0]
|
|
800bd48: f3c9 0313 ubfx r3, r9, #0, #20
|
|
800bd4c: 4333 orrs r3, r6
|
|
800bd4e: f000 857a beq.w 800c846 <_dtoa_r+0xb86>
|
|
800bd52: 9b21 ldr r3, [sp, #132] ; 0x84
|
|
800bd54: b963 cbnz r3, 800bd70 <_dtoa_r+0xb0>
|
|
800bd56: 4b9b ldr r3, [pc, #620] ; (800bfc4 <_dtoa_r+0x304>)
|
|
800bd58: e024 b.n 800bda4 <_dtoa_r+0xe4>
|
|
800bd5a: 4b9b ldr r3, [pc, #620] ; (800bfc8 <_dtoa_r+0x308>)
|
|
800bd5c: 9300 str r3, [sp, #0]
|
|
800bd5e: 3308 adds r3, #8
|
|
800bd60: 9a21 ldr r2, [sp, #132] ; 0x84
|
|
800bd62: 6013 str r3, [r2, #0]
|
|
800bd64: 9800 ldr r0, [sp, #0]
|
|
800bd66: b015 add sp, #84 ; 0x54
|
|
800bd68: ecbd 8b02 vpop {d8}
|
|
800bd6c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800bd70: 4b94 ldr r3, [pc, #592] ; (800bfc4 <_dtoa_r+0x304>)
|
|
800bd72: 9300 str r3, [sp, #0]
|
|
800bd74: 3303 adds r3, #3
|
|
800bd76: e7f3 b.n 800bd60 <_dtoa_r+0xa0>
|
|
800bd78: ed9d 7b02 vldr d7, [sp, #8]
|
|
800bd7c: 2200 movs r2, #0
|
|
800bd7e: ec51 0b17 vmov r0, r1, d7
|
|
800bd82: 2300 movs r3, #0
|
|
800bd84: ed8d 7b0a vstr d7, [sp, #40] ; 0x28
|
|
800bd88: f7f4 fe9e bl 8000ac8 <__aeabi_dcmpeq>
|
|
800bd8c: 4680 mov r8, r0
|
|
800bd8e: b158 cbz r0, 800bda8 <_dtoa_r+0xe8>
|
|
800bd90: 9a0f ldr r2, [sp, #60] ; 0x3c
|
|
800bd92: 2301 movs r3, #1
|
|
800bd94: 6013 str r3, [r2, #0]
|
|
800bd96: 9b21 ldr r3, [sp, #132] ; 0x84
|
|
800bd98: 2b00 cmp r3, #0
|
|
800bd9a: f000 8551 beq.w 800c840 <_dtoa_r+0xb80>
|
|
800bd9e: 488b ldr r0, [pc, #556] ; (800bfcc <_dtoa_r+0x30c>)
|
|
800bda0: 6018 str r0, [r3, #0]
|
|
800bda2: 1e43 subs r3, r0, #1
|
|
800bda4: 9300 str r3, [sp, #0]
|
|
800bda6: e7dd b.n 800bd64 <_dtoa_r+0xa4>
|
|
800bda8: ed9d 0b0a vldr d0, [sp, #40] ; 0x28
|
|
800bdac: aa12 add r2, sp, #72 ; 0x48
|
|
800bdae: a913 add r1, sp, #76 ; 0x4c
|
|
800bdb0: 4620 mov r0, r4
|
|
800bdb2: f001 fad1 bl 800d358 <__d2b>
|
|
800bdb6: f3c9 550a ubfx r5, r9, #20, #11
|
|
800bdba: 4683 mov fp, r0
|
|
800bdbc: 2d00 cmp r5, #0
|
|
800bdbe: d07c beq.n 800beba <_dtoa_r+0x1fa>
|
|
800bdc0: 9b0b ldr r3, [sp, #44] ; 0x2c
|
|
800bdc2: f8cd 8040 str.w r8, [sp, #64] ; 0x40
|
|
800bdc6: f3c3 0313 ubfx r3, r3, #0, #20
|
|
800bdca: e9dd 670a ldrd r6, r7, [sp, #40] ; 0x28
|
|
800bdce: f043 577f orr.w r7, r3, #1069547520 ; 0x3fc00000
|
|
800bdd2: f447 1740 orr.w r7, r7, #3145728 ; 0x300000
|
|
800bdd6: f2a5 35ff subw r5, r5, #1023 ; 0x3ff
|
|
800bdda: 4b7d ldr r3, [pc, #500] ; (800bfd0 <_dtoa_r+0x310>)
|
|
800bddc: 2200 movs r2, #0
|
|
800bdde: 4630 mov r0, r6
|
|
800bde0: 4639 mov r1, r7
|
|
800bde2: f7f4 fa51 bl 8000288 <__aeabi_dsub>
|
|
800bde6: a36e add r3, pc, #440 ; (adr r3, 800bfa0 <_dtoa_r+0x2e0>)
|
|
800bde8: e9d3 2300 ldrd r2, r3, [r3]
|
|
800bdec: f7f4 fc04 bl 80005f8 <__aeabi_dmul>
|
|
800bdf0: a36d add r3, pc, #436 ; (adr r3, 800bfa8 <_dtoa_r+0x2e8>)
|
|
800bdf2: e9d3 2300 ldrd r2, r3, [r3]
|
|
800bdf6: f7f4 fa49 bl 800028c <__adddf3>
|
|
800bdfa: 4606 mov r6, r0
|
|
800bdfc: 4628 mov r0, r5
|
|
800bdfe: 460f mov r7, r1
|
|
800be00: f7f4 fb90 bl 8000524 <__aeabi_i2d>
|
|
800be04: a36a add r3, pc, #424 ; (adr r3, 800bfb0 <_dtoa_r+0x2f0>)
|
|
800be06: e9d3 2300 ldrd r2, r3, [r3]
|
|
800be0a: f7f4 fbf5 bl 80005f8 <__aeabi_dmul>
|
|
800be0e: 4602 mov r2, r0
|
|
800be10: 460b mov r3, r1
|
|
800be12: 4630 mov r0, r6
|
|
800be14: 4639 mov r1, r7
|
|
800be16: f7f4 fa39 bl 800028c <__adddf3>
|
|
800be1a: 4606 mov r6, r0
|
|
800be1c: 460f mov r7, r1
|
|
800be1e: f7f4 fe9b bl 8000b58 <__aeabi_d2iz>
|
|
800be22: 2200 movs r2, #0
|
|
800be24: 4682 mov sl, r0
|
|
800be26: 2300 movs r3, #0
|
|
800be28: 4630 mov r0, r6
|
|
800be2a: 4639 mov r1, r7
|
|
800be2c: f7f4 fe56 bl 8000adc <__aeabi_dcmplt>
|
|
800be30: b148 cbz r0, 800be46 <_dtoa_r+0x186>
|
|
800be32: 4650 mov r0, sl
|
|
800be34: f7f4 fb76 bl 8000524 <__aeabi_i2d>
|
|
800be38: 4632 mov r2, r6
|
|
800be3a: 463b mov r3, r7
|
|
800be3c: f7f4 fe44 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800be40: b908 cbnz r0, 800be46 <_dtoa_r+0x186>
|
|
800be42: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff
|
|
800be46: f1ba 0f16 cmp.w sl, #22
|
|
800be4a: d854 bhi.n 800bef6 <_dtoa_r+0x236>
|
|
800be4c: 4b61 ldr r3, [pc, #388] ; (800bfd4 <_dtoa_r+0x314>)
|
|
800be4e: eb03 03ca add.w r3, r3, sl, lsl #3
|
|
800be52: e9d3 2300 ldrd r2, r3, [r3]
|
|
800be56: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
|
|
800be5a: f7f4 fe3f bl 8000adc <__aeabi_dcmplt>
|
|
800be5e: 2800 cmp r0, #0
|
|
800be60: d04b beq.n 800befa <_dtoa_r+0x23a>
|
|
800be62: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff
|
|
800be66: 2300 movs r3, #0
|
|
800be68: 930e str r3, [sp, #56] ; 0x38
|
|
800be6a: 9b12 ldr r3, [sp, #72] ; 0x48
|
|
800be6c: 1b5d subs r5, r3, r5
|
|
800be6e: 1e6b subs r3, r5, #1
|
|
800be70: 9304 str r3, [sp, #16]
|
|
800be72: bf43 ittte mi
|
|
800be74: 2300 movmi r3, #0
|
|
800be76: f1c5 0801 rsbmi r8, r5, #1
|
|
800be7a: 9304 strmi r3, [sp, #16]
|
|
800be7c: f04f 0800 movpl.w r8, #0
|
|
800be80: f1ba 0f00 cmp.w sl, #0
|
|
800be84: db3b blt.n 800befe <_dtoa_r+0x23e>
|
|
800be86: 9b04 ldr r3, [sp, #16]
|
|
800be88: f8cd a034 str.w sl, [sp, #52] ; 0x34
|
|
800be8c: 4453 add r3, sl
|
|
800be8e: 9304 str r3, [sp, #16]
|
|
800be90: 2300 movs r3, #0
|
|
800be92: 9306 str r3, [sp, #24]
|
|
800be94: 9b05 ldr r3, [sp, #20]
|
|
800be96: 2b09 cmp r3, #9
|
|
800be98: d869 bhi.n 800bf6e <_dtoa_r+0x2ae>
|
|
800be9a: 2b05 cmp r3, #5
|
|
800be9c: bfc4 itt gt
|
|
800be9e: 3b04 subgt r3, #4
|
|
800bea0: 9305 strgt r3, [sp, #20]
|
|
800bea2: 9b05 ldr r3, [sp, #20]
|
|
800bea4: f1a3 0302 sub.w r3, r3, #2
|
|
800bea8: bfcc ite gt
|
|
800beaa: 2500 movgt r5, #0
|
|
800beac: 2501 movle r5, #1
|
|
800beae: 2b03 cmp r3, #3
|
|
800beb0: d869 bhi.n 800bf86 <_dtoa_r+0x2c6>
|
|
800beb2: e8df f003 tbb [pc, r3]
|
|
800beb6: 4e2c .short 0x4e2c
|
|
800beb8: 5a4c .short 0x5a4c
|
|
800beba: e9dd 5312 ldrd r5, r3, [sp, #72] ; 0x48
|
|
800bebe: 441d add r5, r3
|
|
800bec0: f205 4332 addw r3, r5, #1074 ; 0x432
|
|
800bec4: 2b20 cmp r3, #32
|
|
800bec6: bfc1 itttt gt
|
|
800bec8: f1c3 0340 rsbgt r3, r3, #64 ; 0x40
|
|
800becc: f205 4012 addwgt r0, r5, #1042 ; 0x412
|
|
800bed0: fa09 f303 lslgt.w r3, r9, r3
|
|
800bed4: fa26 f000 lsrgt.w r0, r6, r0
|
|
800bed8: bfda itte le
|
|
800beda: f1c3 0320 rsble r3, r3, #32
|
|
800bede: fa06 f003 lslle.w r0, r6, r3
|
|
800bee2: 4318 orrgt r0, r3
|
|
800bee4: f7f4 fb0e bl 8000504 <__aeabi_ui2d>
|
|
800bee8: 2301 movs r3, #1
|
|
800beea: 4606 mov r6, r0
|
|
800beec: f1a1 77f8 sub.w r7, r1, #32505856 ; 0x1f00000
|
|
800bef0: 3d01 subs r5, #1
|
|
800bef2: 9310 str r3, [sp, #64] ; 0x40
|
|
800bef4: e771 b.n 800bdda <_dtoa_r+0x11a>
|
|
800bef6: 2301 movs r3, #1
|
|
800bef8: e7b6 b.n 800be68 <_dtoa_r+0x1a8>
|
|
800befa: 900e str r0, [sp, #56] ; 0x38
|
|
800befc: e7b5 b.n 800be6a <_dtoa_r+0x1aa>
|
|
800befe: f1ca 0300 rsb r3, sl, #0
|
|
800bf02: 9306 str r3, [sp, #24]
|
|
800bf04: 2300 movs r3, #0
|
|
800bf06: eba8 080a sub.w r8, r8, sl
|
|
800bf0a: 930d str r3, [sp, #52] ; 0x34
|
|
800bf0c: e7c2 b.n 800be94 <_dtoa_r+0x1d4>
|
|
800bf0e: 2300 movs r3, #0
|
|
800bf10: 9308 str r3, [sp, #32]
|
|
800bf12: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800bf14: 2b00 cmp r3, #0
|
|
800bf16: dc39 bgt.n 800bf8c <_dtoa_r+0x2cc>
|
|
800bf18: f04f 0901 mov.w r9, #1
|
|
800bf1c: f8cd 9004 str.w r9, [sp, #4]
|
|
800bf20: 464b mov r3, r9
|
|
800bf22: f8cd 9024 str.w r9, [sp, #36] ; 0x24
|
|
800bf26: 6a60 ldr r0, [r4, #36] ; 0x24
|
|
800bf28: 2200 movs r2, #0
|
|
800bf2a: 6042 str r2, [r0, #4]
|
|
800bf2c: 2204 movs r2, #4
|
|
800bf2e: f102 0614 add.w r6, r2, #20
|
|
800bf32: 429e cmp r6, r3
|
|
800bf34: 6841 ldr r1, [r0, #4]
|
|
800bf36: d92f bls.n 800bf98 <_dtoa_r+0x2d8>
|
|
800bf38: 4620 mov r0, r4
|
|
800bf3a: f000 feeb bl 800cd14 <_Balloc>
|
|
800bf3e: 9000 str r0, [sp, #0]
|
|
800bf40: 2800 cmp r0, #0
|
|
800bf42: d14b bne.n 800bfdc <_dtoa_r+0x31c>
|
|
800bf44: 4b24 ldr r3, [pc, #144] ; (800bfd8 <_dtoa_r+0x318>)
|
|
800bf46: 4602 mov r2, r0
|
|
800bf48: f44f 71d5 mov.w r1, #426 ; 0x1aa
|
|
800bf4c: e6d1 b.n 800bcf2 <_dtoa_r+0x32>
|
|
800bf4e: 2301 movs r3, #1
|
|
800bf50: e7de b.n 800bf10 <_dtoa_r+0x250>
|
|
800bf52: 2300 movs r3, #0
|
|
800bf54: 9308 str r3, [sp, #32]
|
|
800bf56: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800bf58: eb0a 0903 add.w r9, sl, r3
|
|
800bf5c: f109 0301 add.w r3, r9, #1
|
|
800bf60: 2b01 cmp r3, #1
|
|
800bf62: 9301 str r3, [sp, #4]
|
|
800bf64: bfb8 it lt
|
|
800bf66: 2301 movlt r3, #1
|
|
800bf68: e7dd b.n 800bf26 <_dtoa_r+0x266>
|
|
800bf6a: 2301 movs r3, #1
|
|
800bf6c: e7f2 b.n 800bf54 <_dtoa_r+0x294>
|
|
800bf6e: 2501 movs r5, #1
|
|
800bf70: 2300 movs r3, #0
|
|
800bf72: 9305 str r3, [sp, #20]
|
|
800bf74: 9508 str r5, [sp, #32]
|
|
800bf76: f04f 39ff mov.w r9, #4294967295 ; 0xffffffff
|
|
800bf7a: 2200 movs r2, #0
|
|
800bf7c: f8cd 9004 str.w r9, [sp, #4]
|
|
800bf80: 2312 movs r3, #18
|
|
800bf82: 9209 str r2, [sp, #36] ; 0x24
|
|
800bf84: e7cf b.n 800bf26 <_dtoa_r+0x266>
|
|
800bf86: 2301 movs r3, #1
|
|
800bf88: 9308 str r3, [sp, #32]
|
|
800bf8a: e7f4 b.n 800bf76 <_dtoa_r+0x2b6>
|
|
800bf8c: f8dd 9024 ldr.w r9, [sp, #36] ; 0x24
|
|
800bf90: f8cd 9004 str.w r9, [sp, #4]
|
|
800bf94: 464b mov r3, r9
|
|
800bf96: e7c6 b.n 800bf26 <_dtoa_r+0x266>
|
|
800bf98: 3101 adds r1, #1
|
|
800bf9a: 6041 str r1, [r0, #4]
|
|
800bf9c: 0052 lsls r2, r2, #1
|
|
800bf9e: e7c6 b.n 800bf2e <_dtoa_r+0x26e>
|
|
800bfa0: 636f4361 .word 0x636f4361
|
|
800bfa4: 3fd287a7 .word 0x3fd287a7
|
|
800bfa8: 8b60c8b3 .word 0x8b60c8b3
|
|
800bfac: 3fc68a28 .word 0x3fc68a28
|
|
800bfb0: 509f79fb .word 0x509f79fb
|
|
800bfb4: 3fd34413 .word 0x3fd34413
|
|
800bfb8: 0800e576 .word 0x0800e576
|
|
800bfbc: 0800e58d .word 0x0800e58d
|
|
800bfc0: 7ff00000 .word 0x7ff00000
|
|
800bfc4: 0800e572 .word 0x0800e572
|
|
800bfc8: 0800e569 .word 0x0800e569
|
|
800bfcc: 0800e409 .word 0x0800e409
|
|
800bfd0: 3ff80000 .word 0x3ff80000
|
|
800bfd4: 0800e6e8 .word 0x0800e6e8
|
|
800bfd8: 0800e5ec .word 0x0800e5ec
|
|
800bfdc: 6a63 ldr r3, [r4, #36] ; 0x24
|
|
800bfde: 9a00 ldr r2, [sp, #0]
|
|
800bfe0: 601a str r2, [r3, #0]
|
|
800bfe2: 9b01 ldr r3, [sp, #4]
|
|
800bfe4: 2b0e cmp r3, #14
|
|
800bfe6: f200 80ad bhi.w 800c144 <_dtoa_r+0x484>
|
|
800bfea: 2d00 cmp r5, #0
|
|
800bfec: f000 80aa beq.w 800c144 <_dtoa_r+0x484>
|
|
800bff0: f1ba 0f00 cmp.w sl, #0
|
|
800bff4: dd36 ble.n 800c064 <_dtoa_r+0x3a4>
|
|
800bff6: 4ac3 ldr r2, [pc, #780] ; (800c304 <_dtoa_r+0x644>)
|
|
800bff8: f00a 030f and.w r3, sl, #15
|
|
800bffc: eb02 03c3 add.w r3, r2, r3, lsl #3
|
|
800c000: ed93 7b00 vldr d7, [r3]
|
|
800c004: f41a 7f80 tst.w sl, #256 ; 0x100
|
|
800c008: ea4f 172a mov.w r7, sl, asr #4
|
|
800c00c: eeb0 8a47 vmov.f32 s16, s14
|
|
800c010: eef0 8a67 vmov.f32 s17, s15
|
|
800c014: d016 beq.n 800c044 <_dtoa_r+0x384>
|
|
800c016: 4bbc ldr r3, [pc, #752] ; (800c308 <_dtoa_r+0x648>)
|
|
800c018: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
|
|
800c01c: e9d3 2308 ldrd r2, r3, [r3, #32]
|
|
800c020: f7f4 fc14 bl 800084c <__aeabi_ddiv>
|
|
800c024: e9cd 0102 strd r0, r1, [sp, #8]
|
|
800c028: f007 070f and.w r7, r7, #15
|
|
800c02c: 2503 movs r5, #3
|
|
800c02e: 4eb6 ldr r6, [pc, #728] ; (800c308 <_dtoa_r+0x648>)
|
|
800c030: b957 cbnz r7, 800c048 <_dtoa_r+0x388>
|
|
800c032: e9dd 0102 ldrd r0, r1, [sp, #8]
|
|
800c036: ec53 2b18 vmov r2, r3, d8
|
|
800c03a: f7f4 fc07 bl 800084c <__aeabi_ddiv>
|
|
800c03e: e9cd 0102 strd r0, r1, [sp, #8]
|
|
800c042: e029 b.n 800c098 <_dtoa_r+0x3d8>
|
|
800c044: 2502 movs r5, #2
|
|
800c046: e7f2 b.n 800c02e <_dtoa_r+0x36e>
|
|
800c048: 07f9 lsls r1, r7, #31
|
|
800c04a: d508 bpl.n 800c05e <_dtoa_r+0x39e>
|
|
800c04c: ec51 0b18 vmov r0, r1, d8
|
|
800c050: e9d6 2300 ldrd r2, r3, [r6]
|
|
800c054: f7f4 fad0 bl 80005f8 <__aeabi_dmul>
|
|
800c058: ec41 0b18 vmov d8, r0, r1
|
|
800c05c: 3501 adds r5, #1
|
|
800c05e: 107f asrs r7, r7, #1
|
|
800c060: 3608 adds r6, #8
|
|
800c062: e7e5 b.n 800c030 <_dtoa_r+0x370>
|
|
800c064: f000 80a6 beq.w 800c1b4 <_dtoa_r+0x4f4>
|
|
800c068: f1ca 0600 rsb r6, sl, #0
|
|
800c06c: 4ba5 ldr r3, [pc, #660] ; (800c304 <_dtoa_r+0x644>)
|
|
800c06e: 4fa6 ldr r7, [pc, #664] ; (800c308 <_dtoa_r+0x648>)
|
|
800c070: f006 020f and.w r2, r6, #15
|
|
800c074: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
800c078: e9d3 2300 ldrd r2, r3, [r3]
|
|
800c07c: e9dd 010a ldrd r0, r1, [sp, #40] ; 0x28
|
|
800c080: f7f4 faba bl 80005f8 <__aeabi_dmul>
|
|
800c084: e9cd 0102 strd r0, r1, [sp, #8]
|
|
800c088: 1136 asrs r6, r6, #4
|
|
800c08a: 2300 movs r3, #0
|
|
800c08c: 2502 movs r5, #2
|
|
800c08e: 2e00 cmp r6, #0
|
|
800c090: f040 8085 bne.w 800c19e <_dtoa_r+0x4de>
|
|
800c094: 2b00 cmp r3, #0
|
|
800c096: d1d2 bne.n 800c03e <_dtoa_r+0x37e>
|
|
800c098: 9b0e ldr r3, [sp, #56] ; 0x38
|
|
800c09a: 2b00 cmp r3, #0
|
|
800c09c: f000 808c beq.w 800c1b8 <_dtoa_r+0x4f8>
|
|
800c0a0: e9dd 6702 ldrd r6, r7, [sp, #8]
|
|
800c0a4: 4b99 ldr r3, [pc, #612] ; (800c30c <_dtoa_r+0x64c>)
|
|
800c0a6: 2200 movs r2, #0
|
|
800c0a8: 4630 mov r0, r6
|
|
800c0aa: 4639 mov r1, r7
|
|
800c0ac: f7f4 fd16 bl 8000adc <__aeabi_dcmplt>
|
|
800c0b0: 2800 cmp r0, #0
|
|
800c0b2: f000 8081 beq.w 800c1b8 <_dtoa_r+0x4f8>
|
|
800c0b6: 9b01 ldr r3, [sp, #4]
|
|
800c0b8: 2b00 cmp r3, #0
|
|
800c0ba: d07d beq.n 800c1b8 <_dtoa_r+0x4f8>
|
|
800c0bc: f1b9 0f00 cmp.w r9, #0
|
|
800c0c0: dd3c ble.n 800c13c <_dtoa_r+0x47c>
|
|
800c0c2: f10a 33ff add.w r3, sl, #4294967295 ; 0xffffffff
|
|
800c0c6: 9307 str r3, [sp, #28]
|
|
800c0c8: 2200 movs r2, #0
|
|
800c0ca: 4b91 ldr r3, [pc, #580] ; (800c310 <_dtoa_r+0x650>)
|
|
800c0cc: 4630 mov r0, r6
|
|
800c0ce: 4639 mov r1, r7
|
|
800c0d0: f7f4 fa92 bl 80005f8 <__aeabi_dmul>
|
|
800c0d4: e9cd 0102 strd r0, r1, [sp, #8]
|
|
800c0d8: 3501 adds r5, #1
|
|
800c0da: f8cd 9030 str.w r9, [sp, #48] ; 0x30
|
|
800c0de: e9dd 6702 ldrd r6, r7, [sp, #8]
|
|
800c0e2: 4628 mov r0, r5
|
|
800c0e4: f7f4 fa1e bl 8000524 <__aeabi_i2d>
|
|
800c0e8: 4632 mov r2, r6
|
|
800c0ea: 463b mov r3, r7
|
|
800c0ec: f7f4 fa84 bl 80005f8 <__aeabi_dmul>
|
|
800c0f0: 4b88 ldr r3, [pc, #544] ; (800c314 <_dtoa_r+0x654>)
|
|
800c0f2: 2200 movs r2, #0
|
|
800c0f4: f7f4 f8ca bl 800028c <__adddf3>
|
|
800c0f8: f1a1 7350 sub.w r3, r1, #54525952 ; 0x3400000
|
|
800c0fc: e9cd 0102 strd r0, r1, [sp, #8]
|
|
800c100: 9303 str r3, [sp, #12]
|
|
800c102: 9b0c ldr r3, [sp, #48] ; 0x30
|
|
800c104: 2b00 cmp r3, #0
|
|
800c106: d15c bne.n 800c1c2 <_dtoa_r+0x502>
|
|
800c108: 4b83 ldr r3, [pc, #524] ; (800c318 <_dtoa_r+0x658>)
|
|
800c10a: 2200 movs r2, #0
|
|
800c10c: 4630 mov r0, r6
|
|
800c10e: 4639 mov r1, r7
|
|
800c110: f7f4 f8ba bl 8000288 <__aeabi_dsub>
|
|
800c114: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
800c118: 4606 mov r6, r0
|
|
800c11a: 460f mov r7, r1
|
|
800c11c: f7f4 fcfc bl 8000b18 <__aeabi_dcmpgt>
|
|
800c120: 2800 cmp r0, #0
|
|
800c122: f040 8296 bne.w 800c652 <_dtoa_r+0x992>
|
|
800c126: e9dd 2102 ldrd r2, r1, [sp, #8]
|
|
800c12a: 4630 mov r0, r6
|
|
800c12c: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000
|
|
800c130: 4639 mov r1, r7
|
|
800c132: f7f4 fcd3 bl 8000adc <__aeabi_dcmplt>
|
|
800c136: 2800 cmp r0, #0
|
|
800c138: f040 8288 bne.w 800c64c <_dtoa_r+0x98c>
|
|
800c13c: e9dd 230a ldrd r2, r3, [sp, #40] ; 0x28
|
|
800c140: e9cd 2302 strd r2, r3, [sp, #8]
|
|
800c144: 9b13 ldr r3, [sp, #76] ; 0x4c
|
|
800c146: 2b00 cmp r3, #0
|
|
800c148: f2c0 8158 blt.w 800c3fc <_dtoa_r+0x73c>
|
|
800c14c: f1ba 0f0e cmp.w sl, #14
|
|
800c150: f300 8154 bgt.w 800c3fc <_dtoa_r+0x73c>
|
|
800c154: 4b6b ldr r3, [pc, #428] ; (800c304 <_dtoa_r+0x644>)
|
|
800c156: eb03 03ca add.w r3, r3, sl, lsl #3
|
|
800c15a: e9d3 8900 ldrd r8, r9, [r3]
|
|
800c15e: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800c160: 2b00 cmp r3, #0
|
|
800c162: f280 80e3 bge.w 800c32c <_dtoa_r+0x66c>
|
|
800c166: 9b01 ldr r3, [sp, #4]
|
|
800c168: 2b00 cmp r3, #0
|
|
800c16a: f300 80df bgt.w 800c32c <_dtoa_r+0x66c>
|
|
800c16e: f040 826d bne.w 800c64c <_dtoa_r+0x98c>
|
|
800c172: 4b69 ldr r3, [pc, #420] ; (800c318 <_dtoa_r+0x658>)
|
|
800c174: 2200 movs r2, #0
|
|
800c176: 4640 mov r0, r8
|
|
800c178: 4649 mov r1, r9
|
|
800c17a: f7f4 fa3d bl 80005f8 <__aeabi_dmul>
|
|
800c17e: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
800c182: f7f4 fcbf bl 8000b04 <__aeabi_dcmpge>
|
|
800c186: 9e01 ldr r6, [sp, #4]
|
|
800c188: 4637 mov r7, r6
|
|
800c18a: 2800 cmp r0, #0
|
|
800c18c: f040 8243 bne.w 800c616 <_dtoa_r+0x956>
|
|
800c190: 9d00 ldr r5, [sp, #0]
|
|
800c192: 2331 movs r3, #49 ; 0x31
|
|
800c194: f805 3b01 strb.w r3, [r5], #1
|
|
800c198: f10a 0a01 add.w sl, sl, #1
|
|
800c19c: e23f b.n 800c61e <_dtoa_r+0x95e>
|
|
800c19e: 07f2 lsls r2, r6, #31
|
|
800c1a0: d505 bpl.n 800c1ae <_dtoa_r+0x4ee>
|
|
800c1a2: e9d7 2300 ldrd r2, r3, [r7]
|
|
800c1a6: f7f4 fa27 bl 80005f8 <__aeabi_dmul>
|
|
800c1aa: 3501 adds r5, #1
|
|
800c1ac: 2301 movs r3, #1
|
|
800c1ae: 1076 asrs r6, r6, #1
|
|
800c1b0: 3708 adds r7, #8
|
|
800c1b2: e76c b.n 800c08e <_dtoa_r+0x3ce>
|
|
800c1b4: 2502 movs r5, #2
|
|
800c1b6: e76f b.n 800c098 <_dtoa_r+0x3d8>
|
|
800c1b8: 9b01 ldr r3, [sp, #4]
|
|
800c1ba: f8cd a01c str.w sl, [sp, #28]
|
|
800c1be: 930c str r3, [sp, #48] ; 0x30
|
|
800c1c0: e78d b.n 800c0de <_dtoa_r+0x41e>
|
|
800c1c2: 9900 ldr r1, [sp, #0]
|
|
800c1c4: 980c ldr r0, [sp, #48] ; 0x30
|
|
800c1c6: 9a0c ldr r2, [sp, #48] ; 0x30
|
|
800c1c8: 4b4e ldr r3, [pc, #312] ; (800c304 <_dtoa_r+0x644>)
|
|
800c1ca: ed9d 7b02 vldr d7, [sp, #8]
|
|
800c1ce: 4401 add r1, r0
|
|
800c1d0: 9102 str r1, [sp, #8]
|
|
800c1d2: 9908 ldr r1, [sp, #32]
|
|
800c1d4: eeb0 8a47 vmov.f32 s16, s14
|
|
800c1d8: eef0 8a67 vmov.f32 s17, s15
|
|
800c1dc: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
800c1e0: e953 2302 ldrd r2, r3, [r3, #-8]
|
|
800c1e4: 2900 cmp r1, #0
|
|
800c1e6: d045 beq.n 800c274 <_dtoa_r+0x5b4>
|
|
800c1e8: 494c ldr r1, [pc, #304] ; (800c31c <_dtoa_r+0x65c>)
|
|
800c1ea: 2000 movs r0, #0
|
|
800c1ec: f7f4 fb2e bl 800084c <__aeabi_ddiv>
|
|
800c1f0: ec53 2b18 vmov r2, r3, d8
|
|
800c1f4: f7f4 f848 bl 8000288 <__aeabi_dsub>
|
|
800c1f8: 9d00 ldr r5, [sp, #0]
|
|
800c1fa: ec41 0b18 vmov d8, r0, r1
|
|
800c1fe: 4639 mov r1, r7
|
|
800c200: 4630 mov r0, r6
|
|
800c202: f7f4 fca9 bl 8000b58 <__aeabi_d2iz>
|
|
800c206: 900c str r0, [sp, #48] ; 0x30
|
|
800c208: f7f4 f98c bl 8000524 <__aeabi_i2d>
|
|
800c20c: 4602 mov r2, r0
|
|
800c20e: 460b mov r3, r1
|
|
800c210: 4630 mov r0, r6
|
|
800c212: 4639 mov r1, r7
|
|
800c214: f7f4 f838 bl 8000288 <__aeabi_dsub>
|
|
800c218: 9b0c ldr r3, [sp, #48] ; 0x30
|
|
800c21a: 3330 adds r3, #48 ; 0x30
|
|
800c21c: f805 3b01 strb.w r3, [r5], #1
|
|
800c220: ec53 2b18 vmov r2, r3, d8
|
|
800c224: 4606 mov r6, r0
|
|
800c226: 460f mov r7, r1
|
|
800c228: f7f4 fc58 bl 8000adc <__aeabi_dcmplt>
|
|
800c22c: 2800 cmp r0, #0
|
|
800c22e: d165 bne.n 800c2fc <_dtoa_r+0x63c>
|
|
800c230: 4632 mov r2, r6
|
|
800c232: 463b mov r3, r7
|
|
800c234: 4935 ldr r1, [pc, #212] ; (800c30c <_dtoa_r+0x64c>)
|
|
800c236: 2000 movs r0, #0
|
|
800c238: f7f4 f826 bl 8000288 <__aeabi_dsub>
|
|
800c23c: ec53 2b18 vmov r2, r3, d8
|
|
800c240: f7f4 fc4c bl 8000adc <__aeabi_dcmplt>
|
|
800c244: 2800 cmp r0, #0
|
|
800c246: f040 80b9 bne.w 800c3bc <_dtoa_r+0x6fc>
|
|
800c24a: 9b02 ldr r3, [sp, #8]
|
|
800c24c: 429d cmp r5, r3
|
|
800c24e: f43f af75 beq.w 800c13c <_dtoa_r+0x47c>
|
|
800c252: 4b2f ldr r3, [pc, #188] ; (800c310 <_dtoa_r+0x650>)
|
|
800c254: ec51 0b18 vmov r0, r1, d8
|
|
800c258: 2200 movs r2, #0
|
|
800c25a: f7f4 f9cd bl 80005f8 <__aeabi_dmul>
|
|
800c25e: 4b2c ldr r3, [pc, #176] ; (800c310 <_dtoa_r+0x650>)
|
|
800c260: ec41 0b18 vmov d8, r0, r1
|
|
800c264: 2200 movs r2, #0
|
|
800c266: 4630 mov r0, r6
|
|
800c268: 4639 mov r1, r7
|
|
800c26a: f7f4 f9c5 bl 80005f8 <__aeabi_dmul>
|
|
800c26e: 4606 mov r6, r0
|
|
800c270: 460f mov r7, r1
|
|
800c272: e7c4 b.n 800c1fe <_dtoa_r+0x53e>
|
|
800c274: ec51 0b17 vmov r0, r1, d7
|
|
800c278: f7f4 f9be bl 80005f8 <__aeabi_dmul>
|
|
800c27c: 9b02 ldr r3, [sp, #8]
|
|
800c27e: 9d00 ldr r5, [sp, #0]
|
|
800c280: 930c str r3, [sp, #48] ; 0x30
|
|
800c282: ec41 0b18 vmov d8, r0, r1
|
|
800c286: 4639 mov r1, r7
|
|
800c288: 4630 mov r0, r6
|
|
800c28a: f7f4 fc65 bl 8000b58 <__aeabi_d2iz>
|
|
800c28e: 9011 str r0, [sp, #68] ; 0x44
|
|
800c290: f7f4 f948 bl 8000524 <__aeabi_i2d>
|
|
800c294: 4602 mov r2, r0
|
|
800c296: 460b mov r3, r1
|
|
800c298: 4630 mov r0, r6
|
|
800c29a: 4639 mov r1, r7
|
|
800c29c: f7f3 fff4 bl 8000288 <__aeabi_dsub>
|
|
800c2a0: 9b11 ldr r3, [sp, #68] ; 0x44
|
|
800c2a2: 3330 adds r3, #48 ; 0x30
|
|
800c2a4: f805 3b01 strb.w r3, [r5], #1
|
|
800c2a8: 9b02 ldr r3, [sp, #8]
|
|
800c2aa: 429d cmp r5, r3
|
|
800c2ac: 4606 mov r6, r0
|
|
800c2ae: 460f mov r7, r1
|
|
800c2b0: f04f 0200 mov.w r2, #0
|
|
800c2b4: d134 bne.n 800c320 <_dtoa_r+0x660>
|
|
800c2b6: 4b19 ldr r3, [pc, #100] ; (800c31c <_dtoa_r+0x65c>)
|
|
800c2b8: ec51 0b18 vmov r0, r1, d8
|
|
800c2bc: f7f3 ffe6 bl 800028c <__adddf3>
|
|
800c2c0: 4602 mov r2, r0
|
|
800c2c2: 460b mov r3, r1
|
|
800c2c4: 4630 mov r0, r6
|
|
800c2c6: 4639 mov r1, r7
|
|
800c2c8: f7f4 fc26 bl 8000b18 <__aeabi_dcmpgt>
|
|
800c2cc: 2800 cmp r0, #0
|
|
800c2ce: d175 bne.n 800c3bc <_dtoa_r+0x6fc>
|
|
800c2d0: ec53 2b18 vmov r2, r3, d8
|
|
800c2d4: 4911 ldr r1, [pc, #68] ; (800c31c <_dtoa_r+0x65c>)
|
|
800c2d6: 2000 movs r0, #0
|
|
800c2d8: f7f3 ffd6 bl 8000288 <__aeabi_dsub>
|
|
800c2dc: 4602 mov r2, r0
|
|
800c2de: 460b mov r3, r1
|
|
800c2e0: 4630 mov r0, r6
|
|
800c2e2: 4639 mov r1, r7
|
|
800c2e4: f7f4 fbfa bl 8000adc <__aeabi_dcmplt>
|
|
800c2e8: 2800 cmp r0, #0
|
|
800c2ea: f43f af27 beq.w 800c13c <_dtoa_r+0x47c>
|
|
800c2ee: 9d0c ldr r5, [sp, #48] ; 0x30
|
|
800c2f0: 1e6b subs r3, r5, #1
|
|
800c2f2: 930c str r3, [sp, #48] ; 0x30
|
|
800c2f4: f815 3c01 ldrb.w r3, [r5, #-1]
|
|
800c2f8: 2b30 cmp r3, #48 ; 0x30
|
|
800c2fa: d0f8 beq.n 800c2ee <_dtoa_r+0x62e>
|
|
800c2fc: f8dd a01c ldr.w sl, [sp, #28]
|
|
800c300: e04a b.n 800c398 <_dtoa_r+0x6d8>
|
|
800c302: bf00 nop
|
|
800c304: 0800e6e8 .word 0x0800e6e8
|
|
800c308: 0800e6c0 .word 0x0800e6c0
|
|
800c30c: 3ff00000 .word 0x3ff00000
|
|
800c310: 40240000 .word 0x40240000
|
|
800c314: 401c0000 .word 0x401c0000
|
|
800c318: 40140000 .word 0x40140000
|
|
800c31c: 3fe00000 .word 0x3fe00000
|
|
800c320: 4baf ldr r3, [pc, #700] ; (800c5e0 <_dtoa_r+0x920>)
|
|
800c322: f7f4 f969 bl 80005f8 <__aeabi_dmul>
|
|
800c326: 4606 mov r6, r0
|
|
800c328: 460f mov r7, r1
|
|
800c32a: e7ac b.n 800c286 <_dtoa_r+0x5c6>
|
|
800c32c: e9dd 6702 ldrd r6, r7, [sp, #8]
|
|
800c330: 9d00 ldr r5, [sp, #0]
|
|
800c332: 4642 mov r2, r8
|
|
800c334: 464b mov r3, r9
|
|
800c336: 4630 mov r0, r6
|
|
800c338: 4639 mov r1, r7
|
|
800c33a: f7f4 fa87 bl 800084c <__aeabi_ddiv>
|
|
800c33e: f7f4 fc0b bl 8000b58 <__aeabi_d2iz>
|
|
800c342: 9002 str r0, [sp, #8]
|
|
800c344: f7f4 f8ee bl 8000524 <__aeabi_i2d>
|
|
800c348: 4642 mov r2, r8
|
|
800c34a: 464b mov r3, r9
|
|
800c34c: f7f4 f954 bl 80005f8 <__aeabi_dmul>
|
|
800c350: 4602 mov r2, r0
|
|
800c352: 460b mov r3, r1
|
|
800c354: 4630 mov r0, r6
|
|
800c356: 4639 mov r1, r7
|
|
800c358: f7f3 ff96 bl 8000288 <__aeabi_dsub>
|
|
800c35c: 9e02 ldr r6, [sp, #8]
|
|
800c35e: 9f01 ldr r7, [sp, #4]
|
|
800c360: 3630 adds r6, #48 ; 0x30
|
|
800c362: f805 6b01 strb.w r6, [r5], #1
|
|
800c366: 9e00 ldr r6, [sp, #0]
|
|
800c368: 1bae subs r6, r5, r6
|
|
800c36a: 42b7 cmp r7, r6
|
|
800c36c: 4602 mov r2, r0
|
|
800c36e: 460b mov r3, r1
|
|
800c370: d137 bne.n 800c3e2 <_dtoa_r+0x722>
|
|
800c372: f7f3 ff8b bl 800028c <__adddf3>
|
|
800c376: 4642 mov r2, r8
|
|
800c378: 464b mov r3, r9
|
|
800c37a: 4606 mov r6, r0
|
|
800c37c: 460f mov r7, r1
|
|
800c37e: f7f4 fbcb bl 8000b18 <__aeabi_dcmpgt>
|
|
800c382: b9c8 cbnz r0, 800c3b8 <_dtoa_r+0x6f8>
|
|
800c384: 4642 mov r2, r8
|
|
800c386: 464b mov r3, r9
|
|
800c388: 4630 mov r0, r6
|
|
800c38a: 4639 mov r1, r7
|
|
800c38c: f7f4 fb9c bl 8000ac8 <__aeabi_dcmpeq>
|
|
800c390: b110 cbz r0, 800c398 <_dtoa_r+0x6d8>
|
|
800c392: 9b02 ldr r3, [sp, #8]
|
|
800c394: 07d9 lsls r1, r3, #31
|
|
800c396: d40f bmi.n 800c3b8 <_dtoa_r+0x6f8>
|
|
800c398: 4620 mov r0, r4
|
|
800c39a: 4659 mov r1, fp
|
|
800c39c: f000 fcfa bl 800cd94 <_Bfree>
|
|
800c3a0: 2300 movs r3, #0
|
|
800c3a2: 702b strb r3, [r5, #0]
|
|
800c3a4: 9b0f ldr r3, [sp, #60] ; 0x3c
|
|
800c3a6: f10a 0001 add.w r0, sl, #1
|
|
800c3aa: 6018 str r0, [r3, #0]
|
|
800c3ac: 9b21 ldr r3, [sp, #132] ; 0x84
|
|
800c3ae: 2b00 cmp r3, #0
|
|
800c3b0: f43f acd8 beq.w 800bd64 <_dtoa_r+0xa4>
|
|
800c3b4: 601d str r5, [r3, #0]
|
|
800c3b6: e4d5 b.n 800bd64 <_dtoa_r+0xa4>
|
|
800c3b8: f8cd a01c str.w sl, [sp, #28]
|
|
800c3bc: 462b mov r3, r5
|
|
800c3be: 461d mov r5, r3
|
|
800c3c0: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
800c3c4: 2a39 cmp r2, #57 ; 0x39
|
|
800c3c6: d108 bne.n 800c3da <_dtoa_r+0x71a>
|
|
800c3c8: 9a00 ldr r2, [sp, #0]
|
|
800c3ca: 429a cmp r2, r3
|
|
800c3cc: d1f7 bne.n 800c3be <_dtoa_r+0x6fe>
|
|
800c3ce: 9a07 ldr r2, [sp, #28]
|
|
800c3d0: 9900 ldr r1, [sp, #0]
|
|
800c3d2: 3201 adds r2, #1
|
|
800c3d4: 9207 str r2, [sp, #28]
|
|
800c3d6: 2230 movs r2, #48 ; 0x30
|
|
800c3d8: 700a strb r2, [r1, #0]
|
|
800c3da: 781a ldrb r2, [r3, #0]
|
|
800c3dc: 3201 adds r2, #1
|
|
800c3de: 701a strb r2, [r3, #0]
|
|
800c3e0: e78c b.n 800c2fc <_dtoa_r+0x63c>
|
|
800c3e2: 4b7f ldr r3, [pc, #508] ; (800c5e0 <_dtoa_r+0x920>)
|
|
800c3e4: 2200 movs r2, #0
|
|
800c3e6: f7f4 f907 bl 80005f8 <__aeabi_dmul>
|
|
800c3ea: 2200 movs r2, #0
|
|
800c3ec: 2300 movs r3, #0
|
|
800c3ee: 4606 mov r6, r0
|
|
800c3f0: 460f mov r7, r1
|
|
800c3f2: f7f4 fb69 bl 8000ac8 <__aeabi_dcmpeq>
|
|
800c3f6: 2800 cmp r0, #0
|
|
800c3f8: d09b beq.n 800c332 <_dtoa_r+0x672>
|
|
800c3fa: e7cd b.n 800c398 <_dtoa_r+0x6d8>
|
|
800c3fc: 9a08 ldr r2, [sp, #32]
|
|
800c3fe: 2a00 cmp r2, #0
|
|
800c400: f000 80c4 beq.w 800c58c <_dtoa_r+0x8cc>
|
|
800c404: 9a05 ldr r2, [sp, #20]
|
|
800c406: 2a01 cmp r2, #1
|
|
800c408: f300 80a8 bgt.w 800c55c <_dtoa_r+0x89c>
|
|
800c40c: 9a10 ldr r2, [sp, #64] ; 0x40
|
|
800c40e: 2a00 cmp r2, #0
|
|
800c410: f000 80a0 beq.w 800c554 <_dtoa_r+0x894>
|
|
800c414: f203 4333 addw r3, r3, #1075 ; 0x433
|
|
800c418: 9e06 ldr r6, [sp, #24]
|
|
800c41a: 4645 mov r5, r8
|
|
800c41c: 9a04 ldr r2, [sp, #16]
|
|
800c41e: 2101 movs r1, #1
|
|
800c420: 441a add r2, r3
|
|
800c422: 4620 mov r0, r4
|
|
800c424: 4498 add r8, r3
|
|
800c426: 9204 str r2, [sp, #16]
|
|
800c428: f000 fd70 bl 800cf0c <__i2b>
|
|
800c42c: 4607 mov r7, r0
|
|
800c42e: 2d00 cmp r5, #0
|
|
800c430: dd0b ble.n 800c44a <_dtoa_r+0x78a>
|
|
800c432: 9b04 ldr r3, [sp, #16]
|
|
800c434: 2b00 cmp r3, #0
|
|
800c436: dd08 ble.n 800c44a <_dtoa_r+0x78a>
|
|
800c438: 42ab cmp r3, r5
|
|
800c43a: 9a04 ldr r2, [sp, #16]
|
|
800c43c: bfa8 it ge
|
|
800c43e: 462b movge r3, r5
|
|
800c440: eba8 0803 sub.w r8, r8, r3
|
|
800c444: 1aed subs r5, r5, r3
|
|
800c446: 1ad3 subs r3, r2, r3
|
|
800c448: 9304 str r3, [sp, #16]
|
|
800c44a: 9b06 ldr r3, [sp, #24]
|
|
800c44c: b1fb cbz r3, 800c48e <_dtoa_r+0x7ce>
|
|
800c44e: 9b08 ldr r3, [sp, #32]
|
|
800c450: 2b00 cmp r3, #0
|
|
800c452: f000 809f beq.w 800c594 <_dtoa_r+0x8d4>
|
|
800c456: 2e00 cmp r6, #0
|
|
800c458: dd11 ble.n 800c47e <_dtoa_r+0x7be>
|
|
800c45a: 4639 mov r1, r7
|
|
800c45c: 4632 mov r2, r6
|
|
800c45e: 4620 mov r0, r4
|
|
800c460: f000 fe10 bl 800d084 <__pow5mult>
|
|
800c464: 465a mov r2, fp
|
|
800c466: 4601 mov r1, r0
|
|
800c468: 4607 mov r7, r0
|
|
800c46a: 4620 mov r0, r4
|
|
800c46c: f000 fd64 bl 800cf38 <__multiply>
|
|
800c470: 4659 mov r1, fp
|
|
800c472: 9007 str r0, [sp, #28]
|
|
800c474: 4620 mov r0, r4
|
|
800c476: f000 fc8d bl 800cd94 <_Bfree>
|
|
800c47a: 9b07 ldr r3, [sp, #28]
|
|
800c47c: 469b mov fp, r3
|
|
800c47e: 9b06 ldr r3, [sp, #24]
|
|
800c480: 1b9a subs r2, r3, r6
|
|
800c482: d004 beq.n 800c48e <_dtoa_r+0x7ce>
|
|
800c484: 4659 mov r1, fp
|
|
800c486: 4620 mov r0, r4
|
|
800c488: f000 fdfc bl 800d084 <__pow5mult>
|
|
800c48c: 4683 mov fp, r0
|
|
800c48e: 2101 movs r1, #1
|
|
800c490: 4620 mov r0, r4
|
|
800c492: f000 fd3b bl 800cf0c <__i2b>
|
|
800c496: 9b0d ldr r3, [sp, #52] ; 0x34
|
|
800c498: 2b00 cmp r3, #0
|
|
800c49a: 4606 mov r6, r0
|
|
800c49c: dd7c ble.n 800c598 <_dtoa_r+0x8d8>
|
|
800c49e: 461a mov r2, r3
|
|
800c4a0: 4601 mov r1, r0
|
|
800c4a2: 4620 mov r0, r4
|
|
800c4a4: f000 fdee bl 800d084 <__pow5mult>
|
|
800c4a8: 9b05 ldr r3, [sp, #20]
|
|
800c4aa: 2b01 cmp r3, #1
|
|
800c4ac: 4606 mov r6, r0
|
|
800c4ae: dd76 ble.n 800c59e <_dtoa_r+0x8de>
|
|
800c4b0: 2300 movs r3, #0
|
|
800c4b2: 9306 str r3, [sp, #24]
|
|
800c4b4: 6933 ldr r3, [r6, #16]
|
|
800c4b6: eb06 0383 add.w r3, r6, r3, lsl #2
|
|
800c4ba: 6918 ldr r0, [r3, #16]
|
|
800c4bc: f000 fcd6 bl 800ce6c <__hi0bits>
|
|
800c4c0: f1c0 0020 rsb r0, r0, #32
|
|
800c4c4: 9b04 ldr r3, [sp, #16]
|
|
800c4c6: 4418 add r0, r3
|
|
800c4c8: f010 001f ands.w r0, r0, #31
|
|
800c4cc: f000 8086 beq.w 800c5dc <_dtoa_r+0x91c>
|
|
800c4d0: f1c0 0320 rsb r3, r0, #32
|
|
800c4d4: 2b04 cmp r3, #4
|
|
800c4d6: dd7f ble.n 800c5d8 <_dtoa_r+0x918>
|
|
800c4d8: f1c0 001c rsb r0, r0, #28
|
|
800c4dc: 9b04 ldr r3, [sp, #16]
|
|
800c4de: 4403 add r3, r0
|
|
800c4e0: 4480 add r8, r0
|
|
800c4e2: 4405 add r5, r0
|
|
800c4e4: 9304 str r3, [sp, #16]
|
|
800c4e6: f1b8 0f00 cmp.w r8, #0
|
|
800c4ea: dd05 ble.n 800c4f8 <_dtoa_r+0x838>
|
|
800c4ec: 4659 mov r1, fp
|
|
800c4ee: 4642 mov r2, r8
|
|
800c4f0: 4620 mov r0, r4
|
|
800c4f2: f000 fe21 bl 800d138 <__lshift>
|
|
800c4f6: 4683 mov fp, r0
|
|
800c4f8: 9b04 ldr r3, [sp, #16]
|
|
800c4fa: 2b00 cmp r3, #0
|
|
800c4fc: dd05 ble.n 800c50a <_dtoa_r+0x84a>
|
|
800c4fe: 4631 mov r1, r6
|
|
800c500: 461a mov r2, r3
|
|
800c502: 4620 mov r0, r4
|
|
800c504: f000 fe18 bl 800d138 <__lshift>
|
|
800c508: 4606 mov r6, r0
|
|
800c50a: 9b0e ldr r3, [sp, #56] ; 0x38
|
|
800c50c: 2b00 cmp r3, #0
|
|
800c50e: d069 beq.n 800c5e4 <_dtoa_r+0x924>
|
|
800c510: 4631 mov r1, r6
|
|
800c512: 4658 mov r0, fp
|
|
800c514: f000 fe7c bl 800d210 <__mcmp>
|
|
800c518: 2800 cmp r0, #0
|
|
800c51a: da63 bge.n 800c5e4 <_dtoa_r+0x924>
|
|
800c51c: 2300 movs r3, #0
|
|
800c51e: 4659 mov r1, fp
|
|
800c520: 220a movs r2, #10
|
|
800c522: 4620 mov r0, r4
|
|
800c524: f000 fc58 bl 800cdd8 <__multadd>
|
|
800c528: 9b08 ldr r3, [sp, #32]
|
|
800c52a: f10a 3aff add.w sl, sl, #4294967295 ; 0xffffffff
|
|
800c52e: 4683 mov fp, r0
|
|
800c530: 2b00 cmp r3, #0
|
|
800c532: f000 818f beq.w 800c854 <_dtoa_r+0xb94>
|
|
800c536: 4639 mov r1, r7
|
|
800c538: 2300 movs r3, #0
|
|
800c53a: 220a movs r2, #10
|
|
800c53c: 4620 mov r0, r4
|
|
800c53e: f000 fc4b bl 800cdd8 <__multadd>
|
|
800c542: f1b9 0f00 cmp.w r9, #0
|
|
800c546: 4607 mov r7, r0
|
|
800c548: f300 808e bgt.w 800c668 <_dtoa_r+0x9a8>
|
|
800c54c: 9b05 ldr r3, [sp, #20]
|
|
800c54e: 2b02 cmp r3, #2
|
|
800c550: dc50 bgt.n 800c5f4 <_dtoa_r+0x934>
|
|
800c552: e089 b.n 800c668 <_dtoa_r+0x9a8>
|
|
800c554: 9b12 ldr r3, [sp, #72] ; 0x48
|
|
800c556: f1c3 0336 rsb r3, r3, #54 ; 0x36
|
|
800c55a: e75d b.n 800c418 <_dtoa_r+0x758>
|
|
800c55c: 9b01 ldr r3, [sp, #4]
|
|
800c55e: 1e5e subs r6, r3, #1
|
|
800c560: 9b06 ldr r3, [sp, #24]
|
|
800c562: 42b3 cmp r3, r6
|
|
800c564: bfbf itttt lt
|
|
800c566: 9b06 ldrlt r3, [sp, #24]
|
|
800c568: 9606 strlt r6, [sp, #24]
|
|
800c56a: 1af2 sublt r2, r6, r3
|
|
800c56c: 9b0d ldrlt r3, [sp, #52] ; 0x34
|
|
800c56e: bfb6 itet lt
|
|
800c570: 189b addlt r3, r3, r2
|
|
800c572: 1b9e subge r6, r3, r6
|
|
800c574: 930d strlt r3, [sp, #52] ; 0x34
|
|
800c576: 9b01 ldr r3, [sp, #4]
|
|
800c578: bfb8 it lt
|
|
800c57a: 2600 movlt r6, #0
|
|
800c57c: 2b00 cmp r3, #0
|
|
800c57e: bfb5 itete lt
|
|
800c580: eba8 0503 sublt.w r5, r8, r3
|
|
800c584: 9b01 ldrge r3, [sp, #4]
|
|
800c586: 2300 movlt r3, #0
|
|
800c588: 4645 movge r5, r8
|
|
800c58a: e747 b.n 800c41c <_dtoa_r+0x75c>
|
|
800c58c: 9e06 ldr r6, [sp, #24]
|
|
800c58e: 9f08 ldr r7, [sp, #32]
|
|
800c590: 4645 mov r5, r8
|
|
800c592: e74c b.n 800c42e <_dtoa_r+0x76e>
|
|
800c594: 9a06 ldr r2, [sp, #24]
|
|
800c596: e775 b.n 800c484 <_dtoa_r+0x7c4>
|
|
800c598: 9b05 ldr r3, [sp, #20]
|
|
800c59a: 2b01 cmp r3, #1
|
|
800c59c: dc18 bgt.n 800c5d0 <_dtoa_r+0x910>
|
|
800c59e: 9b02 ldr r3, [sp, #8]
|
|
800c5a0: b9b3 cbnz r3, 800c5d0 <_dtoa_r+0x910>
|
|
800c5a2: 9b03 ldr r3, [sp, #12]
|
|
800c5a4: f3c3 0313 ubfx r3, r3, #0, #20
|
|
800c5a8: b9a3 cbnz r3, 800c5d4 <_dtoa_r+0x914>
|
|
800c5aa: 9b03 ldr r3, [sp, #12]
|
|
800c5ac: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000
|
|
800c5b0: 0d1b lsrs r3, r3, #20
|
|
800c5b2: 051b lsls r3, r3, #20
|
|
800c5b4: b12b cbz r3, 800c5c2 <_dtoa_r+0x902>
|
|
800c5b6: 9b04 ldr r3, [sp, #16]
|
|
800c5b8: 3301 adds r3, #1
|
|
800c5ba: 9304 str r3, [sp, #16]
|
|
800c5bc: f108 0801 add.w r8, r8, #1
|
|
800c5c0: 2301 movs r3, #1
|
|
800c5c2: 9306 str r3, [sp, #24]
|
|
800c5c4: 9b0d ldr r3, [sp, #52] ; 0x34
|
|
800c5c6: 2b00 cmp r3, #0
|
|
800c5c8: f47f af74 bne.w 800c4b4 <_dtoa_r+0x7f4>
|
|
800c5cc: 2001 movs r0, #1
|
|
800c5ce: e779 b.n 800c4c4 <_dtoa_r+0x804>
|
|
800c5d0: 2300 movs r3, #0
|
|
800c5d2: e7f6 b.n 800c5c2 <_dtoa_r+0x902>
|
|
800c5d4: 9b02 ldr r3, [sp, #8]
|
|
800c5d6: e7f4 b.n 800c5c2 <_dtoa_r+0x902>
|
|
800c5d8: d085 beq.n 800c4e6 <_dtoa_r+0x826>
|
|
800c5da: 4618 mov r0, r3
|
|
800c5dc: 301c adds r0, #28
|
|
800c5de: e77d b.n 800c4dc <_dtoa_r+0x81c>
|
|
800c5e0: 40240000 .word 0x40240000
|
|
800c5e4: 9b01 ldr r3, [sp, #4]
|
|
800c5e6: 2b00 cmp r3, #0
|
|
800c5e8: dc38 bgt.n 800c65c <_dtoa_r+0x99c>
|
|
800c5ea: 9b05 ldr r3, [sp, #20]
|
|
800c5ec: 2b02 cmp r3, #2
|
|
800c5ee: dd35 ble.n 800c65c <_dtoa_r+0x99c>
|
|
800c5f0: f8dd 9004 ldr.w r9, [sp, #4]
|
|
800c5f4: f1b9 0f00 cmp.w r9, #0
|
|
800c5f8: d10d bne.n 800c616 <_dtoa_r+0x956>
|
|
800c5fa: 4631 mov r1, r6
|
|
800c5fc: 464b mov r3, r9
|
|
800c5fe: 2205 movs r2, #5
|
|
800c600: 4620 mov r0, r4
|
|
800c602: f000 fbe9 bl 800cdd8 <__multadd>
|
|
800c606: 4601 mov r1, r0
|
|
800c608: 4606 mov r6, r0
|
|
800c60a: 4658 mov r0, fp
|
|
800c60c: f000 fe00 bl 800d210 <__mcmp>
|
|
800c610: 2800 cmp r0, #0
|
|
800c612: f73f adbd bgt.w 800c190 <_dtoa_r+0x4d0>
|
|
800c616: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800c618: 9d00 ldr r5, [sp, #0]
|
|
800c61a: ea6f 0a03 mvn.w sl, r3
|
|
800c61e: f04f 0800 mov.w r8, #0
|
|
800c622: 4631 mov r1, r6
|
|
800c624: 4620 mov r0, r4
|
|
800c626: f000 fbb5 bl 800cd94 <_Bfree>
|
|
800c62a: 2f00 cmp r7, #0
|
|
800c62c: f43f aeb4 beq.w 800c398 <_dtoa_r+0x6d8>
|
|
800c630: f1b8 0f00 cmp.w r8, #0
|
|
800c634: d005 beq.n 800c642 <_dtoa_r+0x982>
|
|
800c636: 45b8 cmp r8, r7
|
|
800c638: d003 beq.n 800c642 <_dtoa_r+0x982>
|
|
800c63a: 4641 mov r1, r8
|
|
800c63c: 4620 mov r0, r4
|
|
800c63e: f000 fba9 bl 800cd94 <_Bfree>
|
|
800c642: 4639 mov r1, r7
|
|
800c644: 4620 mov r0, r4
|
|
800c646: f000 fba5 bl 800cd94 <_Bfree>
|
|
800c64a: e6a5 b.n 800c398 <_dtoa_r+0x6d8>
|
|
800c64c: 2600 movs r6, #0
|
|
800c64e: 4637 mov r7, r6
|
|
800c650: e7e1 b.n 800c616 <_dtoa_r+0x956>
|
|
800c652: 9e0c ldr r6, [sp, #48] ; 0x30
|
|
800c654: f8dd a01c ldr.w sl, [sp, #28]
|
|
800c658: 4637 mov r7, r6
|
|
800c65a: e599 b.n 800c190 <_dtoa_r+0x4d0>
|
|
800c65c: 9b08 ldr r3, [sp, #32]
|
|
800c65e: f8dd 9004 ldr.w r9, [sp, #4]
|
|
800c662: 2b00 cmp r3, #0
|
|
800c664: f000 80fd beq.w 800c862 <_dtoa_r+0xba2>
|
|
800c668: 2d00 cmp r5, #0
|
|
800c66a: dd05 ble.n 800c678 <_dtoa_r+0x9b8>
|
|
800c66c: 4639 mov r1, r7
|
|
800c66e: 462a mov r2, r5
|
|
800c670: 4620 mov r0, r4
|
|
800c672: f000 fd61 bl 800d138 <__lshift>
|
|
800c676: 4607 mov r7, r0
|
|
800c678: 9b06 ldr r3, [sp, #24]
|
|
800c67a: 2b00 cmp r3, #0
|
|
800c67c: d05c beq.n 800c738 <_dtoa_r+0xa78>
|
|
800c67e: 6879 ldr r1, [r7, #4]
|
|
800c680: 4620 mov r0, r4
|
|
800c682: f000 fb47 bl 800cd14 <_Balloc>
|
|
800c686: 4605 mov r5, r0
|
|
800c688: b928 cbnz r0, 800c696 <_dtoa_r+0x9d6>
|
|
800c68a: 4b80 ldr r3, [pc, #512] ; (800c88c <_dtoa_r+0xbcc>)
|
|
800c68c: 4602 mov r2, r0
|
|
800c68e: f240 21ea movw r1, #746 ; 0x2ea
|
|
800c692: f7ff bb2e b.w 800bcf2 <_dtoa_r+0x32>
|
|
800c696: 693a ldr r2, [r7, #16]
|
|
800c698: 3202 adds r2, #2
|
|
800c69a: 0092 lsls r2, r2, #2
|
|
800c69c: f107 010c add.w r1, r7, #12
|
|
800c6a0: 300c adds r0, #12
|
|
800c6a2: f7fe fc5b bl 800af5c <memcpy>
|
|
800c6a6: 2201 movs r2, #1
|
|
800c6a8: 4629 mov r1, r5
|
|
800c6aa: 4620 mov r0, r4
|
|
800c6ac: f000 fd44 bl 800d138 <__lshift>
|
|
800c6b0: 9b00 ldr r3, [sp, #0]
|
|
800c6b2: 3301 adds r3, #1
|
|
800c6b4: 9301 str r3, [sp, #4]
|
|
800c6b6: 9b00 ldr r3, [sp, #0]
|
|
800c6b8: 444b add r3, r9
|
|
800c6ba: 9307 str r3, [sp, #28]
|
|
800c6bc: 9b02 ldr r3, [sp, #8]
|
|
800c6be: f003 0301 and.w r3, r3, #1
|
|
800c6c2: 46b8 mov r8, r7
|
|
800c6c4: 9306 str r3, [sp, #24]
|
|
800c6c6: 4607 mov r7, r0
|
|
800c6c8: 9b01 ldr r3, [sp, #4]
|
|
800c6ca: 4631 mov r1, r6
|
|
800c6cc: 3b01 subs r3, #1
|
|
800c6ce: 4658 mov r0, fp
|
|
800c6d0: 9302 str r3, [sp, #8]
|
|
800c6d2: f7ff fa67 bl 800bba4 <quorem>
|
|
800c6d6: 4603 mov r3, r0
|
|
800c6d8: 3330 adds r3, #48 ; 0x30
|
|
800c6da: 9004 str r0, [sp, #16]
|
|
800c6dc: 4641 mov r1, r8
|
|
800c6de: 4658 mov r0, fp
|
|
800c6e0: 9308 str r3, [sp, #32]
|
|
800c6e2: f000 fd95 bl 800d210 <__mcmp>
|
|
800c6e6: 463a mov r2, r7
|
|
800c6e8: 4681 mov r9, r0
|
|
800c6ea: 4631 mov r1, r6
|
|
800c6ec: 4620 mov r0, r4
|
|
800c6ee: f000 fdab bl 800d248 <__mdiff>
|
|
800c6f2: 68c2 ldr r2, [r0, #12]
|
|
800c6f4: 9b08 ldr r3, [sp, #32]
|
|
800c6f6: 4605 mov r5, r0
|
|
800c6f8: bb02 cbnz r2, 800c73c <_dtoa_r+0xa7c>
|
|
800c6fa: 4601 mov r1, r0
|
|
800c6fc: 4658 mov r0, fp
|
|
800c6fe: f000 fd87 bl 800d210 <__mcmp>
|
|
800c702: 9b08 ldr r3, [sp, #32]
|
|
800c704: 4602 mov r2, r0
|
|
800c706: 4629 mov r1, r5
|
|
800c708: 4620 mov r0, r4
|
|
800c70a: e9cd 3208 strd r3, r2, [sp, #32]
|
|
800c70e: f000 fb41 bl 800cd94 <_Bfree>
|
|
800c712: 9b05 ldr r3, [sp, #20]
|
|
800c714: 9a09 ldr r2, [sp, #36] ; 0x24
|
|
800c716: 9d01 ldr r5, [sp, #4]
|
|
800c718: ea43 0102 orr.w r1, r3, r2
|
|
800c71c: 9b06 ldr r3, [sp, #24]
|
|
800c71e: 430b orrs r3, r1
|
|
800c720: 9b08 ldr r3, [sp, #32]
|
|
800c722: d10d bne.n 800c740 <_dtoa_r+0xa80>
|
|
800c724: 2b39 cmp r3, #57 ; 0x39
|
|
800c726: d029 beq.n 800c77c <_dtoa_r+0xabc>
|
|
800c728: f1b9 0f00 cmp.w r9, #0
|
|
800c72c: dd01 ble.n 800c732 <_dtoa_r+0xa72>
|
|
800c72e: 9b04 ldr r3, [sp, #16]
|
|
800c730: 3331 adds r3, #49 ; 0x31
|
|
800c732: 9a02 ldr r2, [sp, #8]
|
|
800c734: 7013 strb r3, [r2, #0]
|
|
800c736: e774 b.n 800c622 <_dtoa_r+0x962>
|
|
800c738: 4638 mov r0, r7
|
|
800c73a: e7b9 b.n 800c6b0 <_dtoa_r+0x9f0>
|
|
800c73c: 2201 movs r2, #1
|
|
800c73e: e7e2 b.n 800c706 <_dtoa_r+0xa46>
|
|
800c740: f1b9 0f00 cmp.w r9, #0
|
|
800c744: db06 blt.n 800c754 <_dtoa_r+0xa94>
|
|
800c746: 9905 ldr r1, [sp, #20]
|
|
800c748: ea41 0909 orr.w r9, r1, r9
|
|
800c74c: 9906 ldr r1, [sp, #24]
|
|
800c74e: ea59 0101 orrs.w r1, r9, r1
|
|
800c752: d120 bne.n 800c796 <_dtoa_r+0xad6>
|
|
800c754: 2a00 cmp r2, #0
|
|
800c756: ddec ble.n 800c732 <_dtoa_r+0xa72>
|
|
800c758: 4659 mov r1, fp
|
|
800c75a: 2201 movs r2, #1
|
|
800c75c: 4620 mov r0, r4
|
|
800c75e: 9301 str r3, [sp, #4]
|
|
800c760: f000 fcea bl 800d138 <__lshift>
|
|
800c764: 4631 mov r1, r6
|
|
800c766: 4683 mov fp, r0
|
|
800c768: f000 fd52 bl 800d210 <__mcmp>
|
|
800c76c: 2800 cmp r0, #0
|
|
800c76e: 9b01 ldr r3, [sp, #4]
|
|
800c770: dc02 bgt.n 800c778 <_dtoa_r+0xab8>
|
|
800c772: d1de bne.n 800c732 <_dtoa_r+0xa72>
|
|
800c774: 07da lsls r2, r3, #31
|
|
800c776: d5dc bpl.n 800c732 <_dtoa_r+0xa72>
|
|
800c778: 2b39 cmp r3, #57 ; 0x39
|
|
800c77a: d1d8 bne.n 800c72e <_dtoa_r+0xa6e>
|
|
800c77c: 9a02 ldr r2, [sp, #8]
|
|
800c77e: 2339 movs r3, #57 ; 0x39
|
|
800c780: 7013 strb r3, [r2, #0]
|
|
800c782: 462b mov r3, r5
|
|
800c784: 461d mov r5, r3
|
|
800c786: 3b01 subs r3, #1
|
|
800c788: f815 2c01 ldrb.w r2, [r5, #-1]
|
|
800c78c: 2a39 cmp r2, #57 ; 0x39
|
|
800c78e: d050 beq.n 800c832 <_dtoa_r+0xb72>
|
|
800c790: 3201 adds r2, #1
|
|
800c792: 701a strb r2, [r3, #0]
|
|
800c794: e745 b.n 800c622 <_dtoa_r+0x962>
|
|
800c796: 2a00 cmp r2, #0
|
|
800c798: dd03 ble.n 800c7a2 <_dtoa_r+0xae2>
|
|
800c79a: 2b39 cmp r3, #57 ; 0x39
|
|
800c79c: d0ee beq.n 800c77c <_dtoa_r+0xabc>
|
|
800c79e: 3301 adds r3, #1
|
|
800c7a0: e7c7 b.n 800c732 <_dtoa_r+0xa72>
|
|
800c7a2: 9a01 ldr r2, [sp, #4]
|
|
800c7a4: 9907 ldr r1, [sp, #28]
|
|
800c7a6: f802 3c01 strb.w r3, [r2, #-1]
|
|
800c7aa: 428a cmp r2, r1
|
|
800c7ac: d02a beq.n 800c804 <_dtoa_r+0xb44>
|
|
800c7ae: 4659 mov r1, fp
|
|
800c7b0: 2300 movs r3, #0
|
|
800c7b2: 220a movs r2, #10
|
|
800c7b4: 4620 mov r0, r4
|
|
800c7b6: f000 fb0f bl 800cdd8 <__multadd>
|
|
800c7ba: 45b8 cmp r8, r7
|
|
800c7bc: 4683 mov fp, r0
|
|
800c7be: f04f 0300 mov.w r3, #0
|
|
800c7c2: f04f 020a mov.w r2, #10
|
|
800c7c6: 4641 mov r1, r8
|
|
800c7c8: 4620 mov r0, r4
|
|
800c7ca: d107 bne.n 800c7dc <_dtoa_r+0xb1c>
|
|
800c7cc: f000 fb04 bl 800cdd8 <__multadd>
|
|
800c7d0: 4680 mov r8, r0
|
|
800c7d2: 4607 mov r7, r0
|
|
800c7d4: 9b01 ldr r3, [sp, #4]
|
|
800c7d6: 3301 adds r3, #1
|
|
800c7d8: 9301 str r3, [sp, #4]
|
|
800c7da: e775 b.n 800c6c8 <_dtoa_r+0xa08>
|
|
800c7dc: f000 fafc bl 800cdd8 <__multadd>
|
|
800c7e0: 4639 mov r1, r7
|
|
800c7e2: 4680 mov r8, r0
|
|
800c7e4: 2300 movs r3, #0
|
|
800c7e6: 220a movs r2, #10
|
|
800c7e8: 4620 mov r0, r4
|
|
800c7ea: f000 faf5 bl 800cdd8 <__multadd>
|
|
800c7ee: 4607 mov r7, r0
|
|
800c7f0: e7f0 b.n 800c7d4 <_dtoa_r+0xb14>
|
|
800c7f2: f1b9 0f00 cmp.w r9, #0
|
|
800c7f6: 9a00 ldr r2, [sp, #0]
|
|
800c7f8: bfcc ite gt
|
|
800c7fa: 464d movgt r5, r9
|
|
800c7fc: 2501 movle r5, #1
|
|
800c7fe: 4415 add r5, r2
|
|
800c800: f04f 0800 mov.w r8, #0
|
|
800c804: 4659 mov r1, fp
|
|
800c806: 2201 movs r2, #1
|
|
800c808: 4620 mov r0, r4
|
|
800c80a: 9301 str r3, [sp, #4]
|
|
800c80c: f000 fc94 bl 800d138 <__lshift>
|
|
800c810: 4631 mov r1, r6
|
|
800c812: 4683 mov fp, r0
|
|
800c814: f000 fcfc bl 800d210 <__mcmp>
|
|
800c818: 2800 cmp r0, #0
|
|
800c81a: dcb2 bgt.n 800c782 <_dtoa_r+0xac2>
|
|
800c81c: d102 bne.n 800c824 <_dtoa_r+0xb64>
|
|
800c81e: 9b01 ldr r3, [sp, #4]
|
|
800c820: 07db lsls r3, r3, #31
|
|
800c822: d4ae bmi.n 800c782 <_dtoa_r+0xac2>
|
|
800c824: 462b mov r3, r5
|
|
800c826: 461d mov r5, r3
|
|
800c828: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
800c82c: 2a30 cmp r2, #48 ; 0x30
|
|
800c82e: d0fa beq.n 800c826 <_dtoa_r+0xb66>
|
|
800c830: e6f7 b.n 800c622 <_dtoa_r+0x962>
|
|
800c832: 9a00 ldr r2, [sp, #0]
|
|
800c834: 429a cmp r2, r3
|
|
800c836: d1a5 bne.n 800c784 <_dtoa_r+0xac4>
|
|
800c838: f10a 0a01 add.w sl, sl, #1
|
|
800c83c: 2331 movs r3, #49 ; 0x31
|
|
800c83e: e779 b.n 800c734 <_dtoa_r+0xa74>
|
|
800c840: 4b13 ldr r3, [pc, #76] ; (800c890 <_dtoa_r+0xbd0>)
|
|
800c842: f7ff baaf b.w 800bda4 <_dtoa_r+0xe4>
|
|
800c846: 9b21 ldr r3, [sp, #132] ; 0x84
|
|
800c848: 2b00 cmp r3, #0
|
|
800c84a: f47f aa86 bne.w 800bd5a <_dtoa_r+0x9a>
|
|
800c84e: 4b11 ldr r3, [pc, #68] ; (800c894 <_dtoa_r+0xbd4>)
|
|
800c850: f7ff baa8 b.w 800bda4 <_dtoa_r+0xe4>
|
|
800c854: f1b9 0f00 cmp.w r9, #0
|
|
800c858: dc03 bgt.n 800c862 <_dtoa_r+0xba2>
|
|
800c85a: 9b05 ldr r3, [sp, #20]
|
|
800c85c: 2b02 cmp r3, #2
|
|
800c85e: f73f aec9 bgt.w 800c5f4 <_dtoa_r+0x934>
|
|
800c862: 9d00 ldr r5, [sp, #0]
|
|
800c864: 4631 mov r1, r6
|
|
800c866: 4658 mov r0, fp
|
|
800c868: f7ff f99c bl 800bba4 <quorem>
|
|
800c86c: f100 0330 add.w r3, r0, #48 ; 0x30
|
|
800c870: f805 3b01 strb.w r3, [r5], #1
|
|
800c874: 9a00 ldr r2, [sp, #0]
|
|
800c876: 1aaa subs r2, r5, r2
|
|
800c878: 4591 cmp r9, r2
|
|
800c87a: ddba ble.n 800c7f2 <_dtoa_r+0xb32>
|
|
800c87c: 4659 mov r1, fp
|
|
800c87e: 2300 movs r3, #0
|
|
800c880: 220a movs r2, #10
|
|
800c882: 4620 mov r0, r4
|
|
800c884: f000 faa8 bl 800cdd8 <__multadd>
|
|
800c888: 4683 mov fp, r0
|
|
800c88a: e7eb b.n 800c864 <_dtoa_r+0xba4>
|
|
800c88c: 0800e5ec .word 0x0800e5ec
|
|
800c890: 0800e408 .word 0x0800e408
|
|
800c894: 0800e569 .word 0x0800e569
|
|
|
|
0800c898 <__sflush_r>:
|
|
800c898: 898a ldrh r2, [r1, #12]
|
|
800c89a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
800c89e: 4605 mov r5, r0
|
|
800c8a0: 0710 lsls r0, r2, #28
|
|
800c8a2: 460c mov r4, r1
|
|
800c8a4: d458 bmi.n 800c958 <__sflush_r+0xc0>
|
|
800c8a6: 684b ldr r3, [r1, #4]
|
|
800c8a8: 2b00 cmp r3, #0
|
|
800c8aa: dc05 bgt.n 800c8b8 <__sflush_r+0x20>
|
|
800c8ac: 6c0b ldr r3, [r1, #64] ; 0x40
|
|
800c8ae: 2b00 cmp r3, #0
|
|
800c8b0: dc02 bgt.n 800c8b8 <__sflush_r+0x20>
|
|
800c8b2: 2000 movs r0, #0
|
|
800c8b4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
800c8b8: 6ae6 ldr r6, [r4, #44] ; 0x2c
|
|
800c8ba: 2e00 cmp r6, #0
|
|
800c8bc: d0f9 beq.n 800c8b2 <__sflush_r+0x1a>
|
|
800c8be: 2300 movs r3, #0
|
|
800c8c0: f412 5280 ands.w r2, r2, #4096 ; 0x1000
|
|
800c8c4: 682f ldr r7, [r5, #0]
|
|
800c8c6: 602b str r3, [r5, #0]
|
|
800c8c8: d032 beq.n 800c930 <__sflush_r+0x98>
|
|
800c8ca: 6d60 ldr r0, [r4, #84] ; 0x54
|
|
800c8cc: 89a3 ldrh r3, [r4, #12]
|
|
800c8ce: 075a lsls r2, r3, #29
|
|
800c8d0: d505 bpl.n 800c8de <__sflush_r+0x46>
|
|
800c8d2: 6863 ldr r3, [r4, #4]
|
|
800c8d4: 1ac0 subs r0, r0, r3
|
|
800c8d6: 6b63 ldr r3, [r4, #52] ; 0x34
|
|
800c8d8: b10b cbz r3, 800c8de <__sflush_r+0x46>
|
|
800c8da: 6c23 ldr r3, [r4, #64] ; 0x40
|
|
800c8dc: 1ac0 subs r0, r0, r3
|
|
800c8de: 2300 movs r3, #0
|
|
800c8e0: 4602 mov r2, r0
|
|
800c8e2: 6ae6 ldr r6, [r4, #44] ; 0x2c
|
|
800c8e4: 6a21 ldr r1, [r4, #32]
|
|
800c8e6: 4628 mov r0, r5
|
|
800c8e8: 47b0 blx r6
|
|
800c8ea: 1c43 adds r3, r0, #1
|
|
800c8ec: 89a3 ldrh r3, [r4, #12]
|
|
800c8ee: d106 bne.n 800c8fe <__sflush_r+0x66>
|
|
800c8f0: 6829 ldr r1, [r5, #0]
|
|
800c8f2: 291d cmp r1, #29
|
|
800c8f4: d82c bhi.n 800c950 <__sflush_r+0xb8>
|
|
800c8f6: 4a2a ldr r2, [pc, #168] ; (800c9a0 <__sflush_r+0x108>)
|
|
800c8f8: 40ca lsrs r2, r1
|
|
800c8fa: 07d6 lsls r6, r2, #31
|
|
800c8fc: d528 bpl.n 800c950 <__sflush_r+0xb8>
|
|
800c8fe: 2200 movs r2, #0
|
|
800c900: 6062 str r2, [r4, #4]
|
|
800c902: 04d9 lsls r1, r3, #19
|
|
800c904: 6922 ldr r2, [r4, #16]
|
|
800c906: 6022 str r2, [r4, #0]
|
|
800c908: d504 bpl.n 800c914 <__sflush_r+0x7c>
|
|
800c90a: 1c42 adds r2, r0, #1
|
|
800c90c: d101 bne.n 800c912 <__sflush_r+0x7a>
|
|
800c90e: 682b ldr r3, [r5, #0]
|
|
800c910: b903 cbnz r3, 800c914 <__sflush_r+0x7c>
|
|
800c912: 6560 str r0, [r4, #84] ; 0x54
|
|
800c914: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
800c916: 602f str r7, [r5, #0]
|
|
800c918: 2900 cmp r1, #0
|
|
800c91a: d0ca beq.n 800c8b2 <__sflush_r+0x1a>
|
|
800c91c: f104 0344 add.w r3, r4, #68 ; 0x44
|
|
800c920: 4299 cmp r1, r3
|
|
800c922: d002 beq.n 800c92a <__sflush_r+0x92>
|
|
800c924: 4628 mov r0, r5
|
|
800c926: f000 fd83 bl 800d430 <_free_r>
|
|
800c92a: 2000 movs r0, #0
|
|
800c92c: 6360 str r0, [r4, #52] ; 0x34
|
|
800c92e: e7c1 b.n 800c8b4 <__sflush_r+0x1c>
|
|
800c930: 6a21 ldr r1, [r4, #32]
|
|
800c932: 2301 movs r3, #1
|
|
800c934: 4628 mov r0, r5
|
|
800c936: 47b0 blx r6
|
|
800c938: 1c41 adds r1, r0, #1
|
|
800c93a: d1c7 bne.n 800c8cc <__sflush_r+0x34>
|
|
800c93c: 682b ldr r3, [r5, #0]
|
|
800c93e: 2b00 cmp r3, #0
|
|
800c940: d0c4 beq.n 800c8cc <__sflush_r+0x34>
|
|
800c942: 2b1d cmp r3, #29
|
|
800c944: d001 beq.n 800c94a <__sflush_r+0xb2>
|
|
800c946: 2b16 cmp r3, #22
|
|
800c948: d101 bne.n 800c94e <__sflush_r+0xb6>
|
|
800c94a: 602f str r7, [r5, #0]
|
|
800c94c: e7b1 b.n 800c8b2 <__sflush_r+0x1a>
|
|
800c94e: 89a3 ldrh r3, [r4, #12]
|
|
800c950: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
800c954: 81a3 strh r3, [r4, #12]
|
|
800c956: e7ad b.n 800c8b4 <__sflush_r+0x1c>
|
|
800c958: 690f ldr r7, [r1, #16]
|
|
800c95a: 2f00 cmp r7, #0
|
|
800c95c: d0a9 beq.n 800c8b2 <__sflush_r+0x1a>
|
|
800c95e: 0793 lsls r3, r2, #30
|
|
800c960: 680e ldr r6, [r1, #0]
|
|
800c962: bf08 it eq
|
|
800c964: 694b ldreq r3, [r1, #20]
|
|
800c966: 600f str r7, [r1, #0]
|
|
800c968: bf18 it ne
|
|
800c96a: 2300 movne r3, #0
|
|
800c96c: eba6 0807 sub.w r8, r6, r7
|
|
800c970: 608b str r3, [r1, #8]
|
|
800c972: f1b8 0f00 cmp.w r8, #0
|
|
800c976: dd9c ble.n 800c8b2 <__sflush_r+0x1a>
|
|
800c978: 6a21 ldr r1, [r4, #32]
|
|
800c97a: 6aa6 ldr r6, [r4, #40] ; 0x28
|
|
800c97c: 4643 mov r3, r8
|
|
800c97e: 463a mov r2, r7
|
|
800c980: 4628 mov r0, r5
|
|
800c982: 47b0 blx r6
|
|
800c984: 2800 cmp r0, #0
|
|
800c986: dc06 bgt.n 800c996 <__sflush_r+0xfe>
|
|
800c988: 89a3 ldrh r3, [r4, #12]
|
|
800c98a: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
800c98e: 81a3 strh r3, [r4, #12]
|
|
800c990: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800c994: e78e b.n 800c8b4 <__sflush_r+0x1c>
|
|
800c996: 4407 add r7, r0
|
|
800c998: eba8 0800 sub.w r8, r8, r0
|
|
800c99c: e7e9 b.n 800c972 <__sflush_r+0xda>
|
|
800c99e: bf00 nop
|
|
800c9a0: 20400001 .word 0x20400001
|
|
|
|
0800c9a4 <_fflush_r>:
|
|
800c9a4: b538 push {r3, r4, r5, lr}
|
|
800c9a6: 690b ldr r3, [r1, #16]
|
|
800c9a8: 4605 mov r5, r0
|
|
800c9aa: 460c mov r4, r1
|
|
800c9ac: b913 cbnz r3, 800c9b4 <_fflush_r+0x10>
|
|
800c9ae: 2500 movs r5, #0
|
|
800c9b0: 4628 mov r0, r5
|
|
800c9b2: bd38 pop {r3, r4, r5, pc}
|
|
800c9b4: b118 cbz r0, 800c9be <_fflush_r+0x1a>
|
|
800c9b6: 6983 ldr r3, [r0, #24]
|
|
800c9b8: b90b cbnz r3, 800c9be <_fflush_r+0x1a>
|
|
800c9ba: f000 f887 bl 800cacc <__sinit>
|
|
800c9be: 4b14 ldr r3, [pc, #80] ; (800ca10 <_fflush_r+0x6c>)
|
|
800c9c0: 429c cmp r4, r3
|
|
800c9c2: d11b bne.n 800c9fc <_fflush_r+0x58>
|
|
800c9c4: 686c ldr r4, [r5, #4]
|
|
800c9c6: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
800c9ca: 2b00 cmp r3, #0
|
|
800c9cc: d0ef beq.n 800c9ae <_fflush_r+0xa>
|
|
800c9ce: 6e62 ldr r2, [r4, #100] ; 0x64
|
|
800c9d0: 07d0 lsls r0, r2, #31
|
|
800c9d2: d404 bmi.n 800c9de <_fflush_r+0x3a>
|
|
800c9d4: 0599 lsls r1, r3, #22
|
|
800c9d6: d402 bmi.n 800c9de <_fflush_r+0x3a>
|
|
800c9d8: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
800c9da: f000 f92c bl 800cc36 <__retarget_lock_acquire_recursive>
|
|
800c9de: 4628 mov r0, r5
|
|
800c9e0: 4621 mov r1, r4
|
|
800c9e2: f7ff ff59 bl 800c898 <__sflush_r>
|
|
800c9e6: 6e63 ldr r3, [r4, #100] ; 0x64
|
|
800c9e8: 07da lsls r2, r3, #31
|
|
800c9ea: 4605 mov r5, r0
|
|
800c9ec: d4e0 bmi.n 800c9b0 <_fflush_r+0xc>
|
|
800c9ee: 89a3 ldrh r3, [r4, #12]
|
|
800c9f0: 059b lsls r3, r3, #22
|
|
800c9f2: d4dd bmi.n 800c9b0 <_fflush_r+0xc>
|
|
800c9f4: 6da0 ldr r0, [r4, #88] ; 0x58
|
|
800c9f6: f000 f91f bl 800cc38 <__retarget_lock_release_recursive>
|
|
800c9fa: e7d9 b.n 800c9b0 <_fflush_r+0xc>
|
|
800c9fc: 4b05 ldr r3, [pc, #20] ; (800ca14 <_fflush_r+0x70>)
|
|
800c9fe: 429c cmp r4, r3
|
|
800ca00: d101 bne.n 800ca06 <_fflush_r+0x62>
|
|
800ca02: 68ac ldr r4, [r5, #8]
|
|
800ca04: e7df b.n 800c9c6 <_fflush_r+0x22>
|
|
800ca06: 4b04 ldr r3, [pc, #16] ; (800ca18 <_fflush_r+0x74>)
|
|
800ca08: 429c cmp r4, r3
|
|
800ca0a: bf08 it eq
|
|
800ca0c: 68ec ldreq r4, [r5, #12]
|
|
800ca0e: e7da b.n 800c9c6 <_fflush_r+0x22>
|
|
800ca10: 0800e620 .word 0x0800e620
|
|
800ca14: 0800e640 .word 0x0800e640
|
|
800ca18: 0800e600 .word 0x0800e600
|
|
|
|
0800ca1c <std>:
|
|
800ca1c: 2300 movs r3, #0
|
|
800ca1e: b510 push {r4, lr}
|
|
800ca20: 4604 mov r4, r0
|
|
800ca22: e9c0 3300 strd r3, r3, [r0]
|
|
800ca26: e9c0 3304 strd r3, r3, [r0, #16]
|
|
800ca2a: 6083 str r3, [r0, #8]
|
|
800ca2c: 8181 strh r1, [r0, #12]
|
|
800ca2e: 6643 str r3, [r0, #100] ; 0x64
|
|
800ca30: 81c2 strh r2, [r0, #14]
|
|
800ca32: 6183 str r3, [r0, #24]
|
|
800ca34: 4619 mov r1, r3
|
|
800ca36: 2208 movs r2, #8
|
|
800ca38: 305c adds r0, #92 ; 0x5c
|
|
800ca3a: f7fe fa9d bl 800af78 <memset>
|
|
800ca3e: 4b05 ldr r3, [pc, #20] ; (800ca54 <std+0x38>)
|
|
800ca40: 6263 str r3, [r4, #36] ; 0x24
|
|
800ca42: 4b05 ldr r3, [pc, #20] ; (800ca58 <std+0x3c>)
|
|
800ca44: 62a3 str r3, [r4, #40] ; 0x28
|
|
800ca46: 4b05 ldr r3, [pc, #20] ; (800ca5c <std+0x40>)
|
|
800ca48: 62e3 str r3, [r4, #44] ; 0x2c
|
|
800ca4a: 4b05 ldr r3, [pc, #20] ; (800ca60 <std+0x44>)
|
|
800ca4c: 6224 str r4, [r4, #32]
|
|
800ca4e: 6323 str r3, [r4, #48] ; 0x30
|
|
800ca50: bd10 pop {r4, pc}
|
|
800ca52: bf00 nop
|
|
800ca54: 0800db11 .word 0x0800db11
|
|
800ca58: 0800db33 .word 0x0800db33
|
|
800ca5c: 0800db6b .word 0x0800db6b
|
|
800ca60: 0800db8f .word 0x0800db8f
|
|
|
|
0800ca64 <_cleanup_r>:
|
|
800ca64: 4901 ldr r1, [pc, #4] ; (800ca6c <_cleanup_r+0x8>)
|
|
800ca66: f000 b8c1 b.w 800cbec <_fwalk_reent>
|
|
800ca6a: bf00 nop
|
|
800ca6c: 0800c9a5 .word 0x0800c9a5
|
|
|
|
0800ca70 <__sfmoreglue>:
|
|
800ca70: b570 push {r4, r5, r6, lr}
|
|
800ca72: 1e4a subs r2, r1, #1
|
|
800ca74: 2568 movs r5, #104 ; 0x68
|
|
800ca76: 4355 muls r5, r2
|
|
800ca78: 460e mov r6, r1
|
|
800ca7a: f105 0174 add.w r1, r5, #116 ; 0x74
|
|
800ca7e: f000 fd27 bl 800d4d0 <_malloc_r>
|
|
800ca82: 4604 mov r4, r0
|
|
800ca84: b140 cbz r0, 800ca98 <__sfmoreglue+0x28>
|
|
800ca86: 2100 movs r1, #0
|
|
800ca88: e9c0 1600 strd r1, r6, [r0]
|
|
800ca8c: 300c adds r0, #12
|
|
800ca8e: 60a0 str r0, [r4, #8]
|
|
800ca90: f105 0268 add.w r2, r5, #104 ; 0x68
|
|
800ca94: f7fe fa70 bl 800af78 <memset>
|
|
800ca98: 4620 mov r0, r4
|
|
800ca9a: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0800ca9c <__sfp_lock_acquire>:
|
|
800ca9c: 4801 ldr r0, [pc, #4] ; (800caa4 <__sfp_lock_acquire+0x8>)
|
|
800ca9e: f000 b8ca b.w 800cc36 <__retarget_lock_acquire_recursive>
|
|
800caa2: bf00 nop
|
|
800caa4: 20000a84 .word 0x20000a84
|
|
|
|
0800caa8 <__sfp_lock_release>:
|
|
800caa8: 4801 ldr r0, [pc, #4] ; (800cab0 <__sfp_lock_release+0x8>)
|
|
800caaa: f000 b8c5 b.w 800cc38 <__retarget_lock_release_recursive>
|
|
800caae: bf00 nop
|
|
800cab0: 20000a84 .word 0x20000a84
|
|
|
|
0800cab4 <__sinit_lock_acquire>:
|
|
800cab4: 4801 ldr r0, [pc, #4] ; (800cabc <__sinit_lock_acquire+0x8>)
|
|
800cab6: f000 b8be b.w 800cc36 <__retarget_lock_acquire_recursive>
|
|
800caba: bf00 nop
|
|
800cabc: 20000a7f .word 0x20000a7f
|
|
|
|
0800cac0 <__sinit_lock_release>:
|
|
800cac0: 4801 ldr r0, [pc, #4] ; (800cac8 <__sinit_lock_release+0x8>)
|
|
800cac2: f000 b8b9 b.w 800cc38 <__retarget_lock_release_recursive>
|
|
800cac6: bf00 nop
|
|
800cac8: 20000a7f .word 0x20000a7f
|
|
|
|
0800cacc <__sinit>:
|
|
800cacc: b510 push {r4, lr}
|
|
800cace: 4604 mov r4, r0
|
|
800cad0: f7ff fff0 bl 800cab4 <__sinit_lock_acquire>
|
|
800cad4: 69a3 ldr r3, [r4, #24]
|
|
800cad6: b11b cbz r3, 800cae0 <__sinit+0x14>
|
|
800cad8: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
800cadc: f7ff bff0 b.w 800cac0 <__sinit_lock_release>
|
|
800cae0: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48
|
|
800cae4: 6523 str r3, [r4, #80] ; 0x50
|
|
800cae6: 4b13 ldr r3, [pc, #76] ; (800cb34 <__sinit+0x68>)
|
|
800cae8: 4a13 ldr r2, [pc, #76] ; (800cb38 <__sinit+0x6c>)
|
|
800caea: 681b ldr r3, [r3, #0]
|
|
800caec: 62a2 str r2, [r4, #40] ; 0x28
|
|
800caee: 42a3 cmp r3, r4
|
|
800caf0: bf04 itt eq
|
|
800caf2: 2301 moveq r3, #1
|
|
800caf4: 61a3 streq r3, [r4, #24]
|
|
800caf6: 4620 mov r0, r4
|
|
800caf8: f000 f820 bl 800cb3c <__sfp>
|
|
800cafc: 6060 str r0, [r4, #4]
|
|
800cafe: 4620 mov r0, r4
|
|
800cb00: f000 f81c bl 800cb3c <__sfp>
|
|
800cb04: 60a0 str r0, [r4, #8]
|
|
800cb06: 4620 mov r0, r4
|
|
800cb08: f000 f818 bl 800cb3c <__sfp>
|
|
800cb0c: 2200 movs r2, #0
|
|
800cb0e: 60e0 str r0, [r4, #12]
|
|
800cb10: 2104 movs r1, #4
|
|
800cb12: 6860 ldr r0, [r4, #4]
|
|
800cb14: f7ff ff82 bl 800ca1c <std>
|
|
800cb18: 68a0 ldr r0, [r4, #8]
|
|
800cb1a: 2201 movs r2, #1
|
|
800cb1c: 2109 movs r1, #9
|
|
800cb1e: f7ff ff7d bl 800ca1c <std>
|
|
800cb22: 68e0 ldr r0, [r4, #12]
|
|
800cb24: 2202 movs r2, #2
|
|
800cb26: 2112 movs r1, #18
|
|
800cb28: f7ff ff78 bl 800ca1c <std>
|
|
800cb2c: 2301 movs r3, #1
|
|
800cb2e: 61a3 str r3, [r4, #24]
|
|
800cb30: e7d2 b.n 800cad8 <__sinit+0xc>
|
|
800cb32: bf00 nop
|
|
800cb34: 0800e3f4 .word 0x0800e3f4
|
|
800cb38: 0800ca65 .word 0x0800ca65
|
|
|
|
0800cb3c <__sfp>:
|
|
800cb3c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800cb3e: 4607 mov r7, r0
|
|
800cb40: f7ff ffac bl 800ca9c <__sfp_lock_acquire>
|
|
800cb44: 4b1e ldr r3, [pc, #120] ; (800cbc0 <__sfp+0x84>)
|
|
800cb46: 681e ldr r6, [r3, #0]
|
|
800cb48: 69b3 ldr r3, [r6, #24]
|
|
800cb4a: b913 cbnz r3, 800cb52 <__sfp+0x16>
|
|
800cb4c: 4630 mov r0, r6
|
|
800cb4e: f7ff ffbd bl 800cacc <__sinit>
|
|
800cb52: 3648 adds r6, #72 ; 0x48
|
|
800cb54: e9d6 3401 ldrd r3, r4, [r6, #4]
|
|
800cb58: 3b01 subs r3, #1
|
|
800cb5a: d503 bpl.n 800cb64 <__sfp+0x28>
|
|
800cb5c: 6833 ldr r3, [r6, #0]
|
|
800cb5e: b30b cbz r3, 800cba4 <__sfp+0x68>
|
|
800cb60: 6836 ldr r6, [r6, #0]
|
|
800cb62: e7f7 b.n 800cb54 <__sfp+0x18>
|
|
800cb64: f9b4 500c ldrsh.w r5, [r4, #12]
|
|
800cb68: b9d5 cbnz r5, 800cba0 <__sfp+0x64>
|
|
800cb6a: 4b16 ldr r3, [pc, #88] ; (800cbc4 <__sfp+0x88>)
|
|
800cb6c: 60e3 str r3, [r4, #12]
|
|
800cb6e: f104 0058 add.w r0, r4, #88 ; 0x58
|
|
800cb72: 6665 str r5, [r4, #100] ; 0x64
|
|
800cb74: f000 f85e bl 800cc34 <__retarget_lock_init_recursive>
|
|
800cb78: f7ff ff96 bl 800caa8 <__sfp_lock_release>
|
|
800cb7c: e9c4 5501 strd r5, r5, [r4, #4]
|
|
800cb80: e9c4 5504 strd r5, r5, [r4, #16]
|
|
800cb84: 6025 str r5, [r4, #0]
|
|
800cb86: 61a5 str r5, [r4, #24]
|
|
800cb88: 2208 movs r2, #8
|
|
800cb8a: 4629 mov r1, r5
|
|
800cb8c: f104 005c add.w r0, r4, #92 ; 0x5c
|
|
800cb90: f7fe f9f2 bl 800af78 <memset>
|
|
800cb94: e9c4 550d strd r5, r5, [r4, #52] ; 0x34
|
|
800cb98: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48
|
|
800cb9c: 4620 mov r0, r4
|
|
800cb9e: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
800cba0: 3468 adds r4, #104 ; 0x68
|
|
800cba2: e7d9 b.n 800cb58 <__sfp+0x1c>
|
|
800cba4: 2104 movs r1, #4
|
|
800cba6: 4638 mov r0, r7
|
|
800cba8: f7ff ff62 bl 800ca70 <__sfmoreglue>
|
|
800cbac: 4604 mov r4, r0
|
|
800cbae: 6030 str r0, [r6, #0]
|
|
800cbb0: 2800 cmp r0, #0
|
|
800cbb2: d1d5 bne.n 800cb60 <__sfp+0x24>
|
|
800cbb4: f7ff ff78 bl 800caa8 <__sfp_lock_release>
|
|
800cbb8: 230c movs r3, #12
|
|
800cbba: 603b str r3, [r7, #0]
|
|
800cbbc: e7ee b.n 800cb9c <__sfp+0x60>
|
|
800cbbe: bf00 nop
|
|
800cbc0: 0800e3f4 .word 0x0800e3f4
|
|
800cbc4: ffff0001 .word 0xffff0001
|
|
|
|
0800cbc8 <fiprintf>:
|
|
800cbc8: b40e push {r1, r2, r3}
|
|
800cbca: b503 push {r0, r1, lr}
|
|
800cbcc: 4601 mov r1, r0
|
|
800cbce: ab03 add r3, sp, #12
|
|
800cbd0: 4805 ldr r0, [pc, #20] ; (800cbe8 <fiprintf+0x20>)
|
|
800cbd2: f853 2b04 ldr.w r2, [r3], #4
|
|
800cbd6: 6800 ldr r0, [r0, #0]
|
|
800cbd8: 9301 str r3, [sp, #4]
|
|
800cbda: f000 fe59 bl 800d890 <_vfiprintf_r>
|
|
800cbde: b002 add sp, #8
|
|
800cbe0: f85d eb04 ldr.w lr, [sp], #4
|
|
800cbe4: b003 add sp, #12
|
|
800cbe6: 4770 bx lr
|
|
800cbe8: 20000278 .word 0x20000278
|
|
|
|
0800cbec <_fwalk_reent>:
|
|
800cbec: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
800cbf0: 4606 mov r6, r0
|
|
800cbf2: 4688 mov r8, r1
|
|
800cbf4: f100 0448 add.w r4, r0, #72 ; 0x48
|
|
800cbf8: 2700 movs r7, #0
|
|
800cbfa: e9d4 9501 ldrd r9, r5, [r4, #4]
|
|
800cbfe: f1b9 0901 subs.w r9, r9, #1
|
|
800cc02: d505 bpl.n 800cc10 <_fwalk_reent+0x24>
|
|
800cc04: 6824 ldr r4, [r4, #0]
|
|
800cc06: 2c00 cmp r4, #0
|
|
800cc08: d1f7 bne.n 800cbfa <_fwalk_reent+0xe>
|
|
800cc0a: 4638 mov r0, r7
|
|
800cc0c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
800cc10: 89ab ldrh r3, [r5, #12]
|
|
800cc12: 2b01 cmp r3, #1
|
|
800cc14: d907 bls.n 800cc26 <_fwalk_reent+0x3a>
|
|
800cc16: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
800cc1a: 3301 adds r3, #1
|
|
800cc1c: d003 beq.n 800cc26 <_fwalk_reent+0x3a>
|
|
800cc1e: 4629 mov r1, r5
|
|
800cc20: 4630 mov r0, r6
|
|
800cc22: 47c0 blx r8
|
|
800cc24: 4307 orrs r7, r0
|
|
800cc26: 3568 adds r5, #104 ; 0x68
|
|
800cc28: e7e9 b.n 800cbfe <_fwalk_reent+0x12>
|
|
...
|
|
|
|
0800cc2c <_localeconv_r>:
|
|
800cc2c: 4800 ldr r0, [pc, #0] ; (800cc30 <_localeconv_r+0x4>)
|
|
800cc2e: 4770 bx lr
|
|
800cc30: 200003cc .word 0x200003cc
|
|
|
|
0800cc34 <__retarget_lock_init_recursive>:
|
|
800cc34: 4770 bx lr
|
|
|
|
0800cc36 <__retarget_lock_acquire_recursive>:
|
|
800cc36: 4770 bx lr
|
|
|
|
0800cc38 <__retarget_lock_release_recursive>:
|
|
800cc38: 4770 bx lr
|
|
|
|
0800cc3a <__swhatbuf_r>:
|
|
800cc3a: b570 push {r4, r5, r6, lr}
|
|
800cc3c: 460e mov r6, r1
|
|
800cc3e: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800cc42: 2900 cmp r1, #0
|
|
800cc44: b096 sub sp, #88 ; 0x58
|
|
800cc46: 4614 mov r4, r2
|
|
800cc48: 461d mov r5, r3
|
|
800cc4a: da07 bge.n 800cc5c <__swhatbuf_r+0x22>
|
|
800cc4c: 2300 movs r3, #0
|
|
800cc4e: 602b str r3, [r5, #0]
|
|
800cc50: 89b3 ldrh r3, [r6, #12]
|
|
800cc52: 061a lsls r2, r3, #24
|
|
800cc54: d410 bmi.n 800cc78 <__swhatbuf_r+0x3e>
|
|
800cc56: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
800cc5a: e00e b.n 800cc7a <__swhatbuf_r+0x40>
|
|
800cc5c: 466a mov r2, sp
|
|
800cc5e: f000 ffc5 bl 800dbec <_fstat_r>
|
|
800cc62: 2800 cmp r0, #0
|
|
800cc64: dbf2 blt.n 800cc4c <__swhatbuf_r+0x12>
|
|
800cc66: 9a01 ldr r2, [sp, #4]
|
|
800cc68: f402 4270 and.w r2, r2, #61440 ; 0xf000
|
|
800cc6c: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000
|
|
800cc70: 425a negs r2, r3
|
|
800cc72: 415a adcs r2, r3
|
|
800cc74: 602a str r2, [r5, #0]
|
|
800cc76: e7ee b.n 800cc56 <__swhatbuf_r+0x1c>
|
|
800cc78: 2340 movs r3, #64 ; 0x40
|
|
800cc7a: 2000 movs r0, #0
|
|
800cc7c: 6023 str r3, [r4, #0]
|
|
800cc7e: b016 add sp, #88 ; 0x58
|
|
800cc80: bd70 pop {r4, r5, r6, pc}
|
|
...
|
|
|
|
0800cc84 <__smakebuf_r>:
|
|
800cc84: 898b ldrh r3, [r1, #12]
|
|
800cc86: b573 push {r0, r1, r4, r5, r6, lr}
|
|
800cc88: 079d lsls r5, r3, #30
|
|
800cc8a: 4606 mov r6, r0
|
|
800cc8c: 460c mov r4, r1
|
|
800cc8e: d507 bpl.n 800cca0 <__smakebuf_r+0x1c>
|
|
800cc90: f104 0347 add.w r3, r4, #71 ; 0x47
|
|
800cc94: 6023 str r3, [r4, #0]
|
|
800cc96: 6123 str r3, [r4, #16]
|
|
800cc98: 2301 movs r3, #1
|
|
800cc9a: 6163 str r3, [r4, #20]
|
|
800cc9c: b002 add sp, #8
|
|
800cc9e: bd70 pop {r4, r5, r6, pc}
|
|
800cca0: ab01 add r3, sp, #4
|
|
800cca2: 466a mov r2, sp
|
|
800cca4: f7ff ffc9 bl 800cc3a <__swhatbuf_r>
|
|
800cca8: 9900 ldr r1, [sp, #0]
|
|
800ccaa: 4605 mov r5, r0
|
|
800ccac: 4630 mov r0, r6
|
|
800ccae: f000 fc0f bl 800d4d0 <_malloc_r>
|
|
800ccb2: b948 cbnz r0, 800ccc8 <__smakebuf_r+0x44>
|
|
800ccb4: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
800ccb8: 059a lsls r2, r3, #22
|
|
800ccba: d4ef bmi.n 800cc9c <__smakebuf_r+0x18>
|
|
800ccbc: f023 0303 bic.w r3, r3, #3
|
|
800ccc0: f043 0302 orr.w r3, r3, #2
|
|
800ccc4: 81a3 strh r3, [r4, #12]
|
|
800ccc6: e7e3 b.n 800cc90 <__smakebuf_r+0xc>
|
|
800ccc8: 4b0d ldr r3, [pc, #52] ; (800cd00 <__smakebuf_r+0x7c>)
|
|
800ccca: 62b3 str r3, [r6, #40] ; 0x28
|
|
800cccc: 89a3 ldrh r3, [r4, #12]
|
|
800ccce: 6020 str r0, [r4, #0]
|
|
800ccd0: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
800ccd4: 81a3 strh r3, [r4, #12]
|
|
800ccd6: 9b00 ldr r3, [sp, #0]
|
|
800ccd8: 6163 str r3, [r4, #20]
|
|
800ccda: 9b01 ldr r3, [sp, #4]
|
|
800ccdc: 6120 str r0, [r4, #16]
|
|
800ccde: b15b cbz r3, 800ccf8 <__smakebuf_r+0x74>
|
|
800cce0: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
800cce4: 4630 mov r0, r6
|
|
800cce6: f000 ff93 bl 800dc10 <_isatty_r>
|
|
800ccea: b128 cbz r0, 800ccf8 <__smakebuf_r+0x74>
|
|
800ccec: 89a3 ldrh r3, [r4, #12]
|
|
800ccee: f023 0303 bic.w r3, r3, #3
|
|
800ccf2: f043 0301 orr.w r3, r3, #1
|
|
800ccf6: 81a3 strh r3, [r4, #12]
|
|
800ccf8: 89a0 ldrh r0, [r4, #12]
|
|
800ccfa: 4305 orrs r5, r0
|
|
800ccfc: 81a5 strh r5, [r4, #12]
|
|
800ccfe: e7cd b.n 800cc9c <__smakebuf_r+0x18>
|
|
800cd00: 0800ca65 .word 0x0800ca65
|
|
|
|
0800cd04 <malloc>:
|
|
800cd04: 4b02 ldr r3, [pc, #8] ; (800cd10 <malloc+0xc>)
|
|
800cd06: 4601 mov r1, r0
|
|
800cd08: 6818 ldr r0, [r3, #0]
|
|
800cd0a: f000 bbe1 b.w 800d4d0 <_malloc_r>
|
|
800cd0e: bf00 nop
|
|
800cd10: 20000278 .word 0x20000278
|
|
|
|
0800cd14 <_Balloc>:
|
|
800cd14: b570 push {r4, r5, r6, lr}
|
|
800cd16: 6a46 ldr r6, [r0, #36] ; 0x24
|
|
800cd18: 4604 mov r4, r0
|
|
800cd1a: 460d mov r5, r1
|
|
800cd1c: b976 cbnz r6, 800cd3c <_Balloc+0x28>
|
|
800cd1e: 2010 movs r0, #16
|
|
800cd20: f7ff fff0 bl 800cd04 <malloc>
|
|
800cd24: 4602 mov r2, r0
|
|
800cd26: 6260 str r0, [r4, #36] ; 0x24
|
|
800cd28: b920 cbnz r0, 800cd34 <_Balloc+0x20>
|
|
800cd2a: 4b18 ldr r3, [pc, #96] ; (800cd8c <_Balloc+0x78>)
|
|
800cd2c: 4818 ldr r0, [pc, #96] ; (800cd90 <_Balloc+0x7c>)
|
|
800cd2e: 2166 movs r1, #102 ; 0x66
|
|
800cd30: f7fe ff1a bl 800bb68 <__assert_func>
|
|
800cd34: e9c0 6601 strd r6, r6, [r0, #4]
|
|
800cd38: 6006 str r6, [r0, #0]
|
|
800cd3a: 60c6 str r6, [r0, #12]
|
|
800cd3c: 6a66 ldr r6, [r4, #36] ; 0x24
|
|
800cd3e: 68f3 ldr r3, [r6, #12]
|
|
800cd40: b183 cbz r3, 800cd64 <_Balloc+0x50>
|
|
800cd42: 6a63 ldr r3, [r4, #36] ; 0x24
|
|
800cd44: 68db ldr r3, [r3, #12]
|
|
800cd46: f853 0025 ldr.w r0, [r3, r5, lsl #2]
|
|
800cd4a: b9b8 cbnz r0, 800cd7c <_Balloc+0x68>
|
|
800cd4c: 2101 movs r1, #1
|
|
800cd4e: fa01 f605 lsl.w r6, r1, r5
|
|
800cd52: 1d72 adds r2, r6, #5
|
|
800cd54: 0092 lsls r2, r2, #2
|
|
800cd56: 4620 mov r0, r4
|
|
800cd58: f000 fb5a bl 800d410 <_calloc_r>
|
|
800cd5c: b160 cbz r0, 800cd78 <_Balloc+0x64>
|
|
800cd5e: e9c0 5601 strd r5, r6, [r0, #4]
|
|
800cd62: e00e b.n 800cd82 <_Balloc+0x6e>
|
|
800cd64: 2221 movs r2, #33 ; 0x21
|
|
800cd66: 2104 movs r1, #4
|
|
800cd68: 4620 mov r0, r4
|
|
800cd6a: f000 fb51 bl 800d410 <_calloc_r>
|
|
800cd6e: 6a63 ldr r3, [r4, #36] ; 0x24
|
|
800cd70: 60f0 str r0, [r6, #12]
|
|
800cd72: 68db ldr r3, [r3, #12]
|
|
800cd74: 2b00 cmp r3, #0
|
|
800cd76: d1e4 bne.n 800cd42 <_Balloc+0x2e>
|
|
800cd78: 2000 movs r0, #0
|
|
800cd7a: bd70 pop {r4, r5, r6, pc}
|
|
800cd7c: 6802 ldr r2, [r0, #0]
|
|
800cd7e: f843 2025 str.w r2, [r3, r5, lsl #2]
|
|
800cd82: 2300 movs r3, #0
|
|
800cd84: e9c0 3303 strd r3, r3, [r0, #12]
|
|
800cd88: e7f7 b.n 800cd7a <_Balloc+0x66>
|
|
800cd8a: bf00 nop
|
|
800cd8c: 0800e576 .word 0x0800e576
|
|
800cd90: 0800e660 .word 0x0800e660
|
|
|
|
0800cd94 <_Bfree>:
|
|
800cd94: b570 push {r4, r5, r6, lr}
|
|
800cd96: 6a46 ldr r6, [r0, #36] ; 0x24
|
|
800cd98: 4605 mov r5, r0
|
|
800cd9a: 460c mov r4, r1
|
|
800cd9c: b976 cbnz r6, 800cdbc <_Bfree+0x28>
|
|
800cd9e: 2010 movs r0, #16
|
|
800cda0: f7ff ffb0 bl 800cd04 <malloc>
|
|
800cda4: 4602 mov r2, r0
|
|
800cda6: 6268 str r0, [r5, #36] ; 0x24
|
|
800cda8: b920 cbnz r0, 800cdb4 <_Bfree+0x20>
|
|
800cdaa: 4b09 ldr r3, [pc, #36] ; (800cdd0 <_Bfree+0x3c>)
|
|
800cdac: 4809 ldr r0, [pc, #36] ; (800cdd4 <_Bfree+0x40>)
|
|
800cdae: 218a movs r1, #138 ; 0x8a
|
|
800cdb0: f7fe feda bl 800bb68 <__assert_func>
|
|
800cdb4: e9c0 6601 strd r6, r6, [r0, #4]
|
|
800cdb8: 6006 str r6, [r0, #0]
|
|
800cdba: 60c6 str r6, [r0, #12]
|
|
800cdbc: b13c cbz r4, 800cdce <_Bfree+0x3a>
|
|
800cdbe: 6a6b ldr r3, [r5, #36] ; 0x24
|
|
800cdc0: 6862 ldr r2, [r4, #4]
|
|
800cdc2: 68db ldr r3, [r3, #12]
|
|
800cdc4: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
800cdc8: 6021 str r1, [r4, #0]
|
|
800cdca: f843 4022 str.w r4, [r3, r2, lsl #2]
|
|
800cdce: bd70 pop {r4, r5, r6, pc}
|
|
800cdd0: 0800e576 .word 0x0800e576
|
|
800cdd4: 0800e660 .word 0x0800e660
|
|
|
|
0800cdd8 <__multadd>:
|
|
800cdd8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
800cddc: 690e ldr r6, [r1, #16]
|
|
800cdde: 4607 mov r7, r0
|
|
800cde0: 4698 mov r8, r3
|
|
800cde2: 460c mov r4, r1
|
|
800cde4: f101 0014 add.w r0, r1, #20
|
|
800cde8: 2300 movs r3, #0
|
|
800cdea: 6805 ldr r5, [r0, #0]
|
|
800cdec: b2a9 uxth r1, r5
|
|
800cdee: fb02 8101 mla r1, r2, r1, r8
|
|
800cdf2: ea4f 4c11 mov.w ip, r1, lsr #16
|
|
800cdf6: 0c2d lsrs r5, r5, #16
|
|
800cdf8: fb02 c505 mla r5, r2, r5, ip
|
|
800cdfc: b289 uxth r1, r1
|
|
800cdfe: 3301 adds r3, #1
|
|
800ce00: eb01 4105 add.w r1, r1, r5, lsl #16
|
|
800ce04: 429e cmp r6, r3
|
|
800ce06: f840 1b04 str.w r1, [r0], #4
|
|
800ce0a: ea4f 4815 mov.w r8, r5, lsr #16
|
|
800ce0e: dcec bgt.n 800cdea <__multadd+0x12>
|
|
800ce10: f1b8 0f00 cmp.w r8, #0
|
|
800ce14: d022 beq.n 800ce5c <__multadd+0x84>
|
|
800ce16: 68a3 ldr r3, [r4, #8]
|
|
800ce18: 42b3 cmp r3, r6
|
|
800ce1a: dc19 bgt.n 800ce50 <__multadd+0x78>
|
|
800ce1c: 6861 ldr r1, [r4, #4]
|
|
800ce1e: 4638 mov r0, r7
|
|
800ce20: 3101 adds r1, #1
|
|
800ce22: f7ff ff77 bl 800cd14 <_Balloc>
|
|
800ce26: 4605 mov r5, r0
|
|
800ce28: b928 cbnz r0, 800ce36 <__multadd+0x5e>
|
|
800ce2a: 4602 mov r2, r0
|
|
800ce2c: 4b0d ldr r3, [pc, #52] ; (800ce64 <__multadd+0x8c>)
|
|
800ce2e: 480e ldr r0, [pc, #56] ; (800ce68 <__multadd+0x90>)
|
|
800ce30: 21b5 movs r1, #181 ; 0xb5
|
|
800ce32: f7fe fe99 bl 800bb68 <__assert_func>
|
|
800ce36: 6922 ldr r2, [r4, #16]
|
|
800ce38: 3202 adds r2, #2
|
|
800ce3a: f104 010c add.w r1, r4, #12
|
|
800ce3e: 0092 lsls r2, r2, #2
|
|
800ce40: 300c adds r0, #12
|
|
800ce42: f7fe f88b bl 800af5c <memcpy>
|
|
800ce46: 4621 mov r1, r4
|
|
800ce48: 4638 mov r0, r7
|
|
800ce4a: f7ff ffa3 bl 800cd94 <_Bfree>
|
|
800ce4e: 462c mov r4, r5
|
|
800ce50: eb04 0386 add.w r3, r4, r6, lsl #2
|
|
800ce54: 3601 adds r6, #1
|
|
800ce56: f8c3 8014 str.w r8, [r3, #20]
|
|
800ce5a: 6126 str r6, [r4, #16]
|
|
800ce5c: 4620 mov r0, r4
|
|
800ce5e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
800ce62: bf00 nop
|
|
800ce64: 0800e5ec .word 0x0800e5ec
|
|
800ce68: 0800e660 .word 0x0800e660
|
|
|
|
0800ce6c <__hi0bits>:
|
|
800ce6c: 0c03 lsrs r3, r0, #16
|
|
800ce6e: 041b lsls r3, r3, #16
|
|
800ce70: b9d3 cbnz r3, 800cea8 <__hi0bits+0x3c>
|
|
800ce72: 0400 lsls r0, r0, #16
|
|
800ce74: 2310 movs r3, #16
|
|
800ce76: f010 4f7f tst.w r0, #4278190080 ; 0xff000000
|
|
800ce7a: bf04 itt eq
|
|
800ce7c: 0200 lsleq r0, r0, #8
|
|
800ce7e: 3308 addeq r3, #8
|
|
800ce80: f010 4f70 tst.w r0, #4026531840 ; 0xf0000000
|
|
800ce84: bf04 itt eq
|
|
800ce86: 0100 lsleq r0, r0, #4
|
|
800ce88: 3304 addeq r3, #4
|
|
800ce8a: f010 4f40 tst.w r0, #3221225472 ; 0xc0000000
|
|
800ce8e: bf04 itt eq
|
|
800ce90: 0080 lsleq r0, r0, #2
|
|
800ce92: 3302 addeq r3, #2
|
|
800ce94: 2800 cmp r0, #0
|
|
800ce96: db05 blt.n 800cea4 <__hi0bits+0x38>
|
|
800ce98: f010 4f80 tst.w r0, #1073741824 ; 0x40000000
|
|
800ce9c: f103 0301 add.w r3, r3, #1
|
|
800cea0: bf08 it eq
|
|
800cea2: 2320 moveq r3, #32
|
|
800cea4: 4618 mov r0, r3
|
|
800cea6: 4770 bx lr
|
|
800cea8: 2300 movs r3, #0
|
|
800ceaa: e7e4 b.n 800ce76 <__hi0bits+0xa>
|
|
|
|
0800ceac <__lo0bits>:
|
|
800ceac: 6803 ldr r3, [r0, #0]
|
|
800ceae: f013 0207 ands.w r2, r3, #7
|
|
800ceb2: 4601 mov r1, r0
|
|
800ceb4: d00b beq.n 800cece <__lo0bits+0x22>
|
|
800ceb6: 07da lsls r2, r3, #31
|
|
800ceb8: d424 bmi.n 800cf04 <__lo0bits+0x58>
|
|
800ceba: 0798 lsls r0, r3, #30
|
|
800cebc: bf49 itett mi
|
|
800cebe: 085b lsrmi r3, r3, #1
|
|
800cec0: 089b lsrpl r3, r3, #2
|
|
800cec2: 2001 movmi r0, #1
|
|
800cec4: 600b strmi r3, [r1, #0]
|
|
800cec6: bf5c itt pl
|
|
800cec8: 600b strpl r3, [r1, #0]
|
|
800ceca: 2002 movpl r0, #2
|
|
800cecc: 4770 bx lr
|
|
800cece: b298 uxth r0, r3
|
|
800ced0: b9b0 cbnz r0, 800cf00 <__lo0bits+0x54>
|
|
800ced2: 0c1b lsrs r3, r3, #16
|
|
800ced4: 2010 movs r0, #16
|
|
800ced6: f013 0fff tst.w r3, #255 ; 0xff
|
|
800ceda: bf04 itt eq
|
|
800cedc: 0a1b lsreq r3, r3, #8
|
|
800cede: 3008 addeq r0, #8
|
|
800cee0: 071a lsls r2, r3, #28
|
|
800cee2: bf04 itt eq
|
|
800cee4: 091b lsreq r3, r3, #4
|
|
800cee6: 3004 addeq r0, #4
|
|
800cee8: 079a lsls r2, r3, #30
|
|
800ceea: bf04 itt eq
|
|
800ceec: 089b lsreq r3, r3, #2
|
|
800ceee: 3002 addeq r0, #2
|
|
800cef0: 07da lsls r2, r3, #31
|
|
800cef2: d403 bmi.n 800cefc <__lo0bits+0x50>
|
|
800cef4: 085b lsrs r3, r3, #1
|
|
800cef6: f100 0001 add.w r0, r0, #1
|
|
800cefa: d005 beq.n 800cf08 <__lo0bits+0x5c>
|
|
800cefc: 600b str r3, [r1, #0]
|
|
800cefe: 4770 bx lr
|
|
800cf00: 4610 mov r0, r2
|
|
800cf02: e7e8 b.n 800ced6 <__lo0bits+0x2a>
|
|
800cf04: 2000 movs r0, #0
|
|
800cf06: 4770 bx lr
|
|
800cf08: 2020 movs r0, #32
|
|
800cf0a: 4770 bx lr
|
|
|
|
0800cf0c <__i2b>:
|
|
800cf0c: b510 push {r4, lr}
|
|
800cf0e: 460c mov r4, r1
|
|
800cf10: 2101 movs r1, #1
|
|
800cf12: f7ff feff bl 800cd14 <_Balloc>
|
|
800cf16: 4602 mov r2, r0
|
|
800cf18: b928 cbnz r0, 800cf26 <__i2b+0x1a>
|
|
800cf1a: 4b05 ldr r3, [pc, #20] ; (800cf30 <__i2b+0x24>)
|
|
800cf1c: 4805 ldr r0, [pc, #20] ; (800cf34 <__i2b+0x28>)
|
|
800cf1e: f44f 71a0 mov.w r1, #320 ; 0x140
|
|
800cf22: f7fe fe21 bl 800bb68 <__assert_func>
|
|
800cf26: 2301 movs r3, #1
|
|
800cf28: 6144 str r4, [r0, #20]
|
|
800cf2a: 6103 str r3, [r0, #16]
|
|
800cf2c: bd10 pop {r4, pc}
|
|
800cf2e: bf00 nop
|
|
800cf30: 0800e5ec .word 0x0800e5ec
|
|
800cf34: 0800e660 .word 0x0800e660
|
|
|
|
0800cf38 <__multiply>:
|
|
800cf38: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800cf3c: 4614 mov r4, r2
|
|
800cf3e: 690a ldr r2, [r1, #16]
|
|
800cf40: 6923 ldr r3, [r4, #16]
|
|
800cf42: 429a cmp r2, r3
|
|
800cf44: bfb8 it lt
|
|
800cf46: 460b movlt r3, r1
|
|
800cf48: 460d mov r5, r1
|
|
800cf4a: bfbc itt lt
|
|
800cf4c: 4625 movlt r5, r4
|
|
800cf4e: 461c movlt r4, r3
|
|
800cf50: f8d5 a010 ldr.w sl, [r5, #16]
|
|
800cf54: f8d4 9010 ldr.w r9, [r4, #16]
|
|
800cf58: 68ab ldr r3, [r5, #8]
|
|
800cf5a: 6869 ldr r1, [r5, #4]
|
|
800cf5c: eb0a 0709 add.w r7, sl, r9
|
|
800cf60: 42bb cmp r3, r7
|
|
800cf62: b085 sub sp, #20
|
|
800cf64: bfb8 it lt
|
|
800cf66: 3101 addlt r1, #1
|
|
800cf68: f7ff fed4 bl 800cd14 <_Balloc>
|
|
800cf6c: b930 cbnz r0, 800cf7c <__multiply+0x44>
|
|
800cf6e: 4602 mov r2, r0
|
|
800cf70: 4b42 ldr r3, [pc, #264] ; (800d07c <__multiply+0x144>)
|
|
800cf72: 4843 ldr r0, [pc, #268] ; (800d080 <__multiply+0x148>)
|
|
800cf74: f240 115d movw r1, #349 ; 0x15d
|
|
800cf78: f7fe fdf6 bl 800bb68 <__assert_func>
|
|
800cf7c: f100 0614 add.w r6, r0, #20
|
|
800cf80: eb06 0887 add.w r8, r6, r7, lsl #2
|
|
800cf84: 4633 mov r3, r6
|
|
800cf86: 2200 movs r2, #0
|
|
800cf88: 4543 cmp r3, r8
|
|
800cf8a: d31e bcc.n 800cfca <__multiply+0x92>
|
|
800cf8c: f105 0c14 add.w ip, r5, #20
|
|
800cf90: f104 0314 add.w r3, r4, #20
|
|
800cf94: eb0c 0c8a add.w ip, ip, sl, lsl #2
|
|
800cf98: eb03 0289 add.w r2, r3, r9, lsl #2
|
|
800cf9c: 9202 str r2, [sp, #8]
|
|
800cf9e: ebac 0205 sub.w r2, ip, r5
|
|
800cfa2: 3a15 subs r2, #21
|
|
800cfa4: f022 0203 bic.w r2, r2, #3
|
|
800cfa8: 3204 adds r2, #4
|
|
800cfaa: f105 0115 add.w r1, r5, #21
|
|
800cfae: 458c cmp ip, r1
|
|
800cfb0: bf38 it cc
|
|
800cfb2: 2204 movcc r2, #4
|
|
800cfb4: 9201 str r2, [sp, #4]
|
|
800cfb6: 9a02 ldr r2, [sp, #8]
|
|
800cfb8: 9303 str r3, [sp, #12]
|
|
800cfba: 429a cmp r2, r3
|
|
800cfbc: d808 bhi.n 800cfd0 <__multiply+0x98>
|
|
800cfbe: 2f00 cmp r7, #0
|
|
800cfc0: dc55 bgt.n 800d06e <__multiply+0x136>
|
|
800cfc2: 6107 str r7, [r0, #16]
|
|
800cfc4: b005 add sp, #20
|
|
800cfc6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800cfca: f843 2b04 str.w r2, [r3], #4
|
|
800cfce: e7db b.n 800cf88 <__multiply+0x50>
|
|
800cfd0: f8b3 a000 ldrh.w sl, [r3]
|
|
800cfd4: f1ba 0f00 cmp.w sl, #0
|
|
800cfd8: d020 beq.n 800d01c <__multiply+0xe4>
|
|
800cfda: f105 0e14 add.w lr, r5, #20
|
|
800cfde: 46b1 mov r9, r6
|
|
800cfe0: 2200 movs r2, #0
|
|
800cfe2: f85e 4b04 ldr.w r4, [lr], #4
|
|
800cfe6: f8d9 b000 ldr.w fp, [r9]
|
|
800cfea: b2a1 uxth r1, r4
|
|
800cfec: fa1f fb8b uxth.w fp, fp
|
|
800cff0: fb0a b101 mla r1, sl, r1, fp
|
|
800cff4: 4411 add r1, r2
|
|
800cff6: f8d9 2000 ldr.w r2, [r9]
|
|
800cffa: 0c24 lsrs r4, r4, #16
|
|
800cffc: 0c12 lsrs r2, r2, #16
|
|
800cffe: fb0a 2404 mla r4, sl, r4, r2
|
|
800d002: eb04 4411 add.w r4, r4, r1, lsr #16
|
|
800d006: b289 uxth r1, r1
|
|
800d008: ea41 4104 orr.w r1, r1, r4, lsl #16
|
|
800d00c: 45f4 cmp ip, lr
|
|
800d00e: f849 1b04 str.w r1, [r9], #4
|
|
800d012: ea4f 4214 mov.w r2, r4, lsr #16
|
|
800d016: d8e4 bhi.n 800cfe2 <__multiply+0xaa>
|
|
800d018: 9901 ldr r1, [sp, #4]
|
|
800d01a: 5072 str r2, [r6, r1]
|
|
800d01c: 9a03 ldr r2, [sp, #12]
|
|
800d01e: f8b2 9002 ldrh.w r9, [r2, #2]
|
|
800d022: 3304 adds r3, #4
|
|
800d024: f1b9 0f00 cmp.w r9, #0
|
|
800d028: d01f beq.n 800d06a <__multiply+0x132>
|
|
800d02a: 6834 ldr r4, [r6, #0]
|
|
800d02c: f105 0114 add.w r1, r5, #20
|
|
800d030: 46b6 mov lr, r6
|
|
800d032: f04f 0a00 mov.w sl, #0
|
|
800d036: 880a ldrh r2, [r1, #0]
|
|
800d038: f8be b002 ldrh.w fp, [lr, #2]
|
|
800d03c: fb09 b202 mla r2, r9, r2, fp
|
|
800d040: 4492 add sl, r2
|
|
800d042: b2a4 uxth r4, r4
|
|
800d044: ea44 440a orr.w r4, r4, sl, lsl #16
|
|
800d048: f84e 4b04 str.w r4, [lr], #4
|
|
800d04c: f851 4b04 ldr.w r4, [r1], #4
|
|
800d050: f8be 2000 ldrh.w r2, [lr]
|
|
800d054: 0c24 lsrs r4, r4, #16
|
|
800d056: fb09 2404 mla r4, r9, r4, r2
|
|
800d05a: eb04 441a add.w r4, r4, sl, lsr #16
|
|
800d05e: 458c cmp ip, r1
|
|
800d060: ea4f 4a14 mov.w sl, r4, lsr #16
|
|
800d064: d8e7 bhi.n 800d036 <__multiply+0xfe>
|
|
800d066: 9a01 ldr r2, [sp, #4]
|
|
800d068: 50b4 str r4, [r6, r2]
|
|
800d06a: 3604 adds r6, #4
|
|
800d06c: e7a3 b.n 800cfb6 <__multiply+0x7e>
|
|
800d06e: f858 3d04 ldr.w r3, [r8, #-4]!
|
|
800d072: 2b00 cmp r3, #0
|
|
800d074: d1a5 bne.n 800cfc2 <__multiply+0x8a>
|
|
800d076: 3f01 subs r7, #1
|
|
800d078: e7a1 b.n 800cfbe <__multiply+0x86>
|
|
800d07a: bf00 nop
|
|
800d07c: 0800e5ec .word 0x0800e5ec
|
|
800d080: 0800e660 .word 0x0800e660
|
|
|
|
0800d084 <__pow5mult>:
|
|
800d084: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
800d088: 4615 mov r5, r2
|
|
800d08a: f012 0203 ands.w r2, r2, #3
|
|
800d08e: 4606 mov r6, r0
|
|
800d090: 460f mov r7, r1
|
|
800d092: d007 beq.n 800d0a4 <__pow5mult+0x20>
|
|
800d094: 4c25 ldr r4, [pc, #148] ; (800d12c <__pow5mult+0xa8>)
|
|
800d096: 3a01 subs r2, #1
|
|
800d098: 2300 movs r3, #0
|
|
800d09a: f854 2022 ldr.w r2, [r4, r2, lsl #2]
|
|
800d09e: f7ff fe9b bl 800cdd8 <__multadd>
|
|
800d0a2: 4607 mov r7, r0
|
|
800d0a4: 10ad asrs r5, r5, #2
|
|
800d0a6: d03d beq.n 800d124 <__pow5mult+0xa0>
|
|
800d0a8: 6a74 ldr r4, [r6, #36] ; 0x24
|
|
800d0aa: b97c cbnz r4, 800d0cc <__pow5mult+0x48>
|
|
800d0ac: 2010 movs r0, #16
|
|
800d0ae: f7ff fe29 bl 800cd04 <malloc>
|
|
800d0b2: 4602 mov r2, r0
|
|
800d0b4: 6270 str r0, [r6, #36] ; 0x24
|
|
800d0b6: b928 cbnz r0, 800d0c4 <__pow5mult+0x40>
|
|
800d0b8: 4b1d ldr r3, [pc, #116] ; (800d130 <__pow5mult+0xac>)
|
|
800d0ba: 481e ldr r0, [pc, #120] ; (800d134 <__pow5mult+0xb0>)
|
|
800d0bc: f44f 71d7 mov.w r1, #430 ; 0x1ae
|
|
800d0c0: f7fe fd52 bl 800bb68 <__assert_func>
|
|
800d0c4: e9c0 4401 strd r4, r4, [r0, #4]
|
|
800d0c8: 6004 str r4, [r0, #0]
|
|
800d0ca: 60c4 str r4, [r0, #12]
|
|
800d0cc: f8d6 8024 ldr.w r8, [r6, #36] ; 0x24
|
|
800d0d0: f8d8 4008 ldr.w r4, [r8, #8]
|
|
800d0d4: b94c cbnz r4, 800d0ea <__pow5mult+0x66>
|
|
800d0d6: f240 2171 movw r1, #625 ; 0x271
|
|
800d0da: 4630 mov r0, r6
|
|
800d0dc: f7ff ff16 bl 800cf0c <__i2b>
|
|
800d0e0: 2300 movs r3, #0
|
|
800d0e2: f8c8 0008 str.w r0, [r8, #8]
|
|
800d0e6: 4604 mov r4, r0
|
|
800d0e8: 6003 str r3, [r0, #0]
|
|
800d0ea: f04f 0900 mov.w r9, #0
|
|
800d0ee: 07eb lsls r3, r5, #31
|
|
800d0f0: d50a bpl.n 800d108 <__pow5mult+0x84>
|
|
800d0f2: 4639 mov r1, r7
|
|
800d0f4: 4622 mov r2, r4
|
|
800d0f6: 4630 mov r0, r6
|
|
800d0f8: f7ff ff1e bl 800cf38 <__multiply>
|
|
800d0fc: 4639 mov r1, r7
|
|
800d0fe: 4680 mov r8, r0
|
|
800d100: 4630 mov r0, r6
|
|
800d102: f7ff fe47 bl 800cd94 <_Bfree>
|
|
800d106: 4647 mov r7, r8
|
|
800d108: 106d asrs r5, r5, #1
|
|
800d10a: d00b beq.n 800d124 <__pow5mult+0xa0>
|
|
800d10c: 6820 ldr r0, [r4, #0]
|
|
800d10e: b938 cbnz r0, 800d120 <__pow5mult+0x9c>
|
|
800d110: 4622 mov r2, r4
|
|
800d112: 4621 mov r1, r4
|
|
800d114: 4630 mov r0, r6
|
|
800d116: f7ff ff0f bl 800cf38 <__multiply>
|
|
800d11a: 6020 str r0, [r4, #0]
|
|
800d11c: f8c0 9000 str.w r9, [r0]
|
|
800d120: 4604 mov r4, r0
|
|
800d122: e7e4 b.n 800d0ee <__pow5mult+0x6a>
|
|
800d124: 4638 mov r0, r7
|
|
800d126: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
800d12a: bf00 nop
|
|
800d12c: 0800e7b0 .word 0x0800e7b0
|
|
800d130: 0800e576 .word 0x0800e576
|
|
800d134: 0800e660 .word 0x0800e660
|
|
|
|
0800d138 <__lshift>:
|
|
800d138: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800d13c: 460c mov r4, r1
|
|
800d13e: 6849 ldr r1, [r1, #4]
|
|
800d140: 6923 ldr r3, [r4, #16]
|
|
800d142: eb03 1862 add.w r8, r3, r2, asr #5
|
|
800d146: 68a3 ldr r3, [r4, #8]
|
|
800d148: 4607 mov r7, r0
|
|
800d14a: 4691 mov r9, r2
|
|
800d14c: ea4f 1a62 mov.w sl, r2, asr #5
|
|
800d150: f108 0601 add.w r6, r8, #1
|
|
800d154: 42b3 cmp r3, r6
|
|
800d156: db0b blt.n 800d170 <__lshift+0x38>
|
|
800d158: 4638 mov r0, r7
|
|
800d15a: f7ff fddb bl 800cd14 <_Balloc>
|
|
800d15e: 4605 mov r5, r0
|
|
800d160: b948 cbnz r0, 800d176 <__lshift+0x3e>
|
|
800d162: 4602 mov r2, r0
|
|
800d164: 4b28 ldr r3, [pc, #160] ; (800d208 <__lshift+0xd0>)
|
|
800d166: 4829 ldr r0, [pc, #164] ; (800d20c <__lshift+0xd4>)
|
|
800d168: f240 11d9 movw r1, #473 ; 0x1d9
|
|
800d16c: f7fe fcfc bl 800bb68 <__assert_func>
|
|
800d170: 3101 adds r1, #1
|
|
800d172: 005b lsls r3, r3, #1
|
|
800d174: e7ee b.n 800d154 <__lshift+0x1c>
|
|
800d176: 2300 movs r3, #0
|
|
800d178: f100 0114 add.w r1, r0, #20
|
|
800d17c: f100 0210 add.w r2, r0, #16
|
|
800d180: 4618 mov r0, r3
|
|
800d182: 4553 cmp r3, sl
|
|
800d184: db33 blt.n 800d1ee <__lshift+0xb6>
|
|
800d186: 6920 ldr r0, [r4, #16]
|
|
800d188: ea2a 7aea bic.w sl, sl, sl, asr #31
|
|
800d18c: f104 0314 add.w r3, r4, #20
|
|
800d190: f019 091f ands.w r9, r9, #31
|
|
800d194: eb01 018a add.w r1, r1, sl, lsl #2
|
|
800d198: eb03 0c80 add.w ip, r3, r0, lsl #2
|
|
800d19c: d02b beq.n 800d1f6 <__lshift+0xbe>
|
|
800d19e: f1c9 0e20 rsb lr, r9, #32
|
|
800d1a2: 468a mov sl, r1
|
|
800d1a4: 2200 movs r2, #0
|
|
800d1a6: 6818 ldr r0, [r3, #0]
|
|
800d1a8: fa00 f009 lsl.w r0, r0, r9
|
|
800d1ac: 4302 orrs r2, r0
|
|
800d1ae: f84a 2b04 str.w r2, [sl], #4
|
|
800d1b2: f853 2b04 ldr.w r2, [r3], #4
|
|
800d1b6: 459c cmp ip, r3
|
|
800d1b8: fa22 f20e lsr.w r2, r2, lr
|
|
800d1bc: d8f3 bhi.n 800d1a6 <__lshift+0x6e>
|
|
800d1be: ebac 0304 sub.w r3, ip, r4
|
|
800d1c2: 3b15 subs r3, #21
|
|
800d1c4: f023 0303 bic.w r3, r3, #3
|
|
800d1c8: 3304 adds r3, #4
|
|
800d1ca: f104 0015 add.w r0, r4, #21
|
|
800d1ce: 4584 cmp ip, r0
|
|
800d1d0: bf38 it cc
|
|
800d1d2: 2304 movcc r3, #4
|
|
800d1d4: 50ca str r2, [r1, r3]
|
|
800d1d6: b10a cbz r2, 800d1dc <__lshift+0xa4>
|
|
800d1d8: f108 0602 add.w r6, r8, #2
|
|
800d1dc: 3e01 subs r6, #1
|
|
800d1de: 4638 mov r0, r7
|
|
800d1e0: 612e str r6, [r5, #16]
|
|
800d1e2: 4621 mov r1, r4
|
|
800d1e4: f7ff fdd6 bl 800cd94 <_Bfree>
|
|
800d1e8: 4628 mov r0, r5
|
|
800d1ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800d1ee: f842 0f04 str.w r0, [r2, #4]!
|
|
800d1f2: 3301 adds r3, #1
|
|
800d1f4: e7c5 b.n 800d182 <__lshift+0x4a>
|
|
800d1f6: 3904 subs r1, #4
|
|
800d1f8: f853 2b04 ldr.w r2, [r3], #4
|
|
800d1fc: f841 2f04 str.w r2, [r1, #4]!
|
|
800d200: 459c cmp ip, r3
|
|
800d202: d8f9 bhi.n 800d1f8 <__lshift+0xc0>
|
|
800d204: e7ea b.n 800d1dc <__lshift+0xa4>
|
|
800d206: bf00 nop
|
|
800d208: 0800e5ec .word 0x0800e5ec
|
|
800d20c: 0800e660 .word 0x0800e660
|
|
|
|
0800d210 <__mcmp>:
|
|
800d210: b530 push {r4, r5, lr}
|
|
800d212: 6902 ldr r2, [r0, #16]
|
|
800d214: 690c ldr r4, [r1, #16]
|
|
800d216: 1b12 subs r2, r2, r4
|
|
800d218: d10e bne.n 800d238 <__mcmp+0x28>
|
|
800d21a: f100 0314 add.w r3, r0, #20
|
|
800d21e: 3114 adds r1, #20
|
|
800d220: eb03 0084 add.w r0, r3, r4, lsl #2
|
|
800d224: eb01 0184 add.w r1, r1, r4, lsl #2
|
|
800d228: f850 5d04 ldr.w r5, [r0, #-4]!
|
|
800d22c: f851 4d04 ldr.w r4, [r1, #-4]!
|
|
800d230: 42a5 cmp r5, r4
|
|
800d232: d003 beq.n 800d23c <__mcmp+0x2c>
|
|
800d234: d305 bcc.n 800d242 <__mcmp+0x32>
|
|
800d236: 2201 movs r2, #1
|
|
800d238: 4610 mov r0, r2
|
|
800d23a: bd30 pop {r4, r5, pc}
|
|
800d23c: 4283 cmp r3, r0
|
|
800d23e: d3f3 bcc.n 800d228 <__mcmp+0x18>
|
|
800d240: e7fa b.n 800d238 <__mcmp+0x28>
|
|
800d242: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
800d246: e7f7 b.n 800d238 <__mcmp+0x28>
|
|
|
|
0800d248 <__mdiff>:
|
|
800d248: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800d24c: 460c mov r4, r1
|
|
800d24e: 4606 mov r6, r0
|
|
800d250: 4611 mov r1, r2
|
|
800d252: 4620 mov r0, r4
|
|
800d254: 4617 mov r7, r2
|
|
800d256: f7ff ffdb bl 800d210 <__mcmp>
|
|
800d25a: 1e05 subs r5, r0, #0
|
|
800d25c: d110 bne.n 800d280 <__mdiff+0x38>
|
|
800d25e: 4629 mov r1, r5
|
|
800d260: 4630 mov r0, r6
|
|
800d262: f7ff fd57 bl 800cd14 <_Balloc>
|
|
800d266: b930 cbnz r0, 800d276 <__mdiff+0x2e>
|
|
800d268: 4b39 ldr r3, [pc, #228] ; (800d350 <__mdiff+0x108>)
|
|
800d26a: 4602 mov r2, r0
|
|
800d26c: f240 2132 movw r1, #562 ; 0x232
|
|
800d270: 4838 ldr r0, [pc, #224] ; (800d354 <__mdiff+0x10c>)
|
|
800d272: f7fe fc79 bl 800bb68 <__assert_func>
|
|
800d276: 2301 movs r3, #1
|
|
800d278: e9c0 3504 strd r3, r5, [r0, #16]
|
|
800d27c: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800d280: bfa4 itt ge
|
|
800d282: 463b movge r3, r7
|
|
800d284: 4627 movge r7, r4
|
|
800d286: 4630 mov r0, r6
|
|
800d288: 6879 ldr r1, [r7, #4]
|
|
800d28a: bfa6 itte ge
|
|
800d28c: 461c movge r4, r3
|
|
800d28e: 2500 movge r5, #0
|
|
800d290: 2501 movlt r5, #1
|
|
800d292: f7ff fd3f bl 800cd14 <_Balloc>
|
|
800d296: b920 cbnz r0, 800d2a2 <__mdiff+0x5a>
|
|
800d298: 4b2d ldr r3, [pc, #180] ; (800d350 <__mdiff+0x108>)
|
|
800d29a: 4602 mov r2, r0
|
|
800d29c: f44f 7110 mov.w r1, #576 ; 0x240
|
|
800d2a0: e7e6 b.n 800d270 <__mdiff+0x28>
|
|
800d2a2: 693e ldr r6, [r7, #16]
|
|
800d2a4: 60c5 str r5, [r0, #12]
|
|
800d2a6: 6925 ldr r5, [r4, #16]
|
|
800d2a8: f107 0114 add.w r1, r7, #20
|
|
800d2ac: f104 0914 add.w r9, r4, #20
|
|
800d2b0: f100 0e14 add.w lr, r0, #20
|
|
800d2b4: f107 0210 add.w r2, r7, #16
|
|
800d2b8: eb01 0c86 add.w ip, r1, r6, lsl #2
|
|
800d2bc: eb09 0585 add.w r5, r9, r5, lsl #2
|
|
800d2c0: 46f2 mov sl, lr
|
|
800d2c2: 2700 movs r7, #0
|
|
800d2c4: f859 3b04 ldr.w r3, [r9], #4
|
|
800d2c8: f852 bf04 ldr.w fp, [r2, #4]!
|
|
800d2cc: fa1f f883 uxth.w r8, r3
|
|
800d2d0: fa17 f78b uxtah r7, r7, fp
|
|
800d2d4: 0c1b lsrs r3, r3, #16
|
|
800d2d6: eba7 0808 sub.w r8, r7, r8
|
|
800d2da: ebc3 431b rsb r3, r3, fp, lsr #16
|
|
800d2de: eb03 4328 add.w r3, r3, r8, asr #16
|
|
800d2e2: fa1f f888 uxth.w r8, r8
|
|
800d2e6: 141f asrs r7, r3, #16
|
|
800d2e8: 454d cmp r5, r9
|
|
800d2ea: ea48 4303 orr.w r3, r8, r3, lsl #16
|
|
800d2ee: f84a 3b04 str.w r3, [sl], #4
|
|
800d2f2: d8e7 bhi.n 800d2c4 <__mdiff+0x7c>
|
|
800d2f4: 1b2b subs r3, r5, r4
|
|
800d2f6: 3b15 subs r3, #21
|
|
800d2f8: f023 0303 bic.w r3, r3, #3
|
|
800d2fc: 3304 adds r3, #4
|
|
800d2fe: 3415 adds r4, #21
|
|
800d300: 42a5 cmp r5, r4
|
|
800d302: bf38 it cc
|
|
800d304: 2304 movcc r3, #4
|
|
800d306: 4419 add r1, r3
|
|
800d308: 4473 add r3, lr
|
|
800d30a: 469e mov lr, r3
|
|
800d30c: 460d mov r5, r1
|
|
800d30e: 4565 cmp r5, ip
|
|
800d310: d30e bcc.n 800d330 <__mdiff+0xe8>
|
|
800d312: f10c 0203 add.w r2, ip, #3
|
|
800d316: 1a52 subs r2, r2, r1
|
|
800d318: f022 0203 bic.w r2, r2, #3
|
|
800d31c: 3903 subs r1, #3
|
|
800d31e: 458c cmp ip, r1
|
|
800d320: bf38 it cc
|
|
800d322: 2200 movcc r2, #0
|
|
800d324: 441a add r2, r3
|
|
800d326: f852 3d04 ldr.w r3, [r2, #-4]!
|
|
800d32a: b17b cbz r3, 800d34c <__mdiff+0x104>
|
|
800d32c: 6106 str r6, [r0, #16]
|
|
800d32e: e7a5 b.n 800d27c <__mdiff+0x34>
|
|
800d330: f855 8b04 ldr.w r8, [r5], #4
|
|
800d334: fa17 f488 uxtah r4, r7, r8
|
|
800d338: 1422 asrs r2, r4, #16
|
|
800d33a: eb02 4218 add.w r2, r2, r8, lsr #16
|
|
800d33e: b2a4 uxth r4, r4
|
|
800d340: ea44 4402 orr.w r4, r4, r2, lsl #16
|
|
800d344: f84e 4b04 str.w r4, [lr], #4
|
|
800d348: 1417 asrs r7, r2, #16
|
|
800d34a: e7e0 b.n 800d30e <__mdiff+0xc6>
|
|
800d34c: 3e01 subs r6, #1
|
|
800d34e: e7ea b.n 800d326 <__mdiff+0xde>
|
|
800d350: 0800e5ec .word 0x0800e5ec
|
|
800d354: 0800e660 .word 0x0800e660
|
|
|
|
0800d358 <__d2b>:
|
|
800d358: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
|
|
800d35c: 4689 mov r9, r1
|
|
800d35e: 2101 movs r1, #1
|
|
800d360: ec57 6b10 vmov r6, r7, d0
|
|
800d364: 4690 mov r8, r2
|
|
800d366: f7ff fcd5 bl 800cd14 <_Balloc>
|
|
800d36a: 4604 mov r4, r0
|
|
800d36c: b930 cbnz r0, 800d37c <__d2b+0x24>
|
|
800d36e: 4602 mov r2, r0
|
|
800d370: 4b25 ldr r3, [pc, #148] ; (800d408 <__d2b+0xb0>)
|
|
800d372: 4826 ldr r0, [pc, #152] ; (800d40c <__d2b+0xb4>)
|
|
800d374: f240 310a movw r1, #778 ; 0x30a
|
|
800d378: f7fe fbf6 bl 800bb68 <__assert_func>
|
|
800d37c: f3c7 550a ubfx r5, r7, #20, #11
|
|
800d380: f3c7 0313 ubfx r3, r7, #0, #20
|
|
800d384: bb35 cbnz r5, 800d3d4 <__d2b+0x7c>
|
|
800d386: 2e00 cmp r6, #0
|
|
800d388: 9301 str r3, [sp, #4]
|
|
800d38a: d028 beq.n 800d3de <__d2b+0x86>
|
|
800d38c: 4668 mov r0, sp
|
|
800d38e: 9600 str r6, [sp, #0]
|
|
800d390: f7ff fd8c bl 800ceac <__lo0bits>
|
|
800d394: 9900 ldr r1, [sp, #0]
|
|
800d396: b300 cbz r0, 800d3da <__d2b+0x82>
|
|
800d398: 9a01 ldr r2, [sp, #4]
|
|
800d39a: f1c0 0320 rsb r3, r0, #32
|
|
800d39e: fa02 f303 lsl.w r3, r2, r3
|
|
800d3a2: 430b orrs r3, r1
|
|
800d3a4: 40c2 lsrs r2, r0
|
|
800d3a6: 6163 str r3, [r4, #20]
|
|
800d3a8: 9201 str r2, [sp, #4]
|
|
800d3aa: 9b01 ldr r3, [sp, #4]
|
|
800d3ac: 61a3 str r3, [r4, #24]
|
|
800d3ae: 2b00 cmp r3, #0
|
|
800d3b0: bf14 ite ne
|
|
800d3b2: 2202 movne r2, #2
|
|
800d3b4: 2201 moveq r2, #1
|
|
800d3b6: 6122 str r2, [r4, #16]
|
|
800d3b8: b1d5 cbz r5, 800d3f0 <__d2b+0x98>
|
|
800d3ba: f2a5 4533 subw r5, r5, #1075 ; 0x433
|
|
800d3be: 4405 add r5, r0
|
|
800d3c0: f8c9 5000 str.w r5, [r9]
|
|
800d3c4: f1c0 0035 rsb r0, r0, #53 ; 0x35
|
|
800d3c8: f8c8 0000 str.w r0, [r8]
|
|
800d3cc: 4620 mov r0, r4
|
|
800d3ce: b003 add sp, #12
|
|
800d3d0: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
800d3d4: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
|
|
800d3d8: e7d5 b.n 800d386 <__d2b+0x2e>
|
|
800d3da: 6161 str r1, [r4, #20]
|
|
800d3dc: e7e5 b.n 800d3aa <__d2b+0x52>
|
|
800d3de: a801 add r0, sp, #4
|
|
800d3e0: f7ff fd64 bl 800ceac <__lo0bits>
|
|
800d3e4: 9b01 ldr r3, [sp, #4]
|
|
800d3e6: 6163 str r3, [r4, #20]
|
|
800d3e8: 2201 movs r2, #1
|
|
800d3ea: 6122 str r2, [r4, #16]
|
|
800d3ec: 3020 adds r0, #32
|
|
800d3ee: e7e3 b.n 800d3b8 <__d2b+0x60>
|
|
800d3f0: eb04 0382 add.w r3, r4, r2, lsl #2
|
|
800d3f4: f2a0 4032 subw r0, r0, #1074 ; 0x432
|
|
800d3f8: f8c9 0000 str.w r0, [r9]
|
|
800d3fc: 6918 ldr r0, [r3, #16]
|
|
800d3fe: f7ff fd35 bl 800ce6c <__hi0bits>
|
|
800d402: ebc0 1042 rsb r0, r0, r2, lsl #5
|
|
800d406: e7df b.n 800d3c8 <__d2b+0x70>
|
|
800d408: 0800e5ec .word 0x0800e5ec
|
|
800d40c: 0800e660 .word 0x0800e660
|
|
|
|
0800d410 <_calloc_r>:
|
|
800d410: b513 push {r0, r1, r4, lr}
|
|
800d412: 434a muls r2, r1
|
|
800d414: 4611 mov r1, r2
|
|
800d416: 9201 str r2, [sp, #4]
|
|
800d418: f000 f85a bl 800d4d0 <_malloc_r>
|
|
800d41c: 4604 mov r4, r0
|
|
800d41e: b118 cbz r0, 800d428 <_calloc_r+0x18>
|
|
800d420: 9a01 ldr r2, [sp, #4]
|
|
800d422: 2100 movs r1, #0
|
|
800d424: f7fd fda8 bl 800af78 <memset>
|
|
800d428: 4620 mov r0, r4
|
|
800d42a: b002 add sp, #8
|
|
800d42c: bd10 pop {r4, pc}
|
|
...
|
|
|
|
0800d430 <_free_r>:
|
|
800d430: b537 push {r0, r1, r2, r4, r5, lr}
|
|
800d432: 2900 cmp r1, #0
|
|
800d434: d048 beq.n 800d4c8 <_free_r+0x98>
|
|
800d436: f851 3c04 ldr.w r3, [r1, #-4]
|
|
800d43a: 9001 str r0, [sp, #4]
|
|
800d43c: 2b00 cmp r3, #0
|
|
800d43e: f1a1 0404 sub.w r4, r1, #4
|
|
800d442: bfb8 it lt
|
|
800d444: 18e4 addlt r4, r4, r3
|
|
800d446: f000 fc31 bl 800dcac <__malloc_lock>
|
|
800d44a: 4a20 ldr r2, [pc, #128] ; (800d4cc <_free_r+0x9c>)
|
|
800d44c: 9801 ldr r0, [sp, #4]
|
|
800d44e: 6813 ldr r3, [r2, #0]
|
|
800d450: 4615 mov r5, r2
|
|
800d452: b933 cbnz r3, 800d462 <_free_r+0x32>
|
|
800d454: 6063 str r3, [r4, #4]
|
|
800d456: 6014 str r4, [r2, #0]
|
|
800d458: b003 add sp, #12
|
|
800d45a: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
|
|
800d45e: f000 bc2b b.w 800dcb8 <__malloc_unlock>
|
|
800d462: 42a3 cmp r3, r4
|
|
800d464: d90b bls.n 800d47e <_free_r+0x4e>
|
|
800d466: 6821 ldr r1, [r4, #0]
|
|
800d468: 1862 adds r2, r4, r1
|
|
800d46a: 4293 cmp r3, r2
|
|
800d46c: bf04 itt eq
|
|
800d46e: 681a ldreq r2, [r3, #0]
|
|
800d470: 685b ldreq r3, [r3, #4]
|
|
800d472: 6063 str r3, [r4, #4]
|
|
800d474: bf04 itt eq
|
|
800d476: 1852 addeq r2, r2, r1
|
|
800d478: 6022 streq r2, [r4, #0]
|
|
800d47a: 602c str r4, [r5, #0]
|
|
800d47c: e7ec b.n 800d458 <_free_r+0x28>
|
|
800d47e: 461a mov r2, r3
|
|
800d480: 685b ldr r3, [r3, #4]
|
|
800d482: b10b cbz r3, 800d488 <_free_r+0x58>
|
|
800d484: 42a3 cmp r3, r4
|
|
800d486: d9fa bls.n 800d47e <_free_r+0x4e>
|
|
800d488: 6811 ldr r1, [r2, #0]
|
|
800d48a: 1855 adds r5, r2, r1
|
|
800d48c: 42a5 cmp r5, r4
|
|
800d48e: d10b bne.n 800d4a8 <_free_r+0x78>
|
|
800d490: 6824 ldr r4, [r4, #0]
|
|
800d492: 4421 add r1, r4
|
|
800d494: 1854 adds r4, r2, r1
|
|
800d496: 42a3 cmp r3, r4
|
|
800d498: 6011 str r1, [r2, #0]
|
|
800d49a: d1dd bne.n 800d458 <_free_r+0x28>
|
|
800d49c: 681c ldr r4, [r3, #0]
|
|
800d49e: 685b ldr r3, [r3, #4]
|
|
800d4a0: 6053 str r3, [r2, #4]
|
|
800d4a2: 4421 add r1, r4
|
|
800d4a4: 6011 str r1, [r2, #0]
|
|
800d4a6: e7d7 b.n 800d458 <_free_r+0x28>
|
|
800d4a8: d902 bls.n 800d4b0 <_free_r+0x80>
|
|
800d4aa: 230c movs r3, #12
|
|
800d4ac: 6003 str r3, [r0, #0]
|
|
800d4ae: e7d3 b.n 800d458 <_free_r+0x28>
|
|
800d4b0: 6825 ldr r5, [r4, #0]
|
|
800d4b2: 1961 adds r1, r4, r5
|
|
800d4b4: 428b cmp r3, r1
|
|
800d4b6: bf04 itt eq
|
|
800d4b8: 6819 ldreq r1, [r3, #0]
|
|
800d4ba: 685b ldreq r3, [r3, #4]
|
|
800d4bc: 6063 str r3, [r4, #4]
|
|
800d4be: bf04 itt eq
|
|
800d4c0: 1949 addeq r1, r1, r5
|
|
800d4c2: 6021 streq r1, [r4, #0]
|
|
800d4c4: 6054 str r4, [r2, #4]
|
|
800d4c6: e7c7 b.n 800d458 <_free_r+0x28>
|
|
800d4c8: b003 add sp, #12
|
|
800d4ca: bd30 pop {r4, r5, pc}
|
|
800d4cc: 20000570 .word 0x20000570
|
|
|
|
0800d4d0 <_malloc_r>:
|
|
800d4d0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800d4d2: 1ccd adds r5, r1, #3
|
|
800d4d4: f025 0503 bic.w r5, r5, #3
|
|
800d4d8: 3508 adds r5, #8
|
|
800d4da: 2d0c cmp r5, #12
|
|
800d4dc: bf38 it cc
|
|
800d4de: 250c movcc r5, #12
|
|
800d4e0: 2d00 cmp r5, #0
|
|
800d4e2: 4606 mov r6, r0
|
|
800d4e4: db01 blt.n 800d4ea <_malloc_r+0x1a>
|
|
800d4e6: 42a9 cmp r1, r5
|
|
800d4e8: d903 bls.n 800d4f2 <_malloc_r+0x22>
|
|
800d4ea: 230c movs r3, #12
|
|
800d4ec: 6033 str r3, [r6, #0]
|
|
800d4ee: 2000 movs r0, #0
|
|
800d4f0: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
800d4f2: f000 fbdb bl 800dcac <__malloc_lock>
|
|
800d4f6: 4921 ldr r1, [pc, #132] ; (800d57c <_malloc_r+0xac>)
|
|
800d4f8: 680a ldr r2, [r1, #0]
|
|
800d4fa: 4614 mov r4, r2
|
|
800d4fc: b99c cbnz r4, 800d526 <_malloc_r+0x56>
|
|
800d4fe: 4f20 ldr r7, [pc, #128] ; (800d580 <_malloc_r+0xb0>)
|
|
800d500: 683b ldr r3, [r7, #0]
|
|
800d502: b923 cbnz r3, 800d50e <_malloc_r+0x3e>
|
|
800d504: 4621 mov r1, r4
|
|
800d506: 4630 mov r0, r6
|
|
800d508: f000 faf2 bl 800daf0 <_sbrk_r>
|
|
800d50c: 6038 str r0, [r7, #0]
|
|
800d50e: 4629 mov r1, r5
|
|
800d510: 4630 mov r0, r6
|
|
800d512: f000 faed bl 800daf0 <_sbrk_r>
|
|
800d516: 1c43 adds r3, r0, #1
|
|
800d518: d123 bne.n 800d562 <_malloc_r+0x92>
|
|
800d51a: 230c movs r3, #12
|
|
800d51c: 6033 str r3, [r6, #0]
|
|
800d51e: 4630 mov r0, r6
|
|
800d520: f000 fbca bl 800dcb8 <__malloc_unlock>
|
|
800d524: e7e3 b.n 800d4ee <_malloc_r+0x1e>
|
|
800d526: 6823 ldr r3, [r4, #0]
|
|
800d528: 1b5b subs r3, r3, r5
|
|
800d52a: d417 bmi.n 800d55c <_malloc_r+0x8c>
|
|
800d52c: 2b0b cmp r3, #11
|
|
800d52e: d903 bls.n 800d538 <_malloc_r+0x68>
|
|
800d530: 6023 str r3, [r4, #0]
|
|
800d532: 441c add r4, r3
|
|
800d534: 6025 str r5, [r4, #0]
|
|
800d536: e004 b.n 800d542 <_malloc_r+0x72>
|
|
800d538: 6863 ldr r3, [r4, #4]
|
|
800d53a: 42a2 cmp r2, r4
|
|
800d53c: bf0c ite eq
|
|
800d53e: 600b streq r3, [r1, #0]
|
|
800d540: 6053 strne r3, [r2, #4]
|
|
800d542: 4630 mov r0, r6
|
|
800d544: f000 fbb8 bl 800dcb8 <__malloc_unlock>
|
|
800d548: f104 000b add.w r0, r4, #11
|
|
800d54c: 1d23 adds r3, r4, #4
|
|
800d54e: f020 0007 bic.w r0, r0, #7
|
|
800d552: 1ac2 subs r2, r0, r3
|
|
800d554: d0cc beq.n 800d4f0 <_malloc_r+0x20>
|
|
800d556: 1a1b subs r3, r3, r0
|
|
800d558: 50a3 str r3, [r4, r2]
|
|
800d55a: e7c9 b.n 800d4f0 <_malloc_r+0x20>
|
|
800d55c: 4622 mov r2, r4
|
|
800d55e: 6864 ldr r4, [r4, #4]
|
|
800d560: e7cc b.n 800d4fc <_malloc_r+0x2c>
|
|
800d562: 1cc4 adds r4, r0, #3
|
|
800d564: f024 0403 bic.w r4, r4, #3
|
|
800d568: 42a0 cmp r0, r4
|
|
800d56a: d0e3 beq.n 800d534 <_malloc_r+0x64>
|
|
800d56c: 1a21 subs r1, r4, r0
|
|
800d56e: 4630 mov r0, r6
|
|
800d570: f000 fabe bl 800daf0 <_sbrk_r>
|
|
800d574: 3001 adds r0, #1
|
|
800d576: d1dd bne.n 800d534 <_malloc_r+0x64>
|
|
800d578: e7cf b.n 800d51a <_malloc_r+0x4a>
|
|
800d57a: bf00 nop
|
|
800d57c: 20000570 .word 0x20000570
|
|
800d580: 20000574 .word 0x20000574
|
|
|
|
0800d584 <__ssputs_r>:
|
|
800d584: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
800d588: 688e ldr r6, [r1, #8]
|
|
800d58a: 429e cmp r6, r3
|
|
800d58c: 4682 mov sl, r0
|
|
800d58e: 460c mov r4, r1
|
|
800d590: 4690 mov r8, r2
|
|
800d592: 461f mov r7, r3
|
|
800d594: d838 bhi.n 800d608 <__ssputs_r+0x84>
|
|
800d596: 898a ldrh r2, [r1, #12]
|
|
800d598: f412 6f90 tst.w r2, #1152 ; 0x480
|
|
800d59c: d032 beq.n 800d604 <__ssputs_r+0x80>
|
|
800d59e: 6825 ldr r5, [r4, #0]
|
|
800d5a0: 6909 ldr r1, [r1, #16]
|
|
800d5a2: eba5 0901 sub.w r9, r5, r1
|
|
800d5a6: 6965 ldr r5, [r4, #20]
|
|
800d5a8: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
800d5ac: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
800d5b0: 3301 adds r3, #1
|
|
800d5b2: 444b add r3, r9
|
|
800d5b4: 106d asrs r5, r5, #1
|
|
800d5b6: 429d cmp r5, r3
|
|
800d5b8: bf38 it cc
|
|
800d5ba: 461d movcc r5, r3
|
|
800d5bc: 0553 lsls r3, r2, #21
|
|
800d5be: d531 bpl.n 800d624 <__ssputs_r+0xa0>
|
|
800d5c0: 4629 mov r1, r5
|
|
800d5c2: f7ff ff85 bl 800d4d0 <_malloc_r>
|
|
800d5c6: 4606 mov r6, r0
|
|
800d5c8: b950 cbnz r0, 800d5e0 <__ssputs_r+0x5c>
|
|
800d5ca: 230c movs r3, #12
|
|
800d5cc: f8ca 3000 str.w r3, [sl]
|
|
800d5d0: 89a3 ldrh r3, [r4, #12]
|
|
800d5d2: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
800d5d6: 81a3 strh r3, [r4, #12]
|
|
800d5d8: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800d5dc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
800d5e0: 6921 ldr r1, [r4, #16]
|
|
800d5e2: 464a mov r2, r9
|
|
800d5e4: f7fd fcba bl 800af5c <memcpy>
|
|
800d5e8: 89a3 ldrh r3, [r4, #12]
|
|
800d5ea: f423 6390 bic.w r3, r3, #1152 ; 0x480
|
|
800d5ee: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
800d5f2: 81a3 strh r3, [r4, #12]
|
|
800d5f4: 6126 str r6, [r4, #16]
|
|
800d5f6: 6165 str r5, [r4, #20]
|
|
800d5f8: 444e add r6, r9
|
|
800d5fa: eba5 0509 sub.w r5, r5, r9
|
|
800d5fe: 6026 str r6, [r4, #0]
|
|
800d600: 60a5 str r5, [r4, #8]
|
|
800d602: 463e mov r6, r7
|
|
800d604: 42be cmp r6, r7
|
|
800d606: d900 bls.n 800d60a <__ssputs_r+0x86>
|
|
800d608: 463e mov r6, r7
|
|
800d60a: 4632 mov r2, r6
|
|
800d60c: 6820 ldr r0, [r4, #0]
|
|
800d60e: 4641 mov r1, r8
|
|
800d610: f000 fb32 bl 800dc78 <memmove>
|
|
800d614: 68a3 ldr r3, [r4, #8]
|
|
800d616: 6822 ldr r2, [r4, #0]
|
|
800d618: 1b9b subs r3, r3, r6
|
|
800d61a: 4432 add r2, r6
|
|
800d61c: 60a3 str r3, [r4, #8]
|
|
800d61e: 6022 str r2, [r4, #0]
|
|
800d620: 2000 movs r0, #0
|
|
800d622: e7db b.n 800d5dc <__ssputs_r+0x58>
|
|
800d624: 462a mov r2, r5
|
|
800d626: f000 fb4d bl 800dcc4 <_realloc_r>
|
|
800d62a: 4606 mov r6, r0
|
|
800d62c: 2800 cmp r0, #0
|
|
800d62e: d1e1 bne.n 800d5f4 <__ssputs_r+0x70>
|
|
800d630: 6921 ldr r1, [r4, #16]
|
|
800d632: 4650 mov r0, sl
|
|
800d634: f7ff fefc bl 800d430 <_free_r>
|
|
800d638: e7c7 b.n 800d5ca <__ssputs_r+0x46>
|
|
...
|
|
|
|
0800d63c <_svfiprintf_r>:
|
|
800d63c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800d640: 4698 mov r8, r3
|
|
800d642: 898b ldrh r3, [r1, #12]
|
|
800d644: 061b lsls r3, r3, #24
|
|
800d646: b09d sub sp, #116 ; 0x74
|
|
800d648: 4607 mov r7, r0
|
|
800d64a: 460d mov r5, r1
|
|
800d64c: 4614 mov r4, r2
|
|
800d64e: d50e bpl.n 800d66e <_svfiprintf_r+0x32>
|
|
800d650: 690b ldr r3, [r1, #16]
|
|
800d652: b963 cbnz r3, 800d66e <_svfiprintf_r+0x32>
|
|
800d654: 2140 movs r1, #64 ; 0x40
|
|
800d656: f7ff ff3b bl 800d4d0 <_malloc_r>
|
|
800d65a: 6028 str r0, [r5, #0]
|
|
800d65c: 6128 str r0, [r5, #16]
|
|
800d65e: b920 cbnz r0, 800d66a <_svfiprintf_r+0x2e>
|
|
800d660: 230c movs r3, #12
|
|
800d662: 603b str r3, [r7, #0]
|
|
800d664: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800d668: e0d1 b.n 800d80e <_svfiprintf_r+0x1d2>
|
|
800d66a: 2340 movs r3, #64 ; 0x40
|
|
800d66c: 616b str r3, [r5, #20]
|
|
800d66e: 2300 movs r3, #0
|
|
800d670: 9309 str r3, [sp, #36] ; 0x24
|
|
800d672: 2320 movs r3, #32
|
|
800d674: f88d 3029 strb.w r3, [sp, #41] ; 0x29
|
|
800d678: f8cd 800c str.w r8, [sp, #12]
|
|
800d67c: 2330 movs r3, #48 ; 0x30
|
|
800d67e: f8df 81a8 ldr.w r8, [pc, #424] ; 800d828 <_svfiprintf_r+0x1ec>
|
|
800d682: f88d 302a strb.w r3, [sp, #42] ; 0x2a
|
|
800d686: f04f 0901 mov.w r9, #1
|
|
800d68a: 4623 mov r3, r4
|
|
800d68c: 469a mov sl, r3
|
|
800d68e: f813 2b01 ldrb.w r2, [r3], #1
|
|
800d692: b10a cbz r2, 800d698 <_svfiprintf_r+0x5c>
|
|
800d694: 2a25 cmp r2, #37 ; 0x25
|
|
800d696: d1f9 bne.n 800d68c <_svfiprintf_r+0x50>
|
|
800d698: ebba 0b04 subs.w fp, sl, r4
|
|
800d69c: d00b beq.n 800d6b6 <_svfiprintf_r+0x7a>
|
|
800d69e: 465b mov r3, fp
|
|
800d6a0: 4622 mov r2, r4
|
|
800d6a2: 4629 mov r1, r5
|
|
800d6a4: 4638 mov r0, r7
|
|
800d6a6: f7ff ff6d bl 800d584 <__ssputs_r>
|
|
800d6aa: 3001 adds r0, #1
|
|
800d6ac: f000 80aa beq.w 800d804 <_svfiprintf_r+0x1c8>
|
|
800d6b0: 9a09 ldr r2, [sp, #36] ; 0x24
|
|
800d6b2: 445a add r2, fp
|
|
800d6b4: 9209 str r2, [sp, #36] ; 0x24
|
|
800d6b6: f89a 3000 ldrb.w r3, [sl]
|
|
800d6ba: 2b00 cmp r3, #0
|
|
800d6bc: f000 80a2 beq.w 800d804 <_svfiprintf_r+0x1c8>
|
|
800d6c0: 2300 movs r3, #0
|
|
800d6c2: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
800d6c6: e9cd 2305 strd r2, r3, [sp, #20]
|
|
800d6ca: f10a 0a01 add.w sl, sl, #1
|
|
800d6ce: 9304 str r3, [sp, #16]
|
|
800d6d0: 9307 str r3, [sp, #28]
|
|
800d6d2: f88d 3053 strb.w r3, [sp, #83] ; 0x53
|
|
800d6d6: 931a str r3, [sp, #104] ; 0x68
|
|
800d6d8: 4654 mov r4, sl
|
|
800d6da: 2205 movs r2, #5
|
|
800d6dc: f814 1b01 ldrb.w r1, [r4], #1
|
|
800d6e0: 4851 ldr r0, [pc, #324] ; (800d828 <_svfiprintf_r+0x1ec>)
|
|
800d6e2: f7f2 fd7d bl 80001e0 <memchr>
|
|
800d6e6: 9a04 ldr r2, [sp, #16]
|
|
800d6e8: b9d8 cbnz r0, 800d722 <_svfiprintf_r+0xe6>
|
|
800d6ea: 06d0 lsls r0, r2, #27
|
|
800d6ec: bf44 itt mi
|
|
800d6ee: 2320 movmi r3, #32
|
|
800d6f0: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
800d6f4: 0711 lsls r1, r2, #28
|
|
800d6f6: bf44 itt mi
|
|
800d6f8: 232b movmi r3, #43 ; 0x2b
|
|
800d6fa: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
800d6fe: f89a 3000 ldrb.w r3, [sl]
|
|
800d702: 2b2a cmp r3, #42 ; 0x2a
|
|
800d704: d015 beq.n 800d732 <_svfiprintf_r+0xf6>
|
|
800d706: 9a07 ldr r2, [sp, #28]
|
|
800d708: 4654 mov r4, sl
|
|
800d70a: 2000 movs r0, #0
|
|
800d70c: f04f 0c0a mov.w ip, #10
|
|
800d710: 4621 mov r1, r4
|
|
800d712: f811 3b01 ldrb.w r3, [r1], #1
|
|
800d716: 3b30 subs r3, #48 ; 0x30
|
|
800d718: 2b09 cmp r3, #9
|
|
800d71a: d94e bls.n 800d7ba <_svfiprintf_r+0x17e>
|
|
800d71c: b1b0 cbz r0, 800d74c <_svfiprintf_r+0x110>
|
|
800d71e: 9207 str r2, [sp, #28]
|
|
800d720: e014 b.n 800d74c <_svfiprintf_r+0x110>
|
|
800d722: eba0 0308 sub.w r3, r0, r8
|
|
800d726: fa09 f303 lsl.w r3, r9, r3
|
|
800d72a: 4313 orrs r3, r2
|
|
800d72c: 9304 str r3, [sp, #16]
|
|
800d72e: 46a2 mov sl, r4
|
|
800d730: e7d2 b.n 800d6d8 <_svfiprintf_r+0x9c>
|
|
800d732: 9b03 ldr r3, [sp, #12]
|
|
800d734: 1d19 adds r1, r3, #4
|
|
800d736: 681b ldr r3, [r3, #0]
|
|
800d738: 9103 str r1, [sp, #12]
|
|
800d73a: 2b00 cmp r3, #0
|
|
800d73c: bfbb ittet lt
|
|
800d73e: 425b neglt r3, r3
|
|
800d740: f042 0202 orrlt.w r2, r2, #2
|
|
800d744: 9307 strge r3, [sp, #28]
|
|
800d746: 9307 strlt r3, [sp, #28]
|
|
800d748: bfb8 it lt
|
|
800d74a: 9204 strlt r2, [sp, #16]
|
|
800d74c: 7823 ldrb r3, [r4, #0]
|
|
800d74e: 2b2e cmp r3, #46 ; 0x2e
|
|
800d750: d10c bne.n 800d76c <_svfiprintf_r+0x130>
|
|
800d752: 7863 ldrb r3, [r4, #1]
|
|
800d754: 2b2a cmp r3, #42 ; 0x2a
|
|
800d756: d135 bne.n 800d7c4 <_svfiprintf_r+0x188>
|
|
800d758: 9b03 ldr r3, [sp, #12]
|
|
800d75a: 1d1a adds r2, r3, #4
|
|
800d75c: 681b ldr r3, [r3, #0]
|
|
800d75e: 9203 str r2, [sp, #12]
|
|
800d760: 2b00 cmp r3, #0
|
|
800d762: bfb8 it lt
|
|
800d764: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff
|
|
800d768: 3402 adds r4, #2
|
|
800d76a: 9305 str r3, [sp, #20]
|
|
800d76c: f8df a0c8 ldr.w sl, [pc, #200] ; 800d838 <_svfiprintf_r+0x1fc>
|
|
800d770: 7821 ldrb r1, [r4, #0]
|
|
800d772: 2203 movs r2, #3
|
|
800d774: 4650 mov r0, sl
|
|
800d776: f7f2 fd33 bl 80001e0 <memchr>
|
|
800d77a: b140 cbz r0, 800d78e <_svfiprintf_r+0x152>
|
|
800d77c: 2340 movs r3, #64 ; 0x40
|
|
800d77e: eba0 000a sub.w r0, r0, sl
|
|
800d782: fa03 f000 lsl.w r0, r3, r0
|
|
800d786: 9b04 ldr r3, [sp, #16]
|
|
800d788: 4303 orrs r3, r0
|
|
800d78a: 3401 adds r4, #1
|
|
800d78c: 9304 str r3, [sp, #16]
|
|
800d78e: f814 1b01 ldrb.w r1, [r4], #1
|
|
800d792: 4826 ldr r0, [pc, #152] ; (800d82c <_svfiprintf_r+0x1f0>)
|
|
800d794: f88d 1028 strb.w r1, [sp, #40] ; 0x28
|
|
800d798: 2206 movs r2, #6
|
|
800d79a: f7f2 fd21 bl 80001e0 <memchr>
|
|
800d79e: 2800 cmp r0, #0
|
|
800d7a0: d038 beq.n 800d814 <_svfiprintf_r+0x1d8>
|
|
800d7a2: 4b23 ldr r3, [pc, #140] ; (800d830 <_svfiprintf_r+0x1f4>)
|
|
800d7a4: bb1b cbnz r3, 800d7ee <_svfiprintf_r+0x1b2>
|
|
800d7a6: 9b03 ldr r3, [sp, #12]
|
|
800d7a8: 3307 adds r3, #7
|
|
800d7aa: f023 0307 bic.w r3, r3, #7
|
|
800d7ae: 3308 adds r3, #8
|
|
800d7b0: 9303 str r3, [sp, #12]
|
|
800d7b2: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800d7b4: 4433 add r3, r6
|
|
800d7b6: 9309 str r3, [sp, #36] ; 0x24
|
|
800d7b8: e767 b.n 800d68a <_svfiprintf_r+0x4e>
|
|
800d7ba: fb0c 3202 mla r2, ip, r2, r3
|
|
800d7be: 460c mov r4, r1
|
|
800d7c0: 2001 movs r0, #1
|
|
800d7c2: e7a5 b.n 800d710 <_svfiprintf_r+0xd4>
|
|
800d7c4: 2300 movs r3, #0
|
|
800d7c6: 3401 adds r4, #1
|
|
800d7c8: 9305 str r3, [sp, #20]
|
|
800d7ca: 4619 mov r1, r3
|
|
800d7cc: f04f 0c0a mov.w ip, #10
|
|
800d7d0: 4620 mov r0, r4
|
|
800d7d2: f810 2b01 ldrb.w r2, [r0], #1
|
|
800d7d6: 3a30 subs r2, #48 ; 0x30
|
|
800d7d8: 2a09 cmp r2, #9
|
|
800d7da: d903 bls.n 800d7e4 <_svfiprintf_r+0x1a8>
|
|
800d7dc: 2b00 cmp r3, #0
|
|
800d7de: d0c5 beq.n 800d76c <_svfiprintf_r+0x130>
|
|
800d7e0: 9105 str r1, [sp, #20]
|
|
800d7e2: e7c3 b.n 800d76c <_svfiprintf_r+0x130>
|
|
800d7e4: fb0c 2101 mla r1, ip, r1, r2
|
|
800d7e8: 4604 mov r4, r0
|
|
800d7ea: 2301 movs r3, #1
|
|
800d7ec: e7f0 b.n 800d7d0 <_svfiprintf_r+0x194>
|
|
800d7ee: ab03 add r3, sp, #12
|
|
800d7f0: 9300 str r3, [sp, #0]
|
|
800d7f2: 462a mov r2, r5
|
|
800d7f4: 4b0f ldr r3, [pc, #60] ; (800d834 <_svfiprintf_r+0x1f8>)
|
|
800d7f6: a904 add r1, sp, #16
|
|
800d7f8: 4638 mov r0, r7
|
|
800d7fa: f7fd fc65 bl 800b0c8 <_printf_float>
|
|
800d7fe: 1c42 adds r2, r0, #1
|
|
800d800: 4606 mov r6, r0
|
|
800d802: d1d6 bne.n 800d7b2 <_svfiprintf_r+0x176>
|
|
800d804: 89ab ldrh r3, [r5, #12]
|
|
800d806: 065b lsls r3, r3, #25
|
|
800d808: f53f af2c bmi.w 800d664 <_svfiprintf_r+0x28>
|
|
800d80c: 9809 ldr r0, [sp, #36] ; 0x24
|
|
800d80e: b01d add sp, #116 ; 0x74
|
|
800d810: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800d814: ab03 add r3, sp, #12
|
|
800d816: 9300 str r3, [sp, #0]
|
|
800d818: 462a mov r2, r5
|
|
800d81a: 4b06 ldr r3, [pc, #24] ; (800d834 <_svfiprintf_r+0x1f8>)
|
|
800d81c: a904 add r1, sp, #16
|
|
800d81e: 4638 mov r0, r7
|
|
800d820: f7fd fef6 bl 800b610 <_printf_i>
|
|
800d824: e7eb b.n 800d7fe <_svfiprintf_r+0x1c2>
|
|
800d826: bf00 nop
|
|
800d828: 0800e7bc .word 0x0800e7bc
|
|
800d82c: 0800e7c6 .word 0x0800e7c6
|
|
800d830: 0800b0c9 .word 0x0800b0c9
|
|
800d834: 0800d585 .word 0x0800d585
|
|
800d838: 0800e7c2 .word 0x0800e7c2
|
|
|
|
0800d83c <__sfputc_r>:
|
|
800d83c: 6893 ldr r3, [r2, #8]
|
|
800d83e: 3b01 subs r3, #1
|
|
800d840: 2b00 cmp r3, #0
|
|
800d842: b410 push {r4}
|
|
800d844: 6093 str r3, [r2, #8]
|
|
800d846: da08 bge.n 800d85a <__sfputc_r+0x1e>
|
|
800d848: 6994 ldr r4, [r2, #24]
|
|
800d84a: 42a3 cmp r3, r4
|
|
800d84c: db01 blt.n 800d852 <__sfputc_r+0x16>
|
|
800d84e: 290a cmp r1, #10
|
|
800d850: d103 bne.n 800d85a <__sfputc_r+0x1e>
|
|
800d852: f85d 4b04 ldr.w r4, [sp], #4
|
|
800d856: f7fe b8c7 b.w 800b9e8 <__swbuf_r>
|
|
800d85a: 6813 ldr r3, [r2, #0]
|
|
800d85c: 1c58 adds r0, r3, #1
|
|
800d85e: 6010 str r0, [r2, #0]
|
|
800d860: 7019 strb r1, [r3, #0]
|
|
800d862: 4608 mov r0, r1
|
|
800d864: f85d 4b04 ldr.w r4, [sp], #4
|
|
800d868: 4770 bx lr
|
|
|
|
0800d86a <__sfputs_r>:
|
|
800d86a: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800d86c: 4606 mov r6, r0
|
|
800d86e: 460f mov r7, r1
|
|
800d870: 4614 mov r4, r2
|
|
800d872: 18d5 adds r5, r2, r3
|
|
800d874: 42ac cmp r4, r5
|
|
800d876: d101 bne.n 800d87c <__sfputs_r+0x12>
|
|
800d878: 2000 movs r0, #0
|
|
800d87a: e007 b.n 800d88c <__sfputs_r+0x22>
|
|
800d87c: f814 1b01 ldrb.w r1, [r4], #1
|
|
800d880: 463a mov r2, r7
|
|
800d882: 4630 mov r0, r6
|
|
800d884: f7ff ffda bl 800d83c <__sfputc_r>
|
|
800d888: 1c43 adds r3, r0, #1
|
|
800d88a: d1f3 bne.n 800d874 <__sfputs_r+0xa>
|
|
800d88c: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
...
|
|
|
|
0800d890 <_vfiprintf_r>:
|
|
800d890: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800d894: 460d mov r5, r1
|
|
800d896: b09d sub sp, #116 ; 0x74
|
|
800d898: 4614 mov r4, r2
|
|
800d89a: 4698 mov r8, r3
|
|
800d89c: 4606 mov r6, r0
|
|
800d89e: b118 cbz r0, 800d8a8 <_vfiprintf_r+0x18>
|
|
800d8a0: 6983 ldr r3, [r0, #24]
|
|
800d8a2: b90b cbnz r3, 800d8a8 <_vfiprintf_r+0x18>
|
|
800d8a4: f7ff f912 bl 800cacc <__sinit>
|
|
800d8a8: 4b89 ldr r3, [pc, #548] ; (800dad0 <_vfiprintf_r+0x240>)
|
|
800d8aa: 429d cmp r5, r3
|
|
800d8ac: d11b bne.n 800d8e6 <_vfiprintf_r+0x56>
|
|
800d8ae: 6875 ldr r5, [r6, #4]
|
|
800d8b0: 6e6b ldr r3, [r5, #100] ; 0x64
|
|
800d8b2: 07d9 lsls r1, r3, #31
|
|
800d8b4: d405 bmi.n 800d8c2 <_vfiprintf_r+0x32>
|
|
800d8b6: 89ab ldrh r3, [r5, #12]
|
|
800d8b8: 059a lsls r2, r3, #22
|
|
800d8ba: d402 bmi.n 800d8c2 <_vfiprintf_r+0x32>
|
|
800d8bc: 6da8 ldr r0, [r5, #88] ; 0x58
|
|
800d8be: f7ff f9ba bl 800cc36 <__retarget_lock_acquire_recursive>
|
|
800d8c2: 89ab ldrh r3, [r5, #12]
|
|
800d8c4: 071b lsls r3, r3, #28
|
|
800d8c6: d501 bpl.n 800d8cc <_vfiprintf_r+0x3c>
|
|
800d8c8: 692b ldr r3, [r5, #16]
|
|
800d8ca: b9eb cbnz r3, 800d908 <_vfiprintf_r+0x78>
|
|
800d8cc: 4629 mov r1, r5
|
|
800d8ce: 4630 mov r0, r6
|
|
800d8d0: f7fe f8dc bl 800ba8c <__swsetup_r>
|
|
800d8d4: b1c0 cbz r0, 800d908 <_vfiprintf_r+0x78>
|
|
800d8d6: 6e6b ldr r3, [r5, #100] ; 0x64
|
|
800d8d8: 07dc lsls r4, r3, #31
|
|
800d8da: d50e bpl.n 800d8fa <_vfiprintf_r+0x6a>
|
|
800d8dc: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800d8e0: b01d add sp, #116 ; 0x74
|
|
800d8e2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800d8e6: 4b7b ldr r3, [pc, #492] ; (800dad4 <_vfiprintf_r+0x244>)
|
|
800d8e8: 429d cmp r5, r3
|
|
800d8ea: d101 bne.n 800d8f0 <_vfiprintf_r+0x60>
|
|
800d8ec: 68b5 ldr r5, [r6, #8]
|
|
800d8ee: e7df b.n 800d8b0 <_vfiprintf_r+0x20>
|
|
800d8f0: 4b79 ldr r3, [pc, #484] ; (800dad8 <_vfiprintf_r+0x248>)
|
|
800d8f2: 429d cmp r5, r3
|
|
800d8f4: bf08 it eq
|
|
800d8f6: 68f5 ldreq r5, [r6, #12]
|
|
800d8f8: e7da b.n 800d8b0 <_vfiprintf_r+0x20>
|
|
800d8fa: 89ab ldrh r3, [r5, #12]
|
|
800d8fc: 0598 lsls r0, r3, #22
|
|
800d8fe: d4ed bmi.n 800d8dc <_vfiprintf_r+0x4c>
|
|
800d900: 6da8 ldr r0, [r5, #88] ; 0x58
|
|
800d902: f7ff f999 bl 800cc38 <__retarget_lock_release_recursive>
|
|
800d906: e7e9 b.n 800d8dc <_vfiprintf_r+0x4c>
|
|
800d908: 2300 movs r3, #0
|
|
800d90a: 9309 str r3, [sp, #36] ; 0x24
|
|
800d90c: 2320 movs r3, #32
|
|
800d90e: f88d 3029 strb.w r3, [sp, #41] ; 0x29
|
|
800d912: f8cd 800c str.w r8, [sp, #12]
|
|
800d916: 2330 movs r3, #48 ; 0x30
|
|
800d918: f8df 81c0 ldr.w r8, [pc, #448] ; 800dadc <_vfiprintf_r+0x24c>
|
|
800d91c: f88d 302a strb.w r3, [sp, #42] ; 0x2a
|
|
800d920: f04f 0901 mov.w r9, #1
|
|
800d924: 4623 mov r3, r4
|
|
800d926: 469a mov sl, r3
|
|
800d928: f813 2b01 ldrb.w r2, [r3], #1
|
|
800d92c: b10a cbz r2, 800d932 <_vfiprintf_r+0xa2>
|
|
800d92e: 2a25 cmp r2, #37 ; 0x25
|
|
800d930: d1f9 bne.n 800d926 <_vfiprintf_r+0x96>
|
|
800d932: ebba 0b04 subs.w fp, sl, r4
|
|
800d936: d00b beq.n 800d950 <_vfiprintf_r+0xc0>
|
|
800d938: 465b mov r3, fp
|
|
800d93a: 4622 mov r2, r4
|
|
800d93c: 4629 mov r1, r5
|
|
800d93e: 4630 mov r0, r6
|
|
800d940: f7ff ff93 bl 800d86a <__sfputs_r>
|
|
800d944: 3001 adds r0, #1
|
|
800d946: f000 80aa beq.w 800da9e <_vfiprintf_r+0x20e>
|
|
800d94a: 9a09 ldr r2, [sp, #36] ; 0x24
|
|
800d94c: 445a add r2, fp
|
|
800d94e: 9209 str r2, [sp, #36] ; 0x24
|
|
800d950: f89a 3000 ldrb.w r3, [sl]
|
|
800d954: 2b00 cmp r3, #0
|
|
800d956: f000 80a2 beq.w 800da9e <_vfiprintf_r+0x20e>
|
|
800d95a: 2300 movs r3, #0
|
|
800d95c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
|
|
800d960: e9cd 2305 strd r2, r3, [sp, #20]
|
|
800d964: f10a 0a01 add.w sl, sl, #1
|
|
800d968: 9304 str r3, [sp, #16]
|
|
800d96a: 9307 str r3, [sp, #28]
|
|
800d96c: f88d 3053 strb.w r3, [sp, #83] ; 0x53
|
|
800d970: 931a str r3, [sp, #104] ; 0x68
|
|
800d972: 4654 mov r4, sl
|
|
800d974: 2205 movs r2, #5
|
|
800d976: f814 1b01 ldrb.w r1, [r4], #1
|
|
800d97a: 4858 ldr r0, [pc, #352] ; (800dadc <_vfiprintf_r+0x24c>)
|
|
800d97c: f7f2 fc30 bl 80001e0 <memchr>
|
|
800d980: 9a04 ldr r2, [sp, #16]
|
|
800d982: b9d8 cbnz r0, 800d9bc <_vfiprintf_r+0x12c>
|
|
800d984: 06d1 lsls r1, r2, #27
|
|
800d986: bf44 itt mi
|
|
800d988: 2320 movmi r3, #32
|
|
800d98a: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
800d98e: 0713 lsls r3, r2, #28
|
|
800d990: bf44 itt mi
|
|
800d992: 232b movmi r3, #43 ; 0x2b
|
|
800d994: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53
|
|
800d998: f89a 3000 ldrb.w r3, [sl]
|
|
800d99c: 2b2a cmp r3, #42 ; 0x2a
|
|
800d99e: d015 beq.n 800d9cc <_vfiprintf_r+0x13c>
|
|
800d9a0: 9a07 ldr r2, [sp, #28]
|
|
800d9a2: 4654 mov r4, sl
|
|
800d9a4: 2000 movs r0, #0
|
|
800d9a6: f04f 0c0a mov.w ip, #10
|
|
800d9aa: 4621 mov r1, r4
|
|
800d9ac: f811 3b01 ldrb.w r3, [r1], #1
|
|
800d9b0: 3b30 subs r3, #48 ; 0x30
|
|
800d9b2: 2b09 cmp r3, #9
|
|
800d9b4: d94e bls.n 800da54 <_vfiprintf_r+0x1c4>
|
|
800d9b6: b1b0 cbz r0, 800d9e6 <_vfiprintf_r+0x156>
|
|
800d9b8: 9207 str r2, [sp, #28]
|
|
800d9ba: e014 b.n 800d9e6 <_vfiprintf_r+0x156>
|
|
800d9bc: eba0 0308 sub.w r3, r0, r8
|
|
800d9c0: fa09 f303 lsl.w r3, r9, r3
|
|
800d9c4: 4313 orrs r3, r2
|
|
800d9c6: 9304 str r3, [sp, #16]
|
|
800d9c8: 46a2 mov sl, r4
|
|
800d9ca: e7d2 b.n 800d972 <_vfiprintf_r+0xe2>
|
|
800d9cc: 9b03 ldr r3, [sp, #12]
|
|
800d9ce: 1d19 adds r1, r3, #4
|
|
800d9d0: 681b ldr r3, [r3, #0]
|
|
800d9d2: 9103 str r1, [sp, #12]
|
|
800d9d4: 2b00 cmp r3, #0
|
|
800d9d6: bfbb ittet lt
|
|
800d9d8: 425b neglt r3, r3
|
|
800d9da: f042 0202 orrlt.w r2, r2, #2
|
|
800d9de: 9307 strge r3, [sp, #28]
|
|
800d9e0: 9307 strlt r3, [sp, #28]
|
|
800d9e2: bfb8 it lt
|
|
800d9e4: 9204 strlt r2, [sp, #16]
|
|
800d9e6: 7823 ldrb r3, [r4, #0]
|
|
800d9e8: 2b2e cmp r3, #46 ; 0x2e
|
|
800d9ea: d10c bne.n 800da06 <_vfiprintf_r+0x176>
|
|
800d9ec: 7863 ldrb r3, [r4, #1]
|
|
800d9ee: 2b2a cmp r3, #42 ; 0x2a
|
|
800d9f0: d135 bne.n 800da5e <_vfiprintf_r+0x1ce>
|
|
800d9f2: 9b03 ldr r3, [sp, #12]
|
|
800d9f4: 1d1a adds r2, r3, #4
|
|
800d9f6: 681b ldr r3, [r3, #0]
|
|
800d9f8: 9203 str r2, [sp, #12]
|
|
800d9fa: 2b00 cmp r3, #0
|
|
800d9fc: bfb8 it lt
|
|
800d9fe: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff
|
|
800da02: 3402 adds r4, #2
|
|
800da04: 9305 str r3, [sp, #20]
|
|
800da06: f8df a0e4 ldr.w sl, [pc, #228] ; 800daec <_vfiprintf_r+0x25c>
|
|
800da0a: 7821 ldrb r1, [r4, #0]
|
|
800da0c: 2203 movs r2, #3
|
|
800da0e: 4650 mov r0, sl
|
|
800da10: f7f2 fbe6 bl 80001e0 <memchr>
|
|
800da14: b140 cbz r0, 800da28 <_vfiprintf_r+0x198>
|
|
800da16: 2340 movs r3, #64 ; 0x40
|
|
800da18: eba0 000a sub.w r0, r0, sl
|
|
800da1c: fa03 f000 lsl.w r0, r3, r0
|
|
800da20: 9b04 ldr r3, [sp, #16]
|
|
800da22: 4303 orrs r3, r0
|
|
800da24: 3401 adds r4, #1
|
|
800da26: 9304 str r3, [sp, #16]
|
|
800da28: f814 1b01 ldrb.w r1, [r4], #1
|
|
800da2c: 482c ldr r0, [pc, #176] ; (800dae0 <_vfiprintf_r+0x250>)
|
|
800da2e: f88d 1028 strb.w r1, [sp, #40] ; 0x28
|
|
800da32: 2206 movs r2, #6
|
|
800da34: f7f2 fbd4 bl 80001e0 <memchr>
|
|
800da38: 2800 cmp r0, #0
|
|
800da3a: d03f beq.n 800dabc <_vfiprintf_r+0x22c>
|
|
800da3c: 4b29 ldr r3, [pc, #164] ; (800dae4 <_vfiprintf_r+0x254>)
|
|
800da3e: bb1b cbnz r3, 800da88 <_vfiprintf_r+0x1f8>
|
|
800da40: 9b03 ldr r3, [sp, #12]
|
|
800da42: 3307 adds r3, #7
|
|
800da44: f023 0307 bic.w r3, r3, #7
|
|
800da48: 3308 adds r3, #8
|
|
800da4a: 9303 str r3, [sp, #12]
|
|
800da4c: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
800da4e: 443b add r3, r7
|
|
800da50: 9309 str r3, [sp, #36] ; 0x24
|
|
800da52: e767 b.n 800d924 <_vfiprintf_r+0x94>
|
|
800da54: fb0c 3202 mla r2, ip, r2, r3
|
|
800da58: 460c mov r4, r1
|
|
800da5a: 2001 movs r0, #1
|
|
800da5c: e7a5 b.n 800d9aa <_vfiprintf_r+0x11a>
|
|
800da5e: 2300 movs r3, #0
|
|
800da60: 3401 adds r4, #1
|
|
800da62: 9305 str r3, [sp, #20]
|
|
800da64: 4619 mov r1, r3
|
|
800da66: f04f 0c0a mov.w ip, #10
|
|
800da6a: 4620 mov r0, r4
|
|
800da6c: f810 2b01 ldrb.w r2, [r0], #1
|
|
800da70: 3a30 subs r2, #48 ; 0x30
|
|
800da72: 2a09 cmp r2, #9
|
|
800da74: d903 bls.n 800da7e <_vfiprintf_r+0x1ee>
|
|
800da76: 2b00 cmp r3, #0
|
|
800da78: d0c5 beq.n 800da06 <_vfiprintf_r+0x176>
|
|
800da7a: 9105 str r1, [sp, #20]
|
|
800da7c: e7c3 b.n 800da06 <_vfiprintf_r+0x176>
|
|
800da7e: fb0c 2101 mla r1, ip, r1, r2
|
|
800da82: 4604 mov r4, r0
|
|
800da84: 2301 movs r3, #1
|
|
800da86: e7f0 b.n 800da6a <_vfiprintf_r+0x1da>
|
|
800da88: ab03 add r3, sp, #12
|
|
800da8a: 9300 str r3, [sp, #0]
|
|
800da8c: 462a mov r2, r5
|
|
800da8e: 4b16 ldr r3, [pc, #88] ; (800dae8 <_vfiprintf_r+0x258>)
|
|
800da90: a904 add r1, sp, #16
|
|
800da92: 4630 mov r0, r6
|
|
800da94: f7fd fb18 bl 800b0c8 <_printf_float>
|
|
800da98: 4607 mov r7, r0
|
|
800da9a: 1c78 adds r0, r7, #1
|
|
800da9c: d1d6 bne.n 800da4c <_vfiprintf_r+0x1bc>
|
|
800da9e: 6e6b ldr r3, [r5, #100] ; 0x64
|
|
800daa0: 07d9 lsls r1, r3, #31
|
|
800daa2: d405 bmi.n 800dab0 <_vfiprintf_r+0x220>
|
|
800daa4: 89ab ldrh r3, [r5, #12]
|
|
800daa6: 059a lsls r2, r3, #22
|
|
800daa8: d402 bmi.n 800dab0 <_vfiprintf_r+0x220>
|
|
800daaa: 6da8 ldr r0, [r5, #88] ; 0x58
|
|
800daac: f7ff f8c4 bl 800cc38 <__retarget_lock_release_recursive>
|
|
800dab0: 89ab ldrh r3, [r5, #12]
|
|
800dab2: 065b lsls r3, r3, #25
|
|
800dab4: f53f af12 bmi.w 800d8dc <_vfiprintf_r+0x4c>
|
|
800dab8: 9809 ldr r0, [sp, #36] ; 0x24
|
|
800daba: e711 b.n 800d8e0 <_vfiprintf_r+0x50>
|
|
800dabc: ab03 add r3, sp, #12
|
|
800dabe: 9300 str r3, [sp, #0]
|
|
800dac0: 462a mov r2, r5
|
|
800dac2: 4b09 ldr r3, [pc, #36] ; (800dae8 <_vfiprintf_r+0x258>)
|
|
800dac4: a904 add r1, sp, #16
|
|
800dac6: 4630 mov r0, r6
|
|
800dac8: f7fd fda2 bl 800b610 <_printf_i>
|
|
800dacc: e7e4 b.n 800da98 <_vfiprintf_r+0x208>
|
|
800dace: bf00 nop
|
|
800dad0: 0800e620 .word 0x0800e620
|
|
800dad4: 0800e640 .word 0x0800e640
|
|
800dad8: 0800e600 .word 0x0800e600
|
|
800dadc: 0800e7bc .word 0x0800e7bc
|
|
800dae0: 0800e7c6 .word 0x0800e7c6
|
|
800dae4: 0800b0c9 .word 0x0800b0c9
|
|
800dae8: 0800d86b .word 0x0800d86b
|
|
800daec: 0800e7c2 .word 0x0800e7c2
|
|
|
|
0800daf0 <_sbrk_r>:
|
|
800daf0: b538 push {r3, r4, r5, lr}
|
|
800daf2: 4d06 ldr r5, [pc, #24] ; (800db0c <_sbrk_r+0x1c>)
|
|
800daf4: 2300 movs r3, #0
|
|
800daf6: 4604 mov r4, r0
|
|
800daf8: 4608 mov r0, r1
|
|
800dafa: 602b str r3, [r5, #0]
|
|
800dafc: f7f5 fa5e bl 8002fbc <_sbrk>
|
|
800db00: 1c43 adds r3, r0, #1
|
|
800db02: d102 bne.n 800db0a <_sbrk_r+0x1a>
|
|
800db04: 682b ldr r3, [r5, #0]
|
|
800db06: b103 cbz r3, 800db0a <_sbrk_r+0x1a>
|
|
800db08: 6023 str r3, [r4, #0]
|
|
800db0a: bd38 pop {r3, r4, r5, pc}
|
|
800db0c: 20000a88 .word 0x20000a88
|
|
|
|
0800db10 <__sread>:
|
|
800db10: b510 push {r4, lr}
|
|
800db12: 460c mov r4, r1
|
|
800db14: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800db18: f000 f8fa bl 800dd10 <_read_r>
|
|
800db1c: 2800 cmp r0, #0
|
|
800db1e: bfab itete ge
|
|
800db20: 6d63 ldrge r3, [r4, #84] ; 0x54
|
|
800db22: 89a3 ldrhlt r3, [r4, #12]
|
|
800db24: 181b addge r3, r3, r0
|
|
800db26: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
|
|
800db2a: bfac ite ge
|
|
800db2c: 6563 strge r3, [r4, #84] ; 0x54
|
|
800db2e: 81a3 strhlt r3, [r4, #12]
|
|
800db30: bd10 pop {r4, pc}
|
|
|
|
0800db32 <__swrite>:
|
|
800db32: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
800db36: 461f mov r7, r3
|
|
800db38: 898b ldrh r3, [r1, #12]
|
|
800db3a: 05db lsls r3, r3, #23
|
|
800db3c: 4605 mov r5, r0
|
|
800db3e: 460c mov r4, r1
|
|
800db40: 4616 mov r6, r2
|
|
800db42: d505 bpl.n 800db50 <__swrite+0x1e>
|
|
800db44: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800db48: 2302 movs r3, #2
|
|
800db4a: 2200 movs r2, #0
|
|
800db4c: f000 f870 bl 800dc30 <_lseek_r>
|
|
800db50: 89a3 ldrh r3, [r4, #12]
|
|
800db52: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
800db56: f423 5380 bic.w r3, r3, #4096 ; 0x1000
|
|
800db5a: 81a3 strh r3, [r4, #12]
|
|
800db5c: 4632 mov r2, r6
|
|
800db5e: 463b mov r3, r7
|
|
800db60: 4628 mov r0, r5
|
|
800db62: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
800db66: f000 b817 b.w 800db98 <_write_r>
|
|
|
|
0800db6a <__sseek>:
|
|
800db6a: b510 push {r4, lr}
|
|
800db6c: 460c mov r4, r1
|
|
800db6e: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800db72: f000 f85d bl 800dc30 <_lseek_r>
|
|
800db76: 1c43 adds r3, r0, #1
|
|
800db78: 89a3 ldrh r3, [r4, #12]
|
|
800db7a: bf15 itete ne
|
|
800db7c: 6560 strne r0, [r4, #84] ; 0x54
|
|
800db7e: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
|
|
800db82: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
|
|
800db86: 81a3 strheq r3, [r4, #12]
|
|
800db88: bf18 it ne
|
|
800db8a: 81a3 strhne r3, [r4, #12]
|
|
800db8c: bd10 pop {r4, pc}
|
|
|
|
0800db8e <__sclose>:
|
|
800db8e: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800db92: f000 b81b b.w 800dbcc <_close_r>
|
|
...
|
|
|
|
0800db98 <_write_r>:
|
|
800db98: b538 push {r3, r4, r5, lr}
|
|
800db9a: 4d07 ldr r5, [pc, #28] ; (800dbb8 <_write_r+0x20>)
|
|
800db9c: 4604 mov r4, r0
|
|
800db9e: 4608 mov r0, r1
|
|
800dba0: 4611 mov r1, r2
|
|
800dba2: 2200 movs r2, #0
|
|
800dba4: 602a str r2, [r5, #0]
|
|
800dba6: 461a mov r2, r3
|
|
800dba8: f7f4 fcd6 bl 8002558 <_write>
|
|
800dbac: 1c43 adds r3, r0, #1
|
|
800dbae: d102 bne.n 800dbb6 <_write_r+0x1e>
|
|
800dbb0: 682b ldr r3, [r5, #0]
|
|
800dbb2: b103 cbz r3, 800dbb6 <_write_r+0x1e>
|
|
800dbb4: 6023 str r3, [r4, #0]
|
|
800dbb6: bd38 pop {r3, r4, r5, pc}
|
|
800dbb8: 20000a88 .word 0x20000a88
|
|
|
|
0800dbbc <abort>:
|
|
800dbbc: b508 push {r3, lr}
|
|
800dbbe: 2006 movs r0, #6
|
|
800dbc0: f000 f8e0 bl 800dd84 <raise>
|
|
800dbc4: 2001 movs r0, #1
|
|
800dbc6: f7f5 f99e bl 8002f06 <_exit>
|
|
...
|
|
|
|
0800dbcc <_close_r>:
|
|
800dbcc: b538 push {r3, r4, r5, lr}
|
|
800dbce: 4d06 ldr r5, [pc, #24] ; (800dbe8 <_close_r+0x1c>)
|
|
800dbd0: 2300 movs r3, #0
|
|
800dbd2: 4604 mov r4, r0
|
|
800dbd4: 4608 mov r0, r1
|
|
800dbd6: 602b str r3, [r5, #0]
|
|
800dbd8: f7f5 f9bc bl 8002f54 <_close>
|
|
800dbdc: 1c43 adds r3, r0, #1
|
|
800dbde: d102 bne.n 800dbe6 <_close_r+0x1a>
|
|
800dbe0: 682b ldr r3, [r5, #0]
|
|
800dbe2: b103 cbz r3, 800dbe6 <_close_r+0x1a>
|
|
800dbe4: 6023 str r3, [r4, #0]
|
|
800dbe6: bd38 pop {r3, r4, r5, pc}
|
|
800dbe8: 20000a88 .word 0x20000a88
|
|
|
|
0800dbec <_fstat_r>:
|
|
800dbec: b538 push {r3, r4, r5, lr}
|
|
800dbee: 4d07 ldr r5, [pc, #28] ; (800dc0c <_fstat_r+0x20>)
|
|
800dbf0: 2300 movs r3, #0
|
|
800dbf2: 4604 mov r4, r0
|
|
800dbf4: 4608 mov r0, r1
|
|
800dbf6: 4611 mov r1, r2
|
|
800dbf8: 602b str r3, [r5, #0]
|
|
800dbfa: f7f5 f9b7 bl 8002f6c <_fstat>
|
|
800dbfe: 1c43 adds r3, r0, #1
|
|
800dc00: d102 bne.n 800dc08 <_fstat_r+0x1c>
|
|
800dc02: 682b ldr r3, [r5, #0]
|
|
800dc04: b103 cbz r3, 800dc08 <_fstat_r+0x1c>
|
|
800dc06: 6023 str r3, [r4, #0]
|
|
800dc08: bd38 pop {r3, r4, r5, pc}
|
|
800dc0a: bf00 nop
|
|
800dc0c: 20000a88 .word 0x20000a88
|
|
|
|
0800dc10 <_isatty_r>:
|
|
800dc10: b538 push {r3, r4, r5, lr}
|
|
800dc12: 4d06 ldr r5, [pc, #24] ; (800dc2c <_isatty_r+0x1c>)
|
|
800dc14: 2300 movs r3, #0
|
|
800dc16: 4604 mov r4, r0
|
|
800dc18: 4608 mov r0, r1
|
|
800dc1a: 602b str r3, [r5, #0]
|
|
800dc1c: f7f5 f9b6 bl 8002f8c <_isatty>
|
|
800dc20: 1c43 adds r3, r0, #1
|
|
800dc22: d102 bne.n 800dc2a <_isatty_r+0x1a>
|
|
800dc24: 682b ldr r3, [r5, #0]
|
|
800dc26: b103 cbz r3, 800dc2a <_isatty_r+0x1a>
|
|
800dc28: 6023 str r3, [r4, #0]
|
|
800dc2a: bd38 pop {r3, r4, r5, pc}
|
|
800dc2c: 20000a88 .word 0x20000a88
|
|
|
|
0800dc30 <_lseek_r>:
|
|
800dc30: b538 push {r3, r4, r5, lr}
|
|
800dc32: 4d07 ldr r5, [pc, #28] ; (800dc50 <_lseek_r+0x20>)
|
|
800dc34: 4604 mov r4, r0
|
|
800dc36: 4608 mov r0, r1
|
|
800dc38: 4611 mov r1, r2
|
|
800dc3a: 2200 movs r2, #0
|
|
800dc3c: 602a str r2, [r5, #0]
|
|
800dc3e: 461a mov r2, r3
|
|
800dc40: f7f5 f9af bl 8002fa2 <_lseek>
|
|
800dc44: 1c43 adds r3, r0, #1
|
|
800dc46: d102 bne.n 800dc4e <_lseek_r+0x1e>
|
|
800dc48: 682b ldr r3, [r5, #0]
|
|
800dc4a: b103 cbz r3, 800dc4e <_lseek_r+0x1e>
|
|
800dc4c: 6023 str r3, [r4, #0]
|
|
800dc4e: bd38 pop {r3, r4, r5, pc}
|
|
800dc50: 20000a88 .word 0x20000a88
|
|
|
|
0800dc54 <__ascii_mbtowc>:
|
|
800dc54: b082 sub sp, #8
|
|
800dc56: b901 cbnz r1, 800dc5a <__ascii_mbtowc+0x6>
|
|
800dc58: a901 add r1, sp, #4
|
|
800dc5a: b142 cbz r2, 800dc6e <__ascii_mbtowc+0x1a>
|
|
800dc5c: b14b cbz r3, 800dc72 <__ascii_mbtowc+0x1e>
|
|
800dc5e: 7813 ldrb r3, [r2, #0]
|
|
800dc60: 600b str r3, [r1, #0]
|
|
800dc62: 7812 ldrb r2, [r2, #0]
|
|
800dc64: 1e10 subs r0, r2, #0
|
|
800dc66: bf18 it ne
|
|
800dc68: 2001 movne r0, #1
|
|
800dc6a: b002 add sp, #8
|
|
800dc6c: 4770 bx lr
|
|
800dc6e: 4610 mov r0, r2
|
|
800dc70: e7fb b.n 800dc6a <__ascii_mbtowc+0x16>
|
|
800dc72: f06f 0001 mvn.w r0, #1
|
|
800dc76: e7f8 b.n 800dc6a <__ascii_mbtowc+0x16>
|
|
|
|
0800dc78 <memmove>:
|
|
800dc78: 4288 cmp r0, r1
|
|
800dc7a: b510 push {r4, lr}
|
|
800dc7c: eb01 0402 add.w r4, r1, r2
|
|
800dc80: d902 bls.n 800dc88 <memmove+0x10>
|
|
800dc82: 4284 cmp r4, r0
|
|
800dc84: 4623 mov r3, r4
|
|
800dc86: d807 bhi.n 800dc98 <memmove+0x20>
|
|
800dc88: 1e43 subs r3, r0, #1
|
|
800dc8a: 42a1 cmp r1, r4
|
|
800dc8c: d008 beq.n 800dca0 <memmove+0x28>
|
|
800dc8e: f811 2b01 ldrb.w r2, [r1], #1
|
|
800dc92: f803 2f01 strb.w r2, [r3, #1]!
|
|
800dc96: e7f8 b.n 800dc8a <memmove+0x12>
|
|
800dc98: 4402 add r2, r0
|
|
800dc9a: 4601 mov r1, r0
|
|
800dc9c: 428a cmp r2, r1
|
|
800dc9e: d100 bne.n 800dca2 <memmove+0x2a>
|
|
800dca0: bd10 pop {r4, pc}
|
|
800dca2: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
800dca6: f802 4d01 strb.w r4, [r2, #-1]!
|
|
800dcaa: e7f7 b.n 800dc9c <memmove+0x24>
|
|
|
|
0800dcac <__malloc_lock>:
|
|
800dcac: 4801 ldr r0, [pc, #4] ; (800dcb4 <__malloc_lock+0x8>)
|
|
800dcae: f7fe bfc2 b.w 800cc36 <__retarget_lock_acquire_recursive>
|
|
800dcb2: bf00 nop
|
|
800dcb4: 20000a80 .word 0x20000a80
|
|
|
|
0800dcb8 <__malloc_unlock>:
|
|
800dcb8: 4801 ldr r0, [pc, #4] ; (800dcc0 <__malloc_unlock+0x8>)
|
|
800dcba: f7fe bfbd b.w 800cc38 <__retarget_lock_release_recursive>
|
|
800dcbe: bf00 nop
|
|
800dcc0: 20000a80 .word 0x20000a80
|
|
|
|
0800dcc4 <_realloc_r>:
|
|
800dcc4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800dcc6: 4607 mov r7, r0
|
|
800dcc8: 4614 mov r4, r2
|
|
800dcca: 460e mov r6, r1
|
|
800dccc: b921 cbnz r1, 800dcd8 <_realloc_r+0x14>
|
|
800dcce: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
|
|
800dcd2: 4611 mov r1, r2
|
|
800dcd4: f7ff bbfc b.w 800d4d0 <_malloc_r>
|
|
800dcd8: b922 cbnz r2, 800dce4 <_realloc_r+0x20>
|
|
800dcda: f7ff fba9 bl 800d430 <_free_r>
|
|
800dcde: 4625 mov r5, r4
|
|
800dce0: 4628 mov r0, r5
|
|
800dce2: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
800dce4: f000 f877 bl 800ddd6 <_malloc_usable_size_r>
|
|
800dce8: 42a0 cmp r0, r4
|
|
800dcea: d20f bcs.n 800dd0c <_realloc_r+0x48>
|
|
800dcec: 4621 mov r1, r4
|
|
800dcee: 4638 mov r0, r7
|
|
800dcf0: f7ff fbee bl 800d4d0 <_malloc_r>
|
|
800dcf4: 4605 mov r5, r0
|
|
800dcf6: 2800 cmp r0, #0
|
|
800dcf8: d0f2 beq.n 800dce0 <_realloc_r+0x1c>
|
|
800dcfa: 4631 mov r1, r6
|
|
800dcfc: 4622 mov r2, r4
|
|
800dcfe: f7fd f92d bl 800af5c <memcpy>
|
|
800dd02: 4631 mov r1, r6
|
|
800dd04: 4638 mov r0, r7
|
|
800dd06: f7ff fb93 bl 800d430 <_free_r>
|
|
800dd0a: e7e9 b.n 800dce0 <_realloc_r+0x1c>
|
|
800dd0c: 4635 mov r5, r6
|
|
800dd0e: e7e7 b.n 800dce0 <_realloc_r+0x1c>
|
|
|
|
0800dd10 <_read_r>:
|
|
800dd10: b538 push {r3, r4, r5, lr}
|
|
800dd12: 4d07 ldr r5, [pc, #28] ; (800dd30 <_read_r+0x20>)
|
|
800dd14: 4604 mov r4, r0
|
|
800dd16: 4608 mov r0, r1
|
|
800dd18: 4611 mov r1, r2
|
|
800dd1a: 2200 movs r2, #0
|
|
800dd1c: 602a str r2, [r5, #0]
|
|
800dd1e: 461a mov r2, r3
|
|
800dd20: f7f5 f8fb bl 8002f1a <_read>
|
|
800dd24: 1c43 adds r3, r0, #1
|
|
800dd26: d102 bne.n 800dd2e <_read_r+0x1e>
|
|
800dd28: 682b ldr r3, [r5, #0]
|
|
800dd2a: b103 cbz r3, 800dd2e <_read_r+0x1e>
|
|
800dd2c: 6023 str r3, [r4, #0]
|
|
800dd2e: bd38 pop {r3, r4, r5, pc}
|
|
800dd30: 20000a88 .word 0x20000a88
|
|
|
|
0800dd34 <_raise_r>:
|
|
800dd34: 291f cmp r1, #31
|
|
800dd36: b538 push {r3, r4, r5, lr}
|
|
800dd38: 4604 mov r4, r0
|
|
800dd3a: 460d mov r5, r1
|
|
800dd3c: d904 bls.n 800dd48 <_raise_r+0x14>
|
|
800dd3e: 2316 movs r3, #22
|
|
800dd40: 6003 str r3, [r0, #0]
|
|
800dd42: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
|
|
800dd46: bd38 pop {r3, r4, r5, pc}
|
|
800dd48: 6c42 ldr r2, [r0, #68] ; 0x44
|
|
800dd4a: b112 cbz r2, 800dd52 <_raise_r+0x1e>
|
|
800dd4c: f852 3021 ldr.w r3, [r2, r1, lsl #2]
|
|
800dd50: b94b cbnz r3, 800dd66 <_raise_r+0x32>
|
|
800dd52: 4620 mov r0, r4
|
|
800dd54: f000 f830 bl 800ddb8 <_getpid_r>
|
|
800dd58: 462a mov r2, r5
|
|
800dd5a: 4601 mov r1, r0
|
|
800dd5c: 4620 mov r0, r4
|
|
800dd5e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
800dd62: f000 b817 b.w 800dd94 <_kill_r>
|
|
800dd66: 2b01 cmp r3, #1
|
|
800dd68: d00a beq.n 800dd80 <_raise_r+0x4c>
|
|
800dd6a: 1c59 adds r1, r3, #1
|
|
800dd6c: d103 bne.n 800dd76 <_raise_r+0x42>
|
|
800dd6e: 2316 movs r3, #22
|
|
800dd70: 6003 str r3, [r0, #0]
|
|
800dd72: 2001 movs r0, #1
|
|
800dd74: e7e7 b.n 800dd46 <_raise_r+0x12>
|
|
800dd76: 2400 movs r4, #0
|
|
800dd78: f842 4025 str.w r4, [r2, r5, lsl #2]
|
|
800dd7c: 4628 mov r0, r5
|
|
800dd7e: 4798 blx r3
|
|
800dd80: 2000 movs r0, #0
|
|
800dd82: e7e0 b.n 800dd46 <_raise_r+0x12>
|
|
|
|
0800dd84 <raise>:
|
|
800dd84: 4b02 ldr r3, [pc, #8] ; (800dd90 <raise+0xc>)
|
|
800dd86: 4601 mov r1, r0
|
|
800dd88: 6818 ldr r0, [r3, #0]
|
|
800dd8a: f7ff bfd3 b.w 800dd34 <_raise_r>
|
|
800dd8e: bf00 nop
|
|
800dd90: 20000278 .word 0x20000278
|
|
|
|
0800dd94 <_kill_r>:
|
|
800dd94: b538 push {r3, r4, r5, lr}
|
|
800dd96: 4d07 ldr r5, [pc, #28] ; (800ddb4 <_kill_r+0x20>)
|
|
800dd98: 2300 movs r3, #0
|
|
800dd9a: 4604 mov r4, r0
|
|
800dd9c: 4608 mov r0, r1
|
|
800dd9e: 4611 mov r1, r2
|
|
800dda0: 602b str r3, [r5, #0]
|
|
800dda2: f7f5 f8a0 bl 8002ee6 <_kill>
|
|
800dda6: 1c43 adds r3, r0, #1
|
|
800dda8: d102 bne.n 800ddb0 <_kill_r+0x1c>
|
|
800ddaa: 682b ldr r3, [r5, #0]
|
|
800ddac: b103 cbz r3, 800ddb0 <_kill_r+0x1c>
|
|
800ddae: 6023 str r3, [r4, #0]
|
|
800ddb0: bd38 pop {r3, r4, r5, pc}
|
|
800ddb2: bf00 nop
|
|
800ddb4: 20000a88 .word 0x20000a88
|
|
|
|
0800ddb8 <_getpid_r>:
|
|
800ddb8: f7f5 b88d b.w 8002ed6 <_getpid>
|
|
|
|
0800ddbc <__ascii_wctomb>:
|
|
800ddbc: b149 cbz r1, 800ddd2 <__ascii_wctomb+0x16>
|
|
800ddbe: 2aff cmp r2, #255 ; 0xff
|
|
800ddc0: bf85 ittet hi
|
|
800ddc2: 238a movhi r3, #138 ; 0x8a
|
|
800ddc4: 6003 strhi r3, [r0, #0]
|
|
800ddc6: 700a strbls r2, [r1, #0]
|
|
800ddc8: f04f 30ff movhi.w r0, #4294967295 ; 0xffffffff
|
|
800ddcc: bf98 it ls
|
|
800ddce: 2001 movls r0, #1
|
|
800ddd0: 4770 bx lr
|
|
800ddd2: 4608 mov r0, r1
|
|
800ddd4: 4770 bx lr
|
|
|
|
0800ddd6 <_malloc_usable_size_r>:
|
|
800ddd6: f851 3c04 ldr.w r3, [r1, #-4]
|
|
800ddda: 1f18 subs r0, r3, #4
|
|
800dddc: 2b00 cmp r3, #0
|
|
800ddde: bfbc itt lt
|
|
800dde0: 580b ldrlt r3, [r1, r0]
|
|
800dde2: 18c0 addlt r0, r0, r3
|
|
800dde4: 4770 bx lr
|
|
...
|
|
|
|
0800dde8 <log>:
|
|
800dde8: b538 push {r3, r4, r5, lr}
|
|
800ddea: ed2d 8b02 vpush {d8}
|
|
800ddee: ec55 4b10 vmov r4, r5, d0
|
|
800ddf2: f000 f841 bl 800de78 <__ieee754_log>
|
|
800ddf6: 4b1e ldr r3, [pc, #120] ; (800de70 <log+0x88>)
|
|
800ddf8: eeb0 8a40 vmov.f32 s16, s0
|
|
800ddfc: eef0 8a60 vmov.f32 s17, s1
|
|
800de00: f993 3000 ldrsb.w r3, [r3]
|
|
800de04: 3301 adds r3, #1
|
|
800de06: d01a beq.n 800de3e <log+0x56>
|
|
800de08: 4622 mov r2, r4
|
|
800de0a: 462b mov r3, r5
|
|
800de0c: 4620 mov r0, r4
|
|
800de0e: 4629 mov r1, r5
|
|
800de10: f7f2 fe8c bl 8000b2c <__aeabi_dcmpun>
|
|
800de14: b998 cbnz r0, 800de3e <log+0x56>
|
|
800de16: 2200 movs r2, #0
|
|
800de18: 2300 movs r3, #0
|
|
800de1a: 4620 mov r0, r4
|
|
800de1c: 4629 mov r1, r5
|
|
800de1e: f7f2 fe7b bl 8000b18 <__aeabi_dcmpgt>
|
|
800de22: b960 cbnz r0, 800de3e <log+0x56>
|
|
800de24: 2200 movs r2, #0
|
|
800de26: 2300 movs r3, #0
|
|
800de28: 4620 mov r0, r4
|
|
800de2a: 4629 mov r1, r5
|
|
800de2c: f7f2 fe4c bl 8000ac8 <__aeabi_dcmpeq>
|
|
800de30: b160 cbz r0, 800de4c <log+0x64>
|
|
800de32: f7fd f869 bl 800af08 <__errno>
|
|
800de36: ed9f 8b0c vldr d8, [pc, #48] ; 800de68 <log+0x80>
|
|
800de3a: 2322 movs r3, #34 ; 0x22
|
|
800de3c: 6003 str r3, [r0, #0]
|
|
800de3e: eeb0 0a48 vmov.f32 s0, s16
|
|
800de42: eef0 0a68 vmov.f32 s1, s17
|
|
800de46: ecbd 8b02 vpop {d8}
|
|
800de4a: bd38 pop {r3, r4, r5, pc}
|
|
800de4c: f7fd f85c bl 800af08 <__errno>
|
|
800de50: ecbd 8b02 vpop {d8}
|
|
800de54: 2321 movs r3, #33 ; 0x21
|
|
800de56: 6003 str r3, [r0, #0]
|
|
800de58: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
800de5c: 4805 ldr r0, [pc, #20] ; (800de74 <log+0x8c>)
|
|
800de5e: f000 b9c7 b.w 800e1f0 <nan>
|
|
800de62: bf00 nop
|
|
800de64: f3af 8000 nop.w
|
|
800de68: 00000000 .word 0x00000000
|
|
800de6c: fff00000 .word 0xfff00000
|
|
800de70: 20000448 .word 0x20000448
|
|
800de74: 0800e467 .word 0x0800e467
|
|
|
|
0800de78 <__ieee754_log>:
|
|
800de78: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800de7c: ec51 0b10 vmov r0, r1, d0
|
|
800de80: ed2d 8b04 vpush {d8-d9}
|
|
800de84: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000
|
|
800de88: b083 sub sp, #12
|
|
800de8a: 460d mov r5, r1
|
|
800de8c: da29 bge.n 800dee2 <__ieee754_log+0x6a>
|
|
800de8e: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000
|
|
800de92: 4303 orrs r3, r0
|
|
800de94: ee10 2a10 vmov r2, s0
|
|
800de98: d10c bne.n 800deb4 <__ieee754_log+0x3c>
|
|
800de9a: 49cf ldr r1, [pc, #828] ; (800e1d8 <__ieee754_log+0x360>)
|
|
800de9c: 2200 movs r2, #0
|
|
800de9e: 2300 movs r3, #0
|
|
800dea0: 2000 movs r0, #0
|
|
800dea2: f7f2 fcd3 bl 800084c <__aeabi_ddiv>
|
|
800dea6: ec41 0b10 vmov d0, r0, r1
|
|
800deaa: b003 add sp, #12
|
|
800deac: ecbd 8b04 vpop {d8-d9}
|
|
800deb0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800deb4: 2900 cmp r1, #0
|
|
800deb6: da05 bge.n 800dec4 <__ieee754_log+0x4c>
|
|
800deb8: 460b mov r3, r1
|
|
800deba: f7f2 f9e5 bl 8000288 <__aeabi_dsub>
|
|
800debe: 2200 movs r2, #0
|
|
800dec0: 2300 movs r3, #0
|
|
800dec2: e7ee b.n 800dea2 <__ieee754_log+0x2a>
|
|
800dec4: 4bc5 ldr r3, [pc, #788] ; (800e1dc <__ieee754_log+0x364>)
|
|
800dec6: 2200 movs r2, #0
|
|
800dec8: f7f2 fb96 bl 80005f8 <__aeabi_dmul>
|
|
800decc: f06f 0335 mvn.w r3, #53 ; 0x35
|
|
800ded0: 460d mov r5, r1
|
|
800ded2: 4ac3 ldr r2, [pc, #780] ; (800e1e0 <__ieee754_log+0x368>)
|
|
800ded4: 4295 cmp r5, r2
|
|
800ded6: dd06 ble.n 800dee6 <__ieee754_log+0x6e>
|
|
800ded8: 4602 mov r2, r0
|
|
800deda: 460b mov r3, r1
|
|
800dedc: f7f2 f9d6 bl 800028c <__adddf3>
|
|
800dee0: e7e1 b.n 800dea6 <__ieee754_log+0x2e>
|
|
800dee2: 2300 movs r3, #0
|
|
800dee4: e7f5 b.n 800ded2 <__ieee754_log+0x5a>
|
|
800dee6: 152c asrs r4, r5, #20
|
|
800dee8: f2a4 34ff subw r4, r4, #1023 ; 0x3ff
|
|
800deec: f3c5 0513 ubfx r5, r5, #0, #20
|
|
800def0: 441c add r4, r3
|
|
800def2: f505 2315 add.w r3, r5, #610304 ; 0x95000
|
|
800def6: f603 7364 addw r3, r3, #3940 ; 0xf64
|
|
800defa: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
800defe: f083 527f eor.w r2, r3, #1069547520 ; 0x3fc00000
|
|
800df02: f482 1240 eor.w r2, r2, #3145728 ; 0x300000
|
|
800df06: ea42 0105 orr.w r1, r2, r5
|
|
800df0a: eb04 5413 add.w r4, r4, r3, lsr #20
|
|
800df0e: 2200 movs r2, #0
|
|
800df10: 4bb4 ldr r3, [pc, #720] ; (800e1e4 <__ieee754_log+0x36c>)
|
|
800df12: f7f2 f9b9 bl 8000288 <__aeabi_dsub>
|
|
800df16: 1cab adds r3, r5, #2
|
|
800df18: f3c3 0313 ubfx r3, r3, #0, #20
|
|
800df1c: 2b02 cmp r3, #2
|
|
800df1e: 4682 mov sl, r0
|
|
800df20: 468b mov fp, r1
|
|
800df22: f04f 0200 mov.w r2, #0
|
|
800df26: dc53 bgt.n 800dfd0 <__ieee754_log+0x158>
|
|
800df28: 2300 movs r3, #0
|
|
800df2a: f7f2 fdcd bl 8000ac8 <__aeabi_dcmpeq>
|
|
800df2e: b1d0 cbz r0, 800df66 <__ieee754_log+0xee>
|
|
800df30: 2c00 cmp r4, #0
|
|
800df32: f000 8122 beq.w 800e17a <__ieee754_log+0x302>
|
|
800df36: 4620 mov r0, r4
|
|
800df38: f7f2 faf4 bl 8000524 <__aeabi_i2d>
|
|
800df3c: a390 add r3, pc, #576 ; (adr r3, 800e180 <__ieee754_log+0x308>)
|
|
800df3e: e9d3 2300 ldrd r2, r3, [r3]
|
|
800df42: 4606 mov r6, r0
|
|
800df44: 460f mov r7, r1
|
|
800df46: f7f2 fb57 bl 80005f8 <__aeabi_dmul>
|
|
800df4a: a38f add r3, pc, #572 ; (adr r3, 800e188 <__ieee754_log+0x310>)
|
|
800df4c: e9d3 2300 ldrd r2, r3, [r3]
|
|
800df50: 4604 mov r4, r0
|
|
800df52: 460d mov r5, r1
|
|
800df54: 4630 mov r0, r6
|
|
800df56: 4639 mov r1, r7
|
|
800df58: f7f2 fb4e bl 80005f8 <__aeabi_dmul>
|
|
800df5c: 4602 mov r2, r0
|
|
800df5e: 460b mov r3, r1
|
|
800df60: 4620 mov r0, r4
|
|
800df62: 4629 mov r1, r5
|
|
800df64: e7ba b.n 800dedc <__ieee754_log+0x64>
|
|
800df66: a38a add r3, pc, #552 ; (adr r3, 800e190 <__ieee754_log+0x318>)
|
|
800df68: e9d3 2300 ldrd r2, r3, [r3]
|
|
800df6c: 4650 mov r0, sl
|
|
800df6e: 4659 mov r1, fp
|
|
800df70: f7f2 fb42 bl 80005f8 <__aeabi_dmul>
|
|
800df74: 4602 mov r2, r0
|
|
800df76: 460b mov r3, r1
|
|
800df78: 2000 movs r0, #0
|
|
800df7a: 499b ldr r1, [pc, #620] ; (800e1e8 <__ieee754_log+0x370>)
|
|
800df7c: f7f2 f984 bl 8000288 <__aeabi_dsub>
|
|
800df80: 4652 mov r2, sl
|
|
800df82: 4606 mov r6, r0
|
|
800df84: 460f mov r7, r1
|
|
800df86: 465b mov r3, fp
|
|
800df88: 4650 mov r0, sl
|
|
800df8a: 4659 mov r1, fp
|
|
800df8c: f7f2 fb34 bl 80005f8 <__aeabi_dmul>
|
|
800df90: 4602 mov r2, r0
|
|
800df92: 460b mov r3, r1
|
|
800df94: 4630 mov r0, r6
|
|
800df96: 4639 mov r1, r7
|
|
800df98: f7f2 fb2e bl 80005f8 <__aeabi_dmul>
|
|
800df9c: 4606 mov r6, r0
|
|
800df9e: 460f mov r7, r1
|
|
800dfa0: b914 cbnz r4, 800dfa8 <__ieee754_log+0x130>
|
|
800dfa2: 4632 mov r2, r6
|
|
800dfa4: 463b mov r3, r7
|
|
800dfa6: e0a2 b.n 800e0ee <__ieee754_log+0x276>
|
|
800dfa8: 4620 mov r0, r4
|
|
800dfaa: f7f2 fabb bl 8000524 <__aeabi_i2d>
|
|
800dfae: a374 add r3, pc, #464 ; (adr r3, 800e180 <__ieee754_log+0x308>)
|
|
800dfb0: e9d3 2300 ldrd r2, r3, [r3]
|
|
800dfb4: 4680 mov r8, r0
|
|
800dfb6: 4689 mov r9, r1
|
|
800dfb8: f7f2 fb1e bl 80005f8 <__aeabi_dmul>
|
|
800dfbc: a372 add r3, pc, #456 ; (adr r3, 800e188 <__ieee754_log+0x310>)
|
|
800dfbe: e9d3 2300 ldrd r2, r3, [r3]
|
|
800dfc2: 4604 mov r4, r0
|
|
800dfc4: 460d mov r5, r1
|
|
800dfc6: 4640 mov r0, r8
|
|
800dfc8: 4649 mov r1, r9
|
|
800dfca: f7f2 fb15 bl 80005f8 <__aeabi_dmul>
|
|
800dfce: e0a7 b.n 800e120 <__ieee754_log+0x2a8>
|
|
800dfd0: f04f 4380 mov.w r3, #1073741824 ; 0x40000000
|
|
800dfd4: f7f2 f95a bl 800028c <__adddf3>
|
|
800dfd8: 4602 mov r2, r0
|
|
800dfda: 460b mov r3, r1
|
|
800dfdc: 4650 mov r0, sl
|
|
800dfde: 4659 mov r1, fp
|
|
800dfe0: f7f2 fc34 bl 800084c <__aeabi_ddiv>
|
|
800dfe4: ec41 0b18 vmov d8, r0, r1
|
|
800dfe8: 4620 mov r0, r4
|
|
800dfea: f7f2 fa9b bl 8000524 <__aeabi_i2d>
|
|
800dfee: ec53 2b18 vmov r2, r3, d8
|
|
800dff2: ec41 0b19 vmov d9, r0, r1
|
|
800dff6: ec51 0b18 vmov r0, r1, d8
|
|
800dffa: f7f2 fafd bl 80005f8 <__aeabi_dmul>
|
|
800dffe: f5a5 23c2 sub.w r3, r5, #397312 ; 0x61000
|
|
800e002: f2a3 437a subw r3, r3, #1146 ; 0x47a
|
|
800e006: 9301 str r3, [sp, #4]
|
|
800e008: 4602 mov r2, r0
|
|
800e00a: 460b mov r3, r1
|
|
800e00c: 4680 mov r8, r0
|
|
800e00e: 4689 mov r9, r1
|
|
800e010: f7f2 faf2 bl 80005f8 <__aeabi_dmul>
|
|
800e014: a360 add r3, pc, #384 ; (adr r3, 800e198 <__ieee754_log+0x320>)
|
|
800e016: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e01a: 4606 mov r6, r0
|
|
800e01c: 460f mov r7, r1
|
|
800e01e: f7f2 faeb bl 80005f8 <__aeabi_dmul>
|
|
800e022: a35f add r3, pc, #380 ; (adr r3, 800e1a0 <__ieee754_log+0x328>)
|
|
800e024: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e028: f7f2 f930 bl 800028c <__adddf3>
|
|
800e02c: 4632 mov r2, r6
|
|
800e02e: 463b mov r3, r7
|
|
800e030: f7f2 fae2 bl 80005f8 <__aeabi_dmul>
|
|
800e034: a35c add r3, pc, #368 ; (adr r3, 800e1a8 <__ieee754_log+0x330>)
|
|
800e036: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e03a: f7f2 f927 bl 800028c <__adddf3>
|
|
800e03e: 4632 mov r2, r6
|
|
800e040: 463b mov r3, r7
|
|
800e042: f7f2 fad9 bl 80005f8 <__aeabi_dmul>
|
|
800e046: a35a add r3, pc, #360 ; (adr r3, 800e1b0 <__ieee754_log+0x338>)
|
|
800e048: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e04c: f7f2 f91e bl 800028c <__adddf3>
|
|
800e050: 4642 mov r2, r8
|
|
800e052: 464b mov r3, r9
|
|
800e054: f7f2 fad0 bl 80005f8 <__aeabi_dmul>
|
|
800e058: a357 add r3, pc, #348 ; (adr r3, 800e1b8 <__ieee754_log+0x340>)
|
|
800e05a: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e05e: 4680 mov r8, r0
|
|
800e060: 4689 mov r9, r1
|
|
800e062: 4630 mov r0, r6
|
|
800e064: 4639 mov r1, r7
|
|
800e066: f7f2 fac7 bl 80005f8 <__aeabi_dmul>
|
|
800e06a: a355 add r3, pc, #340 ; (adr r3, 800e1c0 <__ieee754_log+0x348>)
|
|
800e06c: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e070: f7f2 f90c bl 800028c <__adddf3>
|
|
800e074: 4632 mov r2, r6
|
|
800e076: 463b mov r3, r7
|
|
800e078: f7f2 fabe bl 80005f8 <__aeabi_dmul>
|
|
800e07c: a352 add r3, pc, #328 ; (adr r3, 800e1c8 <__ieee754_log+0x350>)
|
|
800e07e: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e082: f7f2 f903 bl 800028c <__adddf3>
|
|
800e086: 4632 mov r2, r6
|
|
800e088: 463b mov r3, r7
|
|
800e08a: f7f2 fab5 bl 80005f8 <__aeabi_dmul>
|
|
800e08e: 460b mov r3, r1
|
|
800e090: 4602 mov r2, r0
|
|
800e092: 4649 mov r1, r9
|
|
800e094: 4640 mov r0, r8
|
|
800e096: f7f2 f8f9 bl 800028c <__adddf3>
|
|
800e09a: f5c5 25d7 rsb r5, r5, #440320 ; 0x6b800
|
|
800e09e: 9b01 ldr r3, [sp, #4]
|
|
800e0a0: 3551 adds r5, #81 ; 0x51
|
|
800e0a2: 431d orrs r5, r3
|
|
800e0a4: 2d00 cmp r5, #0
|
|
800e0a6: 4680 mov r8, r0
|
|
800e0a8: 4689 mov r9, r1
|
|
800e0aa: dd48 ble.n 800e13e <__ieee754_log+0x2c6>
|
|
800e0ac: 4b4e ldr r3, [pc, #312] ; (800e1e8 <__ieee754_log+0x370>)
|
|
800e0ae: 2200 movs r2, #0
|
|
800e0b0: 4650 mov r0, sl
|
|
800e0b2: 4659 mov r1, fp
|
|
800e0b4: f7f2 faa0 bl 80005f8 <__aeabi_dmul>
|
|
800e0b8: 4652 mov r2, sl
|
|
800e0ba: 465b mov r3, fp
|
|
800e0bc: f7f2 fa9c bl 80005f8 <__aeabi_dmul>
|
|
800e0c0: 4602 mov r2, r0
|
|
800e0c2: 460b mov r3, r1
|
|
800e0c4: 4606 mov r6, r0
|
|
800e0c6: 460f mov r7, r1
|
|
800e0c8: 4640 mov r0, r8
|
|
800e0ca: 4649 mov r1, r9
|
|
800e0cc: f7f2 f8de bl 800028c <__adddf3>
|
|
800e0d0: ec53 2b18 vmov r2, r3, d8
|
|
800e0d4: f7f2 fa90 bl 80005f8 <__aeabi_dmul>
|
|
800e0d8: 4680 mov r8, r0
|
|
800e0da: 4689 mov r9, r1
|
|
800e0dc: b964 cbnz r4, 800e0f8 <__ieee754_log+0x280>
|
|
800e0de: 4602 mov r2, r0
|
|
800e0e0: 460b mov r3, r1
|
|
800e0e2: 4630 mov r0, r6
|
|
800e0e4: 4639 mov r1, r7
|
|
800e0e6: f7f2 f8cf bl 8000288 <__aeabi_dsub>
|
|
800e0ea: 4602 mov r2, r0
|
|
800e0ec: 460b mov r3, r1
|
|
800e0ee: 4650 mov r0, sl
|
|
800e0f0: 4659 mov r1, fp
|
|
800e0f2: f7f2 f8c9 bl 8000288 <__aeabi_dsub>
|
|
800e0f6: e6d6 b.n 800dea6 <__ieee754_log+0x2e>
|
|
800e0f8: a321 add r3, pc, #132 ; (adr r3, 800e180 <__ieee754_log+0x308>)
|
|
800e0fa: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e0fe: ec51 0b19 vmov r0, r1, d9
|
|
800e102: f7f2 fa79 bl 80005f8 <__aeabi_dmul>
|
|
800e106: a320 add r3, pc, #128 ; (adr r3, 800e188 <__ieee754_log+0x310>)
|
|
800e108: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e10c: 4604 mov r4, r0
|
|
800e10e: 460d mov r5, r1
|
|
800e110: ec51 0b19 vmov r0, r1, d9
|
|
800e114: f7f2 fa70 bl 80005f8 <__aeabi_dmul>
|
|
800e118: 4642 mov r2, r8
|
|
800e11a: 464b mov r3, r9
|
|
800e11c: f7f2 f8b6 bl 800028c <__adddf3>
|
|
800e120: 4602 mov r2, r0
|
|
800e122: 460b mov r3, r1
|
|
800e124: 4630 mov r0, r6
|
|
800e126: 4639 mov r1, r7
|
|
800e128: f7f2 f8ae bl 8000288 <__aeabi_dsub>
|
|
800e12c: 4652 mov r2, sl
|
|
800e12e: 465b mov r3, fp
|
|
800e130: f7f2 f8aa bl 8000288 <__aeabi_dsub>
|
|
800e134: 4602 mov r2, r0
|
|
800e136: 460b mov r3, r1
|
|
800e138: 4620 mov r0, r4
|
|
800e13a: 4629 mov r1, r5
|
|
800e13c: e7d9 b.n 800e0f2 <__ieee754_log+0x27a>
|
|
800e13e: 4602 mov r2, r0
|
|
800e140: 460b mov r3, r1
|
|
800e142: 4650 mov r0, sl
|
|
800e144: 4659 mov r1, fp
|
|
800e146: f7f2 f89f bl 8000288 <__aeabi_dsub>
|
|
800e14a: ec53 2b18 vmov r2, r3, d8
|
|
800e14e: f7f2 fa53 bl 80005f8 <__aeabi_dmul>
|
|
800e152: 4606 mov r6, r0
|
|
800e154: 460f mov r7, r1
|
|
800e156: 2c00 cmp r4, #0
|
|
800e158: f43f af23 beq.w 800dfa2 <__ieee754_log+0x12a>
|
|
800e15c: a308 add r3, pc, #32 ; (adr r3, 800e180 <__ieee754_log+0x308>)
|
|
800e15e: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e162: ec51 0b19 vmov r0, r1, d9
|
|
800e166: f7f2 fa47 bl 80005f8 <__aeabi_dmul>
|
|
800e16a: a307 add r3, pc, #28 ; (adr r3, 800e188 <__ieee754_log+0x310>)
|
|
800e16c: e9d3 2300 ldrd r2, r3, [r3]
|
|
800e170: 4604 mov r4, r0
|
|
800e172: 460d mov r5, r1
|
|
800e174: ec51 0b19 vmov r0, r1, d9
|
|
800e178: e727 b.n 800dfca <__ieee754_log+0x152>
|
|
800e17a: ed9f 0b15 vldr d0, [pc, #84] ; 800e1d0 <__ieee754_log+0x358>
|
|
800e17e: e694 b.n 800deaa <__ieee754_log+0x32>
|
|
800e180: fee00000 .word 0xfee00000
|
|
800e184: 3fe62e42 .word 0x3fe62e42
|
|
800e188: 35793c76 .word 0x35793c76
|
|
800e18c: 3dea39ef .word 0x3dea39ef
|
|
800e190: 55555555 .word 0x55555555
|
|
800e194: 3fd55555 .word 0x3fd55555
|
|
800e198: df3e5244 .word 0xdf3e5244
|
|
800e19c: 3fc2f112 .word 0x3fc2f112
|
|
800e1a0: 96cb03de .word 0x96cb03de
|
|
800e1a4: 3fc74664 .word 0x3fc74664
|
|
800e1a8: 94229359 .word 0x94229359
|
|
800e1ac: 3fd24924 .word 0x3fd24924
|
|
800e1b0: 55555593 .word 0x55555593
|
|
800e1b4: 3fe55555 .word 0x3fe55555
|
|
800e1b8: d078c69f .word 0xd078c69f
|
|
800e1bc: 3fc39a09 .word 0x3fc39a09
|
|
800e1c0: 1d8e78af .word 0x1d8e78af
|
|
800e1c4: 3fcc71c5 .word 0x3fcc71c5
|
|
800e1c8: 9997fa04 .word 0x9997fa04
|
|
800e1cc: 3fd99999 .word 0x3fd99999
|
|
...
|
|
800e1d8: c3500000 .word 0xc3500000
|
|
800e1dc: 43500000 .word 0x43500000
|
|
800e1e0: 7fefffff .word 0x7fefffff
|
|
800e1e4: 3ff00000 .word 0x3ff00000
|
|
800e1e8: 3fe00000 .word 0x3fe00000
|
|
800e1ec: 00000000 .word 0x00000000
|
|
|
|
0800e1f0 <nan>:
|
|
800e1f0: ed9f 0b01 vldr d0, [pc, #4] ; 800e1f8 <nan+0x8>
|
|
800e1f4: 4770 bx lr
|
|
800e1f6: bf00 nop
|
|
800e1f8: 00000000 .word 0x00000000
|
|
800e1fc: 7ff80000 .word 0x7ff80000
|
|
|
|
0800e200 <_init>:
|
|
800e200: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800e202: bf00 nop
|
|
800e204: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800e206: bc08 pop {r3}
|
|
800e208: 469e mov lr, r3
|
|
800e20a: 4770 bx lr
|
|
|
|
0800e20c <_fini>:
|
|
800e20c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800e20e: bf00 nop
|
|
800e210: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800e212: bc08 pop {r3}
|
|
800e214: 469e mov lr, r3
|
|
800e216: 4770 bx lr
|